ENGR00286345 [iMX6DL] Fixed random hang bug in bus freq driver

Incorrect clock disable of PLL2 caused random hangs during
DDR freq change in iMX6DL.
Remove PERCLK freq change code as this is not required for TO1.1
and later.

Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>

2 files changed, 4 insertions, 34 deletions

diff --git a/arch/arm/mach-imx/busfreq-imx6.c b/arch/arm/mach-imx/busfreq-imx6.c
index a32b1d25fbc1..bc9265293477 100644
--- a/arch/arm/mach-imx/busfreq-imx6.c
+++ b/arch/arm/mach-imx/busfreq-imx6.c
@@ -48,7 +48,8 @@
 #include "hardware.h"
 
 #define LPAPM_CLK		24000000
-#define DDR_AUDIO_CLK		100000000
+#define DDR3_AUDIO_CLK		50000000
+#define LPDDR2_AUDIO_CLK	100000000
 
 int high_bus_freq_mode;
 int med_bus_freq_mode;
@@ -114,7 +115,7 @@ static void enter_lpm_imx6sl(void)
 	if (audio_bus_count) {
 		/* Set up DDR to 100MHz. */
 		spin_lock_irqsave(&freq_lock, flags);
-		update_lpddr2_freq(DDR_AUDIO_CLK);
+		update_lpddr2_freq(LPDDR2_AUDIO_CLK);
 		spin_unlock_irqrestore(&freq_lock, flags);
 
 		/* Fix the clock tree in kernel */
@@ -245,7 +246,7 @@ int reduce_bus_freq(void)
 		if (audio_bus_count) {
 			/* Need to ensure that PLL2_PFD_400M is kept ON. */
 			clk_prepare_enable(pll2_400);
-			update_ddr_freq(DDR_AUDIO_CLK);
+			update_ddr_freq(DDR3_AUDIO_CLK);
 			/* Make sure periph clk's parent also got updated */
 			ret = clk_set_parent(periph_clk2_sel, pll3);
 			if (ret)
@@ -283,9 +284,6 @@ int reduce_bus_freq(void)
 			low_bus_freq_mode = 1;
 			audio_bus_freq_mode = 0;
 		}
-		if (high_bus_freq_mode && cpu_is_imx6dl())
-			clk_disable_unprepare(pll2_400);
-
 	}
 	clk_disable_unprepare(pll3);
 
diff --git a/arch/arm/mach-imx/ddr3_freq_imx6.S b/arch/arm/mach-imx/ddr3_freq_imx6.S
index e7e67ce34382..699f32fbe118 100644
--- a/arch/arm/mach-imx/ddr3_freq_imx6.S
+++ b/arch/arm/mach-imx/ddr3_freq_imx6.S
@@ -64,7 +64,6 @@
 	 * set the AHB dividers before the switch,
 	 * don't change AXI clock divider,
 	 * set the MMDC_DIV=1, AXI_DIV = 2, AHB_DIV=4,
-	 * (need to maintain GPT divider).
 	 */
 	ldr	r0, [r6, #CCM_CBCDR]
 	ldr	r2, =0x3f1f00
@@ -93,7 +92,6 @@ periph_clk_switch3:
 set_ahb_podf_before_switch:
 	/*
 	 * set the MMDC_DIV=1, AXI_DIV = 2, AHB_DIV=4,
-	 * (need to maintain GPT divider).
 	 */
 	ldr	r0, [r6, #CCM_CBCDR]
 	ldr	r2, =0x3f1f00
@@ -124,11 +122,6 @@ periph_clk_switch4:
 	cmp	r0, #0
 	bne	periph_clk_switch4
 
-	/* change the perclk divider so that its at 6MHz. */
-	ldr	r0, [r6, #CCM_CSCMR1]
-	bic	r0, r0, #0x3F
-	orr	r0, r0, #0xA
-	str	r0, [r6, #CCM_CSCMR1]
 	.endm
 
 	.macro	switch_to_400MHz
@@ -163,7 +156,6 @@ periph_clk_switch5:
 set_ahb_podf_before_switch1:
 	/*
 	 * set the MMDC_DIV=1, AXI_DIV = 2, AHB_DIV=4,
-	 * (need to maintain GPT divider).
 	 */
 	ldr	r0, [r6, #CCM_CBCDR]
 	ldr	r2, =0x3f1f00
@@ -199,7 +191,6 @@ periph_clk_switch6:
 	 * change AHB divider so that we are at 400/3=133MHz.
 	 * don't change AXI clock divider.
 	 * set the MMDC_DIV=1, AXI_DIV=2, AHB_DIV=3,
-	 * (need to maintain GPT divider).
 	 */
 	ldr	r0, [r6, #CCM_CBCDR]
 	ldr	r2, =0x3f1f00
@@ -213,12 +204,6 @@ wait_div_update400_2:
 	cmp	r0, #0
 	bne	wait_div_update400_2
 
-	/* change the perclk divider so that its at 6MHz. */
-	ldr	r0, [r6, #CCM_CSCMR1]
-	bic	r0, r0, #0x3F
-	orr	r0, r0, #0xA
-	str	r0, [r6, #CCM_CSCMR1]
-
 	.endm
 
 	.macro	switch_to_50MHz
@@ -261,7 +246,6 @@ switch_pre_periph_clk_50:
 
 	/*
 	 * set the MMDC_DIV=4, AXI_DIV = 4, AHB_DIV=8,
-	 * (need to maintain GPT divider).
 	 */
 	ldr	r0, [r6, #CCM_CBCDR]
 	ldr	r2, =0x3f1f00
@@ -291,12 +275,6 @@ periph_clk_switch2:
 	cmp	r0, #0
 	bne	periph_clk_switch2
 
-	/* change the perclk divider so that its at 6MHz. */
-	ldr	r0, [r6, #CCM_CSCMR1]
-	bic	r0, r0, #0x3F
-	orr	r0, r0, #0x1
-	str	r0, [r6, #CCM_CSCMR1]
-
 	.endm
 
 	.macro	switch_to_24MHz
@@ -339,12 +317,6 @@ wait_div_update:
 	cmp	r0, #0
 	bne	wait_div_update
 
-	/* change the perclk divider so that its at 6MHz. */
-	ldr	r0, [r6, #CCM_CSCMR1]
-	bic	r0, r0, #0x3F
-	orr	r0, r0, #0x1
-	str	r0, [r6, #CCM_CSCMR1]
-
 	.endm
 
 /*