diff options
| author | Ranjani Vaidyanathan <ra5478@freescale.com> | 2011-06-21 12:54:09 -0500 |
|---|---|---|
| committer | Jason Liu <r64343@freescale.com> | 2012-07-20 13:14:12 +0800 |
| commit | eb8c7e47449aaf1277d0ab2ebddd41fec2a49a8b (patch) | |
| tree | 3c231f9c6fcbc430ee12da84eab5a7937e0f4035 /arch | |
| parent | baa5ed8ea94b37d3efb70a918efd2628cab92b9c (diff) | |
ENGR00151891: MX50-Fix bug in exit from LPAPM mode.
When exiting from LPAPM mode, ARM clock is run at 266.67MHZ for
a few instructions while the voltage is still at 0.85V.
Fix this issue by setting the ARM-PODF divider before
switching the parent.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
Diffstat (limited to 'arch')
| -rwxr-xr-x | arch/arm/mach-mx5/bus_freq.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/arch/arm/mach-mx5/bus_freq.c b/arch/arm/mach-mx5/bus_freq.c index c94cf55ae5ff..b5d151e49e6f 100755 --- a/arch/arm/mach-mx5/bus_freq.c +++ b/arch/arm/mach-mx5/bus_freq.c @@ -498,10 +498,12 @@ void exit_lpapm_mode_mx50(int high_bus_freq) __raw_writel(0x02, MXC_CCM_CACRR); clk_set_rate(pll1, cpu_op_tbl[0].pll_rate); - clk_set_parent(pll1_sw_clk, pll1); - /* Set the divider to ARM_PODF to 5. */ + /* Set the divider to ARM_PODF to 5 before + * switching the parent. + */ __raw_writel(0x4, MXC_CCM_CACRR); + clk_set_parent(pll1_sw_clk, pll1); } if (!completion_done(&voltage_change_cmpl)) |