diff options
| author | Alex Frid <afrid@nvidia.com> | 2012-08-24 23:40:00 -0700 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2013-09-14 12:32:40 -0700 |
| commit | d0c3de16438592f9243c3b4ea908d48728e4f261 (patch) | |
| tree | 2aa8486c036b466658dd008c0c6cd170c495ddee /arch | |
| parent | 69584643f160da3affd71ed6194a37a4feb96830 (diff) | |
ARM: tegra11: dvfs: Add cvb maximum voltage limit
Added maximum voltage entry to cvb data. It will be filled in based
on reliability data. This settings affect
(a) maximum cpu frequency in dfll clock source mode
(b) nominal (maximum) cpu voltage in pll clock source mode
In case (a) voltage is controlled automatically by CL-DVFS, and
cvb maximum voltage limit is applied implicitly by capping frequency
target. In case (b) voltage limit is explicitly checked by s/w legacy
DVFS. Depending on actual SoC data, this voltage boundary may prevent
reaching maximum dfll frequency in pll mode.
Change-Id: Ice7b0cd45302b8d29d2a40491701070b8cd74d3c
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/127369
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>
Rebase-Id: R047784202b93e7dfe24ce5e3eabcea00af06685c
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-tegra/dvfs.h | 1 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/tegra11_dvfs.c | 7 |
2 files changed, 7 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/dvfs.h b/arch/arm/mach-tegra/dvfs.h index 6fe33620a19b..9e16b1dd3652 100644 --- a/arch/arm/mach-tegra/dvfs.h +++ b/arch/arm/mach-tegra/dvfs.h @@ -109,6 +109,7 @@ struct cpu_cvb_dvfs_parameters { struct cpu_cvb_dvfs { int speedo_id; + int max_mv; int min_mv; int margin; struct cpu_cvb_dvfs_parameters cvb_table[MAX_DVFS_FREQS]; diff --git a/arch/arm/mach-tegra/tegra11_dvfs.c b/arch/arm/mach-tegra/tegra11_dvfs.c index c7f3108aec86..05805129014b 100644 --- a/arch/arm/mach-tegra/tegra11_dvfs.c +++ b/arch/arm/mach-tegra/tegra11_dvfs.c @@ -62,6 +62,7 @@ static struct dvfs_rail *tegra11_dvfs_rails[] = { static struct cpu_cvb_dvfs cpu_cvb_dvfs_table[] = { { .speedo_id = 0, + .max_mv = 1150, .min_mv = 850, .margin = 103, .cvb_table = { @@ -387,6 +388,8 @@ static int __init set_cpu_dvfs_data(int speedo_id, struct dvfs *cpu_dvfs, mv = get_cvb_voltage(speedo, cvb); dfll_mv = round_cvb_voltage(mv); dfll_mv = max(dfll_mv, d->min_mv); + if (dfll_mv > d->max_mv) + break; /* Check maximum frequency at minimum voltage */ if (dfll_mv > d->min_mv) { @@ -416,8 +419,10 @@ static int __init set_cpu_dvfs_data(int speedo_id, struct dvfs *cpu_dvfs, return -ENOENT; } + /* dvfs tables are successfully populated - fill in the rest */ cpu_dvfs->speedo_id = speedo_id; - cpu_dvfs->dvfs_rail->nominal_millivolts = cpu_millivolts[j - 1]; + cpu_dvfs->dvfs_rail->nominal_millivolts = + min(cpu_millivolts[j - 1], d->max_mv); *max_freq_index = j - 1; dfll_data->out_rate_min = fmax_at_vmin * MHZ; |