ENGR00143799 Add SCC RAM clock to dependency list for SAHARA clock tree

When ARM is in WAIT mode, the SCC RAM clock is disabled since
1 is written to the CCGR register by default. At that point, if SAHARA
tries to access a key or some other piece of data stored in the SCC RAM,
then it might hang.

To prevent this scenario, SCC RAM is added to dependency list
for SCC clock, and SCC clock is added to dependency list for SAHARA.

Signed-off-by: Anish Trivedi <anish@freescale.com>

1 files changed, 17 insertions, 9 deletions

diff --git a/arch/arm/mach-mx5/clock.c b/arch/arm/mach-mx5/clock.c
index 72f6ff0303d0..46c81493c59b 100644
--- a/arch/arm/mach-mx5/clock.c
+++ b/arch/arm/mach-mx5/clock.c
@@ -4008,32 +4008,40 @@ static struct clk fec_clk[] = {
 	},
 };
 
-static struct clk sahara_clk[] = {
+static struct clk scc_clk[] = {
 	{
 	.parent = &ahb_clk,
-	.secondary = &sahara_clk[1],
-	.enable_reg = MXC_CCM_CCGR4,
-	.enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
+	.secondary = &scc_clk[1],
+	.enable_reg = MXC_CCM_CCGR1,
+	.enable_shift = MXC_CCM_CCGRx_CG15_OFFSET,
 	.enable = _clk_enable,
 	.disable = _clk_disable,
 	},
 	{
 	.parent = &tmax1_clk,
-	.secondary = &emi_fast_clk,
+	.secondary = &scc_clk[2],
+	},
+	{
+	.parent = &emi_fast_clk,
+	.secondary = &emi_intr_clk[0],
 	}
 };
 
-static struct clk scc_clk[] = {
+static struct clk sahara_clk[] = {
 	{
 	.parent = &ahb_clk,
-	.secondary = &scc_clk[1],
-	.enable_reg = MXC_CCM_CCGR1,
-	.enable_shift = MXC_CCM_CCGRx_CG15_OFFSET,
+	.secondary = &sahara_clk[1],
+	.enable_reg = MXC_CCM_CCGR4,
+	.enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
 	.enable = _clk_enable,
 	.disable = _clk_disable,
 	},
 	{
 	.parent = &tmax1_clk,
+	.secondary = &sahara_clk[2],
+	},
+	{
+	.parent = &scc_clk,
 	.secondary = &emi_fast_clk,
 	}
 };