diff options
| author | Anson Huang <b20788@freescale.com> | 2015-04-08 13:50:41 +0800 |
|---|---|---|
| committer | guoyin.chen <guoyin.chen@freescale.com> | 2015-05-08 17:26:12 +0800 |
| commit | f2d9298fd60b744820ed8a53ea9081c52ef3d812 (patch) | |
| tree | e736e6694c143dba072e1fb3d8338dd94f2f1d8f /arch | |
| parent | 0c43b58c5b9396c709ebcae6280020287faa7601 (diff) | |
MLK-10595-2 ARM: imx: add d-cache flush before DSM
Before entering DSM, better to flush all L1 d-cache
to main memory, as cache power will be off in DSM.
Signed-off-by: Anson Huang <b20788@freescale.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-imx/suspend-imx7.S | 37 |
1 files changed, 29 insertions, 8 deletions
diff --git a/arch/arm/mach-imx/suspend-imx7.S b/arch/arm/mach-imx/suspend-imx7.S index cb5a1b413df9..b5a541befbf5 100644 --- a/arch/arm/mach-imx/suspend-imx7.S +++ b/arch/arm/mach-imx/suspend-imx7.S @@ -87,6 +87,33 @@ .align 3 + .macro disable_l1_dcache + + /* + * Flush all data from the L1 data cache before disabling + * SCTLR.C bit. + */ + push {r0 - r10, lr} + ldr r7, =v7_flush_dcache_all + mov lr, pc + mov pc, r7 + pop {r0 - r10, lr} + + /* disable d-cache */ + mrc p15, 0, r7, c1, c0, 0 + bic r7, r7, #(1 << 2) + mcr p15, 0, r7, c1, c0, 0 + dsb + isb + + push {r0 - r10, lr} + ldr r7, =v7_flush_dcache_all + mov lr, pc + mov pc, r7 + pop {r0 - r10, lr} + + .endm + .macro store_ttbr1 /* Store TTBR1 to pm_info->ttbr1 */ @@ -121,14 +148,6 @@ ldr r6, =0x0 mcr p15, 0, r6, c8, c3, 0 - /* Disable L1 data cache. */ - mrc p15, 0, r6, c1, c0, 0 - bic r6, r6, #0x4 - mcr p15, 0, r6, c1, c0, 0 - - dsb - isb - .endm .macro restore_ttbr1 @@ -446,6 +465,8 @@ ENTRY(imx7_suspend) str r9, [r11, #MX7_SRC_GPR1] str r1, [r11, #MX7_SRC_GPR2] + disable_l1_dcache + store_ttbr1 ldr r11, [r0, #PM_INFO_MX7_DDRC_V_OFFSET] |