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authorOliver Brown <oliver.brown@nxp.com>2018-08-02 07:51:26 -0500
committerLeonard Crestez <leonard.crestez@nxp.com>2018-08-24 12:41:33 +0300
commitf7c1b76a67a47ea366d5325f502781518d61af37 (patch)
tree6dcff130a7004c6db25ef54a70b63312f3bededa /arch
parent6dd171a75fcabc7a7dd705968f6f06a30f6f3b7a (diff)
MLK-19119 arm64: dts: imx8qm: Correct bus clock for HDMI Interrupt Steer
The Local Interrupt Steer Clock Bus Clock (LIS IPG) should be 83.375 MHz. Signed-off-by: Oliver Brown <oliver.brown@nxp.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi
index e9e17cd86239..a6f609057b13 100644
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi
@@ -2736,7 +2736,7 @@
clock-names = "ipg";
assigned-clocks = <&clk IMX8QM_HDMI_DIG_PLL_CLK>,
<&clk IMX8QM_HDMI_LIS_IPG_CLK>;
- assigned-clock-rates = <675000000>, <85000000>;
+ assigned-clock-rates = <675000000>, <84375000>;
power-domains = <&pd_hdmi>;
};