ENGR00181390-1: qspi: Add platform support for Quad SPI driver

Add platform support for Quad SPI driver.

Signed-off-by: Alison Wang <b18965@freescale.com>
               Xiaochun Li <b41219@freescale.com>

7 files changed, 392 insertions, 1 deletions

diff --git a/arch/arm/mach-mvf/board-twr-vf700.c b/arch/arm/mach-mvf/board-twr-vf700.c
index af8836a783a1..b79b40e2ffb7 100644
--- a/arch/arm/mach-mvf/board-twr-vf700.c
+++ b/arch/arm/mach-mvf/board-twr-vf700.c
@@ -189,6 +189,20 @@ static iomux_v3_cfg_t mvf600_pads[] = {
 
 	/* Touch Screen */
 	MVF600_PAD21_PTA31_TS_IRQ,
+
+	/* Quad SPI */
+	MVF600_PAD79_PTD0_QSPI0_A_SCK,
+	MVF600_PAD80_PTD1_QSPI0_A_CS0,
+	MVF600_PAD81_PTD2_QSPI0_A_D3,
+	MVF600_PAD82_PTD3_QSPI0_A_D2,
+	MVF600_PAD83_PTD4_QSPI0_A_D1,
+	MVF600_PAD84_PTD5_QSPI0_A_D0,
+	MVF600_PAD86_PTD7_QSPI0_B_SCK,
+	MVF600_PAD87_PTD8_QSPI0_B_CS0,
+	MVF600_PAD88_PTD9_QSPI0_B_D3,
+	MVF600_PAD89_PTD10_QSPI0_B_D2,
+	MVF600_PAD90_PTD11_QSPI0_B_D1,
+	MVF600_PAD91_PTD12_QSPI0_B_D0,
 };
 
 static struct mxc_audio_platform_data mvf_twr_audio_data;
@@ -256,6 +270,18 @@ static const struct spi_mvf_master mvf_vf600_spi_data __initconst = {
 	.cs_control = NULL,
 };
 
+static int mvf_vf600_qspi_cs[] = {
+	80,
+	87,
+};
+
+static const struct spi_mvf_master mvf_vf600_qspi_data __initconst = {
+	.bus_num = 0,
+	.chipselect = mvf_vf600_qspi_cs,
+	.num_chipselect = ARRAY_SIZE(mvf_vf600_qspi_cs),
+	.cs_control = NULL,
+};
+
 #if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
 static struct mtd_partition at26df081a_partitions[] = {
 	{
@@ -287,10 +313,37 @@ static struct spi_mvf_chip at26df081a_chip_info = {
 	.asc = 0,
 	.dt = 0,
 };
+
+static struct mtd_partition s25fl256s_partitions[] = {
+	{
+		.name = "s25fl256s",
+		.size = (1024 * 64 * 256),
+		.offset = 0x00000000,
+		.mask_flags = 0,
+	}
+};
+
+static struct flash_platform_data s25fl256s_spi_flash_data = {
+	.name = "Spansion s25fl128s SPI Flash chip",
+	.parts = s25fl256s_partitions,
+	.nr_parts = ARRAY_SIZE(s25fl256s_partitions),
+	.type = "s25fl128s",
+};
 #endif
 
 static struct spi_board_info mvf_spi_board_info[] __initdata = {
 #if defined(CONFIG_MTD_M25P80)
+#if defined(CONFIG_SPI_MVF_QSPI)
+	{
+		/* The modalias must be the same as spi device driver name */
+		.modalias = "m25p80",
+		.max_speed_hz = 20000000,
+		.bus_num = 0,
+		.chip_select = 0,
+		.platform_data = &s25fl256s_spi_flash_data,
+	},
+#endif
+#if defined(CONFIG_SPI_MVF)
 	{
 		/* The modalias must be the same as spi device driver name */
 		.modalias = "m25p80",
@@ -301,7 +354,9 @@ static struct spi_board_info mvf_spi_board_info[] __initdata = {
 		.controller_data = &at26df081a_chip_info
 	},
 #endif
+#endif
 };
+
 static void spi_device_init(void)
 {
 	spi_register_board_info(mvf_spi_board_info,
@@ -403,6 +458,7 @@ static void __init mvf_board_init(void)
 			ARRAY_SIZE(mxc_i2c0_board_info));
 
 	mvf_add_dspi(0, &mvf_vf600_spi_data);
+	mvf_add_qspi(0, &mvf_vf600_qspi_data);
 	spi_device_init();
 
 	mvfa5_add_dcu(0, &mvf_dcu_pdata);
diff --git a/arch/arm/mach-mvf/clock.c b/arch/arm/mach-mvf/clock.c
index 9340d121d25e..0541ee92ac9c 100644
--- a/arch/arm/mach-mvf/clock.c
+++ b/arch/arm/mach-mvf/clock.c
@@ -48,6 +48,7 @@ static struct clk pll4_audio_main_clk;
 static struct clk pll6_video_main_clk;
 static struct clk pll5_enet_main_clk;
 static struct clk pll1_pfd3_396M;
+static struct clk pll1_pfd4_528M;
 
 unsigned long arm_core_clk = 396000000; /* cpu core clk, up to 452MHZ */
 unsigned long arm_sys_clk = 396000000; /* ARM_CLK_DIV, system bus clock */
@@ -157,6 +158,8 @@ static inline void __iomem *_get_pll_base(struct clk *pll)
 		return PLL6_VIDEO_BASE_ADDR;
 	else if (pll == &pll1_pfd3_396M)
 		return PLL1_SYS_BASE_ADDR;
+	else if (pll == &pll1_pfd4_528M)
+		return PLL1_SYS_BASE_ADDR;
 	else
 		BUG();
 	return NULL;
@@ -455,6 +458,15 @@ static int _clk_pll1_pfd3_set_rate(struct clk *clk, unsigned long rate)
 	return 0;
 }
 
+static unsigned long _clk_pll1_pfd4_get_rate(struct clk *clk)
+{
+	return 528000000;
+}
+
+static int _clk_pll1_pfd4_set_rate(struct clk *clk, unsigned long rate)
+{
+	return 0;
+}
 static struct clk pll1_sys_main_clk = {
 	__INIT_CLK_DEBUG(pll1_sys_main_clk)
 	.parent = &osc_clk,
@@ -486,6 +498,17 @@ static struct clk pll1_pfd3_396M = {
 	.disable = _clk_pfd_disable,
 };
 
+static struct clk pll1_pfd4_528M = {
+	__INIT_CLK_DEBUG(pll1_pfd4_528M)
+	.parent = &osc_clk,
+	.enable_reg = (void *)PFD_528SYS_BASE_ADDR,
+	.enable_shift = ANADIG_PFD3_FRAC_OFFSET,
+	.get_rate = _clk_pll1_pfd4_get_rate,
+	.set_rate = _clk_pll1_pfd4_set_rate,
+	.enable = _clk_pfd_enable,
+	.disable = _clk_pfd_disable,
+};
+
 /*
  * PLL PFD output select
  * CCM Clock Switcher Register
@@ -508,7 +531,9 @@ static int _clk_pll1_sw_set_parent(struct clk *clk, struct clk *parent)
 	} else if (parent == &pll1_pfd3_396M) {
 		reg &= ~MXC_CCM_CCSR_PLL1_PFD_CLK_SEL_MASK;
 		reg |= (0x3 << MXC_CCM_CCSR_PLL1_PFD_CLK_SEL_OFFSET);
-
+	} else if (parent == &pll1_pfd4_528M) {
+		reg &= ~MXC_CCM_CCSR_PLL1_PFD_CLK_SEL_MASK;
+		reg |= (0x4 << MXC_CCM_CCSR_PLL1_PFD_CLK_SEL_OFFSET);
 	}
 	__raw_writel(reg, MXC_CCM_CCSR);
 	return 0;
@@ -1640,6 +1665,147 @@ static struct clk ftm_pwm_clk = {
 
 };
 
+static int _clk_qspi0_set_parent(struct clk *clk, struct clk *parent)
+{
+	int mux;
+	u32 reg = __raw_readl(MXC_CCM_CSCMR1)
+		& ~MXC_CCM_CSCMR1_QSPI0_CLK_SEL_MASK;
+
+	mux = _get_mux6(parent, &pll3_usb_otg_main_clk, &pll3_pfd4_320M,
+		&pll2_pfd4_413M, &pll1_pfd4_528M, NULL, NULL);
+
+	reg |= (mux << MXC_CCM_CSCMR1_QSPI0_CLK_SEL_OFFSET);
+
+	__raw_writel(reg, MXC_CCM_CSCMR1);
+
+	return 0;
+}
+
+static int _clk_qspi1_set_parent(struct clk *clk, struct clk *parent)
+{
+	int mux;
+	u32 reg = __raw_readl(MXC_CCM_CSCMR1)
+		& ~MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK;
+
+	mux = _get_mux6(parent, &pll3_usb_otg_main_clk, &pll3_pfd4_320M ,
+		&pll2_pfd4_413M, &pll1_pfd4_528M, NULL, NULL);
+
+	reg |= (mux << MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET);
+
+	__raw_writel(reg, MXC_CCM_CSCMR1);
+
+	return 0;
+}
+
+static unsigned long _clk_qspi0_get_rate(struct clk *clk)
+{
+	u32 reg, div4, div2, div;
+
+	reg = __raw_readl(MXC_CCM_CSCDR3);
+	div4 = ((reg & MXC_CCM_CSCDR3_QSPI0_X4_DIV_MASK) >>
+			MXC_CCM_CSCDR3_QSPI0_X4_DIV_OFFSET) + 1;
+
+	div2 = ((reg & MXC_CCM_CSCDR3_QSPI0_X2_DIV_MASK) >>
+			MXC_CCM_CSCDR3_QSPI0_X2_DIV_OFFSET) + 1;
+
+	div = ((reg & MXC_CCM_CSCDR3_QSPI0_DIV_MASK) >>
+			MXC_CCM_CSCDR3_QSPI0_DIV_OFFSET) + 1;
+
+	return clk_get_rate(clk->parent) / div4 / div2 / div;
+}
+
+static unsigned long _clk_qspi1_get_rate(struct clk *clk)
+{
+	u32 reg, div4, div2, div;
+
+	reg = __raw_readl(MXC_CCM_CSCDR3);
+	div4 = ((reg & MXC_CCM_CSCDR3_QSPI1_X4_DIV_MASK) >>
+			MXC_CCM_CSCDR3_QSPI1_X4_DIV_OFFSET) + 1;
+
+	div2 = ((reg & MXC_CCM_CSCDR3_QSPI1_X2_DIV_MASK) >>
+			MXC_CCM_CSCDR3_QSPI1_X2_DIV_OFFSET) + 1;
+
+	div = ((reg & MXC_CCM_CSCDR3_QSPI1_DIV_MASK) >>
+			MXC_CCM_CSCDR3_QSPI1_DIV_OFFSET) + 1;
+
+	return clk_get_rate(clk->parent) / div4 / div2 / div;
+}
+
+static int _clk_qspi0_set_rate(struct clk *clk, unsigned long rate)
+{
+	u32 reg, div;
+	u32 parent_rate = clk_get_rate(clk->parent);
+
+	reg = __raw_readl(MXC_CCM_CSCDR3);
+	reg &= ~MXC_CCM_CSCDR3_QSPI0_X4_DIV_MASK;
+	reg |= 0x1 << MXC_CCM_CSCDR3_QSPI0_X4_DIV_OFFSET;
+
+	reg &= ~MXC_CCM_CSCDR3_QSPI0_X2_DIV_MASK;
+	reg |= 0x01 << MXC_CCM_CSCDR3_QSPI0_X2_DIV_OFFSET;
+
+	reg &= ~MXC_CCM_CSCDR3_QSPI0_DIV_MASK;
+	reg |= 0x01 << MXC_CCM_CSCDR3_QSPI0_DIV_OFFSET;
+
+	reg |= MXC_CCM_CSCDR3_QSPI0_EN;
+	__raw_writel(reg, MXC_CCM_CSCDR3);
+
+	return 0;
+}
+
+static int _clk_qspi1_set_rate(struct clk *clk, unsigned long rate)
+{
+	u32 reg, div;
+	u32 parent_rate = clk_get_rate(clk->parent);
+
+	reg = __raw_readl(MXC_CCM_CSCDR3);
+	reg &= ~MXC_CCM_CSCDR3_QSPI1_X4_DIV_MASK;
+	reg |= 0x1 << MXC_CCM_CSCDR3_QSPI1_X4_DIV_OFFSET;
+
+	reg &= ~MXC_CCM_CSCDR3_QSPI1_X2_DIV_MASK;
+	reg |= 0x01 << MXC_CCM_CSCDR3_QSPI1_X2_DIV_OFFSET;
+
+	reg &= ~MXC_CCM_CSCDR3_QSPI1_DIV_MASK;
+	reg |= 0x01 << MXC_CCM_CSCDR3_QSPI1_DIV_OFFSET;
+
+	reg |= MXC_CCM_CSCDR3_QSPI1_EN;
+	__raw_writel(reg, MXC_CCM_CSCDR3);
+
+	return 0;
+}
+
+static unsigned long _clk_qspi_round_rate(struct clk *clk, unsigned long rate)
+{
+	return 66000000;
+}
+
+static struct clk qspi0_clk = {
+	__INIT_CLK_DEBUG(qspi0_clk)
+	.id = 0,
+	.parent = &pll1_pfd4_528M,
+	.enable_reg = MXC_CCM_CCGR2,
+	.enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
+	.enable = _clk_enable,
+	.disable = _clk_disable,
+	.set_parent = _clk_qspi0_set_parent,
+	.round_rate = _clk_qspi_round_rate,
+	.set_rate = _clk_qspi0_set_rate,
+	.get_rate = _clk_qspi0_get_rate,
+};
+
+static struct clk qspi1_clk = {
+	__INIT_CLK_DEBUG(quadspi1_clk)
+	.id = 1,
+	.parent = &pll1_pfd4_528M,
+	.enable_reg = MXC_CCM_CCGR8,
+	.enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
+	.enable = _clk_enable,
+	.disable = _clk_disable,
+	.set_parent = _clk_qspi1_set_parent,
+	.round_rate = _clk_qspi_round_rate,
+	.set_rate = _clk_qspi1_set_rate,
+	.get_rate = _clk_qspi1_get_rate,
+};
+
 static struct clk dummy_clk = {
 	.id = 0,
 };
@@ -1660,6 +1826,7 @@ static struct clk_lookup lookups[] = {
 	_REGISTER_CLOCK(NULL, "pll1_main_clk", pll1_sys_main_clk),
 	_REGISTER_CLOCK(NULL, "pll1_pfd2_452M", pll1_pfd2_452M),
 	_REGISTER_CLOCK(NULL, "pll1_pfd3_396M", pll1_pfd3_396M),
+	_REGISTER_CLOCK(NULL, "pll1_pfd4_528M", pll1_pfd4_528M),
 	_REGISTER_CLOCK(NULL, "pll1_sw_clk", pll1_sw_clk), /*PLL1 pfd out clk*/
 	_REGISTER_CLOCK(NULL, "pll2_main_clk", pll2_528_bus_main_clk),
 	_REGISTER_CLOCK(NULL, "pll2_pfd2_396M", pll2_pfd2_396M),
@@ -1692,6 +1859,7 @@ static struct clk_lookup lookups[] = {
 	_REGISTER_CLOCK(NULL, "mvf-usb.0", usb_phy0_clk),
 	_REGISTER_CLOCK(NULL, "mvf-usb.1", usb_phy1_clk),
 	_REGISTER_CLOCK(NULL, "pwm", ftm_pwm_clk),
+	_REGISTER_CLOCK("mvf-qspi.0", NULL, qspi0_clk),
 };
 
 static void clk_tree_init(void)
@@ -1763,6 +1931,8 @@ int __init mvf_clocks_init(unsigned long ckil, unsigned long osc,
 	clk_set_parent(&sai2_clk, &audio_external_clk);
 	clk_set_rate(&sai2_clk, 24576000);
 
+	clk_set_parent(&qspi0_clk, &pll1_pfd4_528M);
+	clk_set_rate(&qspi0_clk, 66000000);
 	return 0;
 
 }
diff --git a/arch/arm/mach-mvf/crm_regs.h b/arch/arm/mach-mvf/crm_regs.h
index 744dbfff2165..78604eb96447 100644
--- a/arch/arm/mach-mvf/crm_regs.h
+++ b/arch/arm/mach-mvf/crm_regs.h
@@ -369,11 +369,19 @@
 #define MXC_CCM_CSCDR3_QSPI1_EN			(0x1 << 12)
 #define MXC_CCM_CSCDR3_QSPI1_DIV		(0x1 << 11)
 #define MXC_CCM_CSCDR3_QSPI1_X2_DIV		(0x1 << 10)
+#define MXC_CCM_CSCDR3_QSPI1_DIV_OFFSET		(11)
+#define MXC_CCM_CSCDR3_QSPI1_DIV_MASK		(0x1 << 11)
+#define MXC_CCM_CSCDR3_QSPI1_X2_DIV_OFFSET	(10)
+#define MXC_CCM_CSCDR3_QSPI1_X2_DIV_MASK	(0x1 << 10)
 #define MXC_CCM_CSCDR3_QSPI1_X4_DIV_MASK	(0x3 << 8)
 #define MXC_CCM_CSCDR3_QSPI1_X4_DIV_OFFSET	(8)
 #define MXC_CCM_CSCDR3_QSPI0_EN			(0x1 << 4)
 #define MXC_CCM_CSCDR3_QSPI0_DIV		(0x1 << 3)
 #define MXC_CCM_CSCDR3_QSPI0_X2_DIV		(0x1 << 2)
+#define MXC_CCM_CSCDR3_QSPI0_DIV_OFFSET		(3)
+#define MXC_CCM_CSCDR3_QSPI0_DIV_MASK		(0x1 << 3)
+#define MXC_CCM_CSCDR3_QSPI0_X2_DIV_OFFSET	(2)
+#define MXC_CCM_CSCDR3_QSPI0_X2_DIV_MASK	(0x1 << 2)
 #define MXC_CCM_CSCDR3_QSPI0_X4_DIV_OFFSET	(0)
 #define MXC_CCM_CSCDR3_QSPI0_X4_DIV_MASK	(0x3)
 
diff --git a/arch/arm/mach-mvf/devices-mvf.h b/arch/arm/mach-mvf/devices-mvf.h
index 4e852fef4a4c..d34b72ba89c9 100644
--- a/arch/arm/mach-mvf/devices-mvf.h
+++ b/arch/arm/mach-mvf/devices-mvf.h
@@ -40,6 +40,10 @@ extern const struct imx_spi_imx_data mvf_dspi_data[] __initconst;
 #define mvf_add_dspi(id, pdata)	\
 	mvf_add_spi_mvf(&mvf_dspi_data[id], pdata)
 
+extern const struct imx_spi_imx_data mvf_qspi_data[] __initconst;
+#define mvf_add_qspi(id, pdata)	\
+	mvf_add_spi_mvf(&mvf_qspi_data[id], pdata)
+
 extern const struct imx_imx_i2c_data mvf_i2c_data[] __initconst;
 #define mvf_add_imx_i2c(id, pdata)	\
 	imx_add_imx_i2c(&mvf_i2c_data[id], pdata)
diff --git a/arch/arm/plat-mxc/devices/platform-mvf-spi.c b/arch/arm/plat-mxc/devices/platform-mvf-spi.c
index 030859dcb2a9..a8296742e54c 100644
--- a/arch/arm/plat-mxc/devices/platform-mvf-spi.c
+++ b/arch/arm/plat-mxc/devices/platform-mvf-spi.c
@@ -29,6 +29,13 @@ const struct imx_spi_imx_data mvf_dspi_data[] __initconst = {
 	mvf_dspi_data_entry(2),
 	mvf_dspi_data_entry(3),
 };
+
+const struct imx_spi_imx_data mvf_qspi_data[] __initconst = {
+#define mvf_qspi_data_entry(_id)					\
+	mvf_spi_data_entry(MVF, QUADSPI, "mvf-qspi", _id, SZ_4K)
+	mvf_qspi_data_entry(0),
+	mvf_qspi_data_entry(1),
+};
 #endif /* ifdef CONFIG_SOC_MVF */
 
 struct platform_device *__init mvf_add_spi_mvf(
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mvf.h b/arch/arm/plat-mxc/include/mach/iomux-mvf.h
index ea661abc0126..309a8ca8e621 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mvf.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mvf.h
@@ -310,4 +310,77 @@ typedef enum iomux_config {
 		IOMUX_PAD(0x0054, 0x0054, 0, 0x0000, 0, \
 				MVF600_GPIO_GENERAL_CTRL | PAD_CTL_IBE_ENABLE)
 
+/*QSPI*/
+#define MVF600_PAD79_PTD0_QSPI0_A_SCK                           \
+	IOMUX_PAD(0x013C, 0x013c, 1, 0x0000, 0, \
+			PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_SLOW |	\
+			PAD_CTL_DSE_150ohm | PAD_CTL_PUS_22K_UP | \
+			PAD_CTL_PKE | PAD_CTL_OBE_IBE_ENABLE)
+
+#define MVF600_PAD80_PTD1_QSPI0_A_CS0                           \
+	IOMUX_PAD(0x0140, 0x0140, 1, 0x0000, 0, \
+			PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_SLOW | \
+			PAD_CTL_DSE_150ohm | PAD_CTL_PUS_22K_UP | \
+			PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_OBE_IBE_ENABLE)
+
+#define MVF600_PAD81_PTD2_QSPI0_A_D3                            \
+	IOMUX_PAD(0x0144, 0x0144, 1, 0x0000, 0, \
+			PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_SLOW | \
+			PAD_CTL_DSE_150ohm | PAD_CTL_PUS_22K_UP | \
+			PAD_CTL_OBE_IBE_ENABLE)
+
+#define MVF600_PAD82_PTD3_QSPI0_A_D2                            \
+	IOMUX_PAD(0x0148, 0x0148, 1, 0x0000, 0, \
+			PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_SLOW | \
+			PAD_CTL_DSE_150ohm | PAD_CTL_PUS_22K_UP | \
+			PAD_CTL_OBE_IBE_ENABLE)
+
+#define MVF600_PAD83_PTD4_QSPI0_A_D1                            \
+	IOMUX_PAD(0x014C, 0x014c, 1, 0x0000, 0, \
+			PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_SLOW | \
+			PAD_CTL_DSE_150ohm | PAD_CTL_PUS_22K_UP | \
+			PAD_CTL_OBE_IBE_ENABLE)
+
+#define MVF600_PAD84_PTD5_QSPI0_A_D0                            \
+	IOMUX_PAD(0x0150, 0x0150, 1, 0x0000, 0, \
+			PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_SLOW | \
+			PAD_CTL_DSE_150ohm | PAD_CTL_PUS_22K_UP | \
+			PAD_CTL_PKE | PAD_CTL_OBE_IBE_ENABLE)
+
+#define MVF600_PAD86_PTD7_QSPI0_B_SCK                           \
+	IOMUX_PAD(0x0158, 0x0158, 1, 0x0000, 0, \
+			PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_SLOW | \
+			PAD_CTL_DSE_150ohm | PAD_CTL_PUS_22K_UP | \
+			PAD_CTL_PKE | PAD_CTL_OBE_IBE_ENABLE)
+
+#define MVF600_PAD87_PTD8_QSPI0_B_CS0                           \
+	IOMUX_PAD(0x015C, 0x015c, 1, 0x0000, 0, \
+			PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_SLOW | \
+			PAD_CTL_DSE_150ohm | PAD_CTL_PUS_22K_UP | \
+			PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_OBE_IBE_ENABLE)
+
+#define MVF600_PAD88_PTD9_QSPI0_B_D3                            \
+	IOMUX_PAD(0x0160, 0x0160, 1, 0x0000, 0, \
+			PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_SLOW | \
+			PAD_CTL_DSE_150ohm | PAD_CTL_PUS_22K_UP | \
+			PAD_CTL_OBE_IBE_ENABLE)
+
+#define MVF600_PAD89_PTD10_QSPI0_B_D2                           \
+	IOMUX_PAD(0x0164, 0x0164, 1, 0x0000, 0, \
+			PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_SLOW | \
+			PAD_CTL_DSE_150ohm | PAD_CTL_PUS_22K_UP | \
+			PAD_CTL_OBE_IBE_ENABLE)
+
+#define MVF600_PAD90_PTD11_QSPI0_B_D1                           \
+	IOMUX_PAD(0x0168, 0x0168, 1, 0x0000, 0, \
+			PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_SLOW | \
+			PAD_CTL_DSE_150ohm | PAD_CTL_PUS_22K_UP | \
+			PAD_CTL_OBE_IBE_ENABLE)
+
+#define MVF600_PAD91_PTD12_QSPI0_B_D0                           \
+	IOMUX_PAD(0x016C, 0x016c, 1, 0x0000, 0, \
+			PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_SLOW | \
+			PAD_CTL_DSE_150ohm | PAD_CTL_PUS_22K_UP | \
+			PAD_CTL_PKE | PAD_CTL_OBE_IBE_ENABLE)
+
 #endif
diff --git a/arch/arm/plat-mxc/include/mach/spi-mvf.h b/arch/arm/plat-mxc/include/mach/spi-mvf.h
index 4a05f3b349af..0441a0f6fde5 100644
--- a/arch/arm/plat-mxc/include/mach/spi-mvf.h
+++ b/arch/arm/plat-mxc/include/mach/spi-mvf.h
@@ -97,4 +97,77 @@ struct spi_mvf_master {
 #define SPI_CS_ASSERT		0x02
 #define SPI_CS_DROP		0x04
 
+/* Quad SPI */
+#define INT_DLPFIE		(0x1 << 31)
+#define INT_TBFIE		(0x1 << 27)
+#define INT_TBUIE		(0x1 << 26)
+#define INT_ILLINIE		(0x1 << 23)
+#define INT_RBOIE		(0x1 << 17)
+#define INT_RBDIE               (0x1 << 16)
+#define INT_ABSEIE              (0x1 << 15)
+#define INT_ABOIE               (0x1 << 12)
+#define INT_IUEIE               (0x1 << 11)
+#define INT_IPAEIE              (0x1 << 7)
+#define INT_IPIEIE              (0x1 << 6)
+#define INT_IPGEIE              (0x1 << 4)
+#define INT_TFIE                (0x1 << 0)
+
+#define QUADSPI_MCR             0x00
+#define QUADSPI_IPCR            0x08
+#define QUADSPI_FLSHCR          0x0c
+#define QUADSPI_BUF0CR          0x10
+#define QUADSPI_BUF1CR          0x14
+#define QUADSPI_BUF2CR          0x18
+#define QUADSPI_BUF3CR          0x1c
+#define QUADSPI_BFGENCR         0x20
+#define QUADSPI_SOCCR           0x24
+#define QUADSPI_BUF0IND         0x30
+#define QUADSPI_BUF1IND         0x34
+#define QUADSPI_BUF2IND         0x38
+#define QUADSPI_SFAR            0x100
+#define QUADSPI_SMPR            0x108
+#define QUADSPI_RBSR            0x10c
+#define QUADSPI_RBCT            0x110
+#define QUADSPI_TBSR            0x150
+#define QUADSPI_TBDR            0x154
+#define QUADSPI_SR              0x15c
+#define QUADSPI_FR              0x160
+#define QUADSPI_RSER            0x164
+#define QUADSPI_SPNDST          0x168
+#define QUADSPI_SPTRCLR         0x16c
+#define QUADSPI_SFA1AD          0x180
+#define QUADSPI_SFA2AD          0x184
+#define QUADSPI_SFB1AD          0x188
+#define QUADSPI_SFB2AD          0x18c
+#define QUADSPI_RBDR            0x200
+#define QUADSPI_LUTKEY          0x300
+#define QUADSPI_LCKCR           0x304
+#define QUADSPI_LUT(x)          (0x310 + (x) * 4)
+
+#define OPRND0(x)               (((x) & 0xff) << 0)
+#define PAD0(x)                 (((x) & 0x3) << 8)
+#define INSTR0(x)               (((x) & 0x3f) << 10)
+
+#define OPRND1(x)               (((x) & 0xff) << 16)
+#define PAD1(x)                 (((x) & 0x3) << 24)
+#define INSTR1(x)               (((x) & 0x3f) << 26)
+
+#define SEQU_CMD		0x1
+#define SEQU_ADDR		0x2
+#define SEQU_DUMMY		0x3
+#define SEQU_MODE		0x4
+#define SEQU_MODE2		0x5
+#define SEQU_MODE4		0x6
+#define SEQU_READ		0x7
+#define SEQU_WRITE		0x8
+#define SEQU_JMP_ON_CS		0x9
+#define SEQU_ADDR_DDR		0xa
+#define SEQU_MODE_DDR		0xb
+#define SEQU_MODE2_DDR		0xc
+#define SEQU_MODE4_DDR		0xd
+#define SEQU_READ_DDR		0xe
+#define SEQU_WRITE_DDR		0xf
+#define SEQU_DATA_LEARN		0x10
+#define SEQU_STOP		0x0
+
 #endif /* SPI_MVF_H_ */