arm: tegra: LP1 suspend with 396MHz

If LP1 suspend with original 696MHz, device
may fail to be resumed.

bug 1468844
bug 1392823

Change-Id: I95baa244c1e15ba0ce3b88ef948fc7f27bbd5d98
Signed-off-by: Martin Chi <mchi@nvidia.com>
Reviewed-on: http://git-master/r/374713

5 files changed, 22 insertions, 10 deletions

diff --git a/arch/arm/mach-tegra/clock.h b/arch/arm/mach-tegra/clock.h
index 86ac51e209e3..793eed87c235 100644
--- a/arch/arm/mach-tegra/clock.h
+++ b/arch/arm/mach-tegra/clock.h
@@ -6,7 +6,7 @@
  * Author:
  *	Colin Cross <ccross@google.com>
  *
- * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2010-2014, NVIDIA CORPORATION.  All rights reserved.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -371,7 +371,8 @@ struct tegra_cpufreq_table_data {
 	struct cpufreq_frequency_table *freq_table;
 	int throttle_lowest_index;
 	int throttle_highest_index;
-	int suspend_index;
+	int suspend_index_lp0;
+	int suspend_index_lp1;
 };
 struct tegra_cpufreq_table_data *tegra_cpufreq_table_get(void);
 unsigned long tegra_emc_to_cpu_ratio(unsigned long cpu_rate);
diff --git a/arch/arm/mach-tegra/cpu-tegra.c b/arch/arm/mach-tegra/cpu-tegra.c
index aa0d98a27116..0a3f1bfaf89c 100644
--- a/arch/arm/mach-tegra/cpu-tegra.c
+++ b/arch/arm/mach-tegra/cpu-tegra.c
@@ -7,7 +7,7 @@
  *	Colin Cross <ccross@google.com>
  *	Based on arch/arm/plat-omap/cpu-omap.c, (C) 2005 Nokia Corporation
  *
- * Copyright (C) 2010-2013 NVIDIA CORPORATION. All rights reserved.
+ * Copyright (C) 2010-2014 NVIDIA CORPORATION. All rights reserved.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -42,6 +42,7 @@
 #include "clock.h"
 #include "cpu-tegra.h"
 #include "dvfs.h"
+#include "pm.h"
 
 /* tegra throttling and edp governors require frequencies in the table
    to be in ascending order */
@@ -53,7 +54,8 @@ static unsigned long policy_max_speed[CONFIG_NR_CPUS];
 static unsigned long target_cpu_speed[CONFIG_NR_CPUS];
 static DEFINE_MUTEX(tegra_cpu_lock);
 static bool is_suspended;
-static int suspend_index;
+static int suspend_index_lp0;
+static int suspend_index_lp1;
 static unsigned int volt_capped_speed;
 static struct pm_qos_request cpufreq_max_req;
 static struct pm_qos_request cpufreq_min_req;
@@ -706,10 +708,16 @@ _out:
 	return ret;
 }
 
+extern enum tegra_suspend_mode current_suspend_mode;
 
 static int tegra_pm_notify(struct notifier_block *nb, unsigned long event,
 	void *dummy)
 {
+	int suspend_index;
+
+	suspend_index = (current_suspend_mode == TEGRA_SUSPEND_LP0) ?
+		suspend_index_lp0 : suspend_index_lp1;
+
 	if (event == PM_SUSPEND_PREPARE) {
 		int i;
 
@@ -856,7 +864,8 @@ static int __init tegra_cpufreq_init(void)
 	if (IS_ERR_OR_NULL(table_data))
 		return -EINVAL;
 
-	suspend_index = table_data->suspend_index;
+	suspend_index_lp0 = table_data->suspend_index_lp0;
+	suspend_index_lp1 = table_data->suspend_index_lp1;
 
 	ret = tegra_throttle_init(&tegra_cpu_lock);
 	if (ret)
diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c
index b08b29e9fa25..ede51c0b1e37 100644
--- a/arch/arm/mach-tegra/pm.c
+++ b/arch/arm/mach-tegra/pm.c
@@ -202,7 +202,7 @@ static struct clk *tegra_dfll;
 static struct clk *tegra_pclk;
 static struct clk *tegra_clk_m;
 static const struct tegra_suspend_platform_data *pdata;
-static enum tegra_suspend_mode current_suspend_mode = TEGRA_SUSPEND_NONE;
+enum tegra_suspend_mode current_suspend_mode = TEGRA_SUSPEND_NONE;
 
 #if defined(CONFIG_TEGRA_CLUSTER_CONTROL) && INSTRUMENT_CLUSTER_SWITCH
 enum tegra_cluster_switch_time_id {
diff --git a/arch/arm/mach-tegra/tegra11_clocks.c b/arch/arm/mach-tegra/tegra11_clocks.c
index 27aab964aae2..6b3b82c286d7 100644
--- a/arch/arm/mach-tegra/tegra11_clocks.c
+++ b/arch/arm/mach-tegra/tegra11_clocks.c
@@ -1,7 +1,7 @@
 /*
  * arch/arm/mach-tegra/tegra11_clocks.c
  *
- * Copyright (c) 2011-2013, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2011-2014, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -7581,7 +7581,8 @@ struct tegra_cpufreq_table_data *tegra_cpufreq_table_get(void)
 	cpu_clk_g->min_rate = min(freq_table[i-2].frequency, g_vmin_freq)*1000;
 
 	/* Suspend index at max LP CPU */
-	freq_table_data.suspend_index = i - 1;
+	freq_table_data.suspend_index_lp0 = i - 1;
+	freq_table_data.suspend_index_lp1 = i - 4;
 
 	/* Fill in "hole" (if any) between LP CPU maximum rate and G CPU dvfs
 	   ladder rate at minimum voltage */
diff --git a/arch/arm/mach-tegra/tegra30_clocks.c b/arch/arm/mach-tegra/tegra30_clocks.c
index 5ee4abcf35f1..4815b8c1887a 100644
--- a/arch/arm/mach-tegra/tegra30_clocks.c
+++ b/arch/arm/mach-tegra/tegra30_clocks.c
@@ -1,7 +1,7 @@
 /*
  * arch/arm/mach-tegra/tegra3_clocks.c
  *
- * Copyright (c) 2010-2013 NVIDIA Corporation. All rights reserved.
+ * Copyright (c) 2010-2014 NVIDIA Corporation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -4902,7 +4902,8 @@ static int clip_cpu_rate_limits(
 	}
 	cpu_clk_lp->max_rate = freq_table[idx].frequency * 1000;
 	cpu_clk_g->min_rate = freq_table[idx-1].frequency * 1000;
-	data->suspend_index = idx;
+	data->suspend_index_lp0 = idx;
+	data->suspend_index_lp1 = idx;
 	return 0;
 }