diff options
| author | Gary King <GKing@nvidia.com> | 2010-02-03 14:31:45 -0800 |
|---|---|---|
| committer | Gary King <GKing@nvidia.com> | 2010-02-03 14:31:45 -0800 |
| commit | ec71a089913e01c433e3d4737b92c1f2f3d5a78e (patch) | |
| tree | e161a2e80e76a997bc86314bd83341948202f752 /arch | |
| parent | 1813dcb0ee82867705908bc698072bb49c9abbae (diff) | |
tegra nvos: add outer cache sync to FlushWriteCombineBuffer
dsb() is inadequate to maintain coherence with DMA devices, since it
only guarantees that writes have been flushed from the CPU's store
buffers; store buffers in a non-DMA-coherent outer cache will not
be flushed.
Change-Id: Ia6082beb5d39c8bef7450e674a7077c5159268a3
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-tegra/nvos/nvos.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/nvos/nvos.c b/arch/arm/mach-tegra/nvos/nvos.c index 11e4806f9d7f..14f531f76f13 100644 --- a/arch/arm/mach-tegra/nvos/nvos.c +++ b/arch/arm/mach-tegra/nvos/nvos.c @@ -1122,6 +1122,7 @@ void NvOsInstrCacheInvalidateRange( void NvOsFlushWriteCombineBuffer( void ) { dsb(); + outer_sync(); } NvError NvOsInterruptRegisterInternal( |