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authorPavan Kunapuli <pkunapuli@nvidia.com>2013-07-24 01:12:53 +0530
committerRiham Haidar <rhaidar@nvidia.com>2013-09-16 12:28:30 -0700
commit1b10b307c339d6ca811fee3ec7460577df64ef7a (patch)
treecb099370e90f6b233ed11353e857cc1dc49a913a /arch
parent7101e9fd4e105ac2e26f0652466d19d67e3cd897 (diff)
mmc: tegra: 1.39V Tuning during device enumeration
Tuning at 1.39V to find a valid tap value that works at all core voltages. Boosting emc clock to 900MHz before setting 1.39V and releasing the frequency after 1.39V setting is removed. Bug 1331018 Reviewed-on: http://git-master/r/252471 (cherry picked from commit 25efc183d9f57431c379fecce0e2cc541b0fbc93) Change-Id: Icbf009a90ba9d0bd88a5991aab2fad8f1783b823 Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com> Signed-off-by: Naveen Kumar Arepalli <naveenk@nvidia.com> Change-Id: I512a29e94cb935c12a8e705da1d4478c640c9529 Reviewed-on: http://git-master/r/274994 GVS: Gerrit_Virtual_Submit Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-tegra/tegra11_clocks.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/tegra11_clocks.c b/arch/arm/mach-tegra/tegra11_clocks.c
index 1e147c3e6665..f8e76d585846 100644
--- a/arch/arm/mach-tegra/tegra11_clocks.c
+++ b/arch/arm/mach-tegra/tegra11_clocks.c
@@ -6781,6 +6781,7 @@ struct clk tegra_list_clks[] = {
SHARED_CLK("2d.emc", "tegra_gr2d", "emc", &tegra_clk_emc, NULL, 0, 0),
SHARED_CLK("msenc.emc", "tegra_msenc", "emc", &tegra_clk_emc, NULL, 0, SHARED_BW),
SHARED_CLK("tsec.emc", "tegra_tsec", "emc", &tegra_clk_emc, NULL, 0, 0),
+ SHARED_CLK("sdmmc1.emc", "sdhci-tegra.0", "emc", &tegra_clk_emc, NULL, 0, 0),
SHARED_CLK("sdmmc4.emc", "sdhci-tegra.3", "emc", &tegra_clk_emc, NULL, 0, 0),
SHARED_CLK("camera.emc", "vi", "emc", &tegra_clk_emc, NULL, 0, SHARED_BW),
SHARED_CLK("iso.emc", "iso", "emc", &tegra_clk_emc, NULL, 0, SHARED_BW),