ARM: tegra: TrustedLogic drop 32055tegra-12r9-android-3.2

The WARs checked into 12r7: disable LP0/LP1 and slave LP2, and force
maxcpus to 1 aren't needed when used with the newer tf_include.h from
this TL drop.

bug 868906
bug 870224
bug 877339

Change-Id: Ic3002b1d5fa09e8171c0d43bf6978ae96e51daf8
Reviewed-on: http://git-master/r/53324
Reviewed-by: Rahul Prabhakar <rahulp@nvidia.com>
Tested-by: Rahul Prabhakar <rahulp@nvidia.com>
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Reviewed-by: Jonathan White <jwhite@nvidia.com>

5 files changed, 25 insertions, 13 deletions

diff --git a/arch/arm/mach-tegra/cortex-a9.S b/arch/arm/mach-tegra/cortex-a9.S
index 96f915725eb1..da571910ca06 100644
--- a/arch/arm/mach-tegra/cortex-a9.S
+++ b/arch/arm/mach-tegra/cortex-a9.S
@@ -465,6 +465,12 @@ ENTRY(__cortex_a9_restore)
 
 	mcr	p15, 2, r0, c0, c0, 0	@ csselr
 	mcr	p15, 0, r1, c1, c0, 0	@ sctlr
+#ifndef CONFIG_TRUSTED_FOUNDATIONS
+	/*
+	 * Restoring ACTRL / PCTLR needs to be done by secure code
+	 * as not all bits of ACTRL are writable (and none of PCTLR)
+	 * by non-secure code.
+	 */
 	tst	r2, #(0x1 << 6)
 	orrne	r2, r2, #(1 << 0)	@ sync FW bit with SMP state
 	mcr	p15, 0, r2, c1, c0, 1	@ actlr
@@ -475,8 +481,6 @@ ENTRY(__cortex_a9_restore)
 	orreq	r3, r3, #(3<<8)		@ set MAXCLKLATENCY to 3 on G
 	orrne	r3, r3, #(2<<8)		@ set MAXCLKLATENCY to 2 on LP
 #endif
-#ifndef CONFIG_TRUSTED_FOUNDATIONS
-	//TL : moved to secure
 	mcr	p15, 0, r3, c15, c0, 0	@ pctlr
 #endif
 
diff --git a/arch/arm/mach-tegra/cpuidle-t3.c b/arch/arm/mach-tegra/cpuidle-t3.c
index ebc009e43354..386adf26b398 100644
--- a/arch/arm/mach-tegra/cpuidle-t3.c
+++ b/arch/arm/mach-tegra/cpuidle-t3.c
@@ -116,13 +116,6 @@ bool tegra_lp2_is_allowed(struct cpuidle_device *dev,
 	if (!tegra_all_cpus_booted)
 		return false;
 
-#ifdef CONFIG_TRUSTED_FOUNDATIONS
-	/* For now, we don't understand this behavior...
-	 * Without this check tt will generate the MC_DECERR msg!
-	 */
-	if (num_online_cpus() > 1)
-		return false;
-#endif
 	/* On A01, lp2 on slave cpu's cause cpu hang randomly.
 	 * Refer to Bug 804085.
 	 */
@@ -391,19 +384,22 @@ static int tegra_lp2_debug_show(struct seq_file *s, void *data)
 			(idle_stats.lp2_count ?: 1));
 
 	seq_printf(s, "\n");
-	seq_printf(s, "lp2 ready time:                 %8llu %8llu %8llu %8llu %8llu ms\n",
+	seq_printf(s, "lp2 ready time:%16s %8llu %8llu %8llu %8llu %8llu ms\n",
+		"",
 		div64_u64(idle_stats.cpu_wants_lp2_time[0], 1000),
 		div64_u64(idle_stats.cpu_wants_lp2_time[1], 1000),
 		div64_u64(idle_stats.cpu_wants_lp2_time[2], 1000),
 		div64_u64(idle_stats.cpu_wants_lp2_time[3], 1000),
 		div64_u64(idle_stats.cpu_wants_lp2_time[4], 1000));
-	seq_printf(s, "lp2 time:                       %8llu %8llu %8llu %8llu %8llu ms\n",
+	seq_printf(s, "lp2 time:%22s %8llu %8llu %8llu %8llu %8llu ms\n",
+		"",
 		div64_u64(idle_stats.in_lp2_time[0], 1000),
 		div64_u64(idle_stats.in_lp2_time[1], 1000),
 		div64_u64(idle_stats.in_lp2_time[2], 1000),
 		div64_u64(idle_stats.in_lp2_time[3], 1000),
 		div64_u64(idle_stats.in_lp2_time[4], 1000));
-	seq_printf(s, "lp2 %:                          %7d%% %7d%% %7d%% %7d%% %7d%%\n",
+	seq_printf(s, "lp2 %%:%26s %7d%% %7d%% %7d%% %7d%% %7d%%\n",
+		"",
 		(int)(idle_stats.cpu_wants_lp2_time[0] ?
 			div64_u64(idle_stats.in_lp2_time[0] * 100,
 			idle_stats.cpu_wants_lp2_time[0]) : 0),
diff --git a/arch/arm/mach-tegra/headsmp-t3.S b/arch/arm/mach-tegra/headsmp-t3.S
index b4e70c29e2f4..7eb5c42765fd 100644
--- a/arch/arm/mach-tegra/headsmp-t3.S
+++ b/arch/arm/mach-tegra/headsmp-t3.S
@@ -151,6 +151,11 @@ ENTRY(tegra_lp2_startup)
 	str	r1, [r0]
 	dsb
 
+#ifdef CONFIG_TRUSTED_FOUNDATIONS
+	/* wake up */
+	smc	0
+#endif
+
 	adr	r4, __tegra_lp2_data
 	ldmia	r4, {r5, r7, r12}
 	mov	r1, r12			@ ctx_restore = __cortex_a9_restore
diff --git a/arch/arm/mach-tegra/tegra2_save.S b/arch/arm/mach-tegra/tegra2_save.S
index 3c0de77d21ec..cb76786ee1f3 100644
--- a/arch/arm/mach-tegra/tegra2_save.S
+++ b/arch/arm/mach-tegra/tegra2_save.S
@@ -183,13 +183,17 @@ __tegra_lp1_reset:
 	/* the CPU and system bus are running at 32KHz and executing from
 	 * IRAM when this code is executed; immediately switch to CLKM and
 	 * enable PLLP. */
+
 	mov32	r0, TEGRA_CLK_RESET_BASE
+#ifndef CONFIG_TRUSTED_FOUNDATIONS
+	/* secure code handles 32KHz to CLKM/OSC clock switch */
 	mov	r1, #(1<<28)
 	str	r1, [r0, #CLK_RESET_SCLK_BURST]
 	str	r1, [r0, #CLK_RESET_CCLK_BURST]
 	mov	r1, #0
 	str	r1, [r0, #CLK_RESET_SCLK_DIVIDER]
 	str	r1, [r0, #CLK_RESET_CCLK_DIVIDER]
+#endif
 
 	ldr	r1, [r0, #CLK_RESET_PLLM_BASE]
 	tst	r1, #(1<<30)
diff --git a/arch/arm/mach-tegra/tegra3_save.S b/arch/arm/mach-tegra/tegra3_save.S
index a5e5aabcc8a0..ed214412d6ec 100644
--- a/arch/arm/mach-tegra/tegra3_save.S
+++ b/arch/arm/mach-tegra/tegra3_save.S
@@ -252,14 +252,17 @@ ENTRY(__tegra_lp1_reset)
 	/* the CPU and system bus are running at 32KHz and executing from
 	 * IRAM when this code is executed; immediately switch to CLKM and
 	 * enable PLLP, PLLM, PLLC, PLLA and PLLX. */
-	mov32	r0, TEGRA_CLK_RESET_BASE
 
+	mov32	r0, TEGRA_CLK_RESET_BASE
+#ifndef CONFIG_TRUSTED_FOUNDATIONS
+	/* secure code handles 32KHz to CLKM/OSC clock switch */
 	mov	r1, #(1<<28)
 	str	r1, [r0, #CLK_RESET_SCLK_BURST]
 	str	r1, [r0, #CLK_RESET_CCLK_BURST]
 	mov	r1, #0
 	str	r1, [r0, #CLK_RESET_SCLK_DIVIDER]
 	str	r1, [r0, #CLK_RESET_CCLK_DIVIDER]
+#endif
 
 	/* enable PLLM via PMC */
 	mov32	r2, TEGRA_PMC_BASE