diff options
| author | Gary King <gking@nvidia.com> | 2010-05-16 18:22:24 -0700 |
|---|---|---|
| committer | Gary King <gking@nvidia.com> | 2010-05-16 20:11:12 -0700 |
| commit | 56f969abc37376f950fc743dab47239c9b773507 (patch) | |
| tree | 687983cc2de102211fc196c643c31eefc634203d /arch | |
| parent | 7b415930da2505d4d2c0b76329215298ff3e6189 (diff) | |
[mtd] add NAND device MTD block driver for Tegra SoCs
Change-Id: Id38598e0a63b3f723cc07933c54bf5a99781ad0a
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-tegra/Makefile | 4 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/include/ap20/arnandflash.h | 4245 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/include/mach/nand.h | 31 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/include/nvddk_nand.h | 599 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/nvddk/Makefile | 6 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/nvddk/nvddk_nand.c | 4948 |
6 files changed, 9832 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index 45ca6396652d..bc437214a4ec 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -31,4 +31,6 @@ obj-$(CONFIG_TEGRA_NVRM) += nvodm/ obj-$(CONFIG_TEGRA_NVRM) += odm_kit/ obj-$(CONFIG_TEGRA_NVRM) += nvreftrack/ obj-$(CONFIG_TEGRA_NVRM) += nvrm_user.o -obj-$(CONFIG_TEGRA_NVRM) += clock_nvrm.o
\ No newline at end of file +obj-$(CONFIG_TEGRA_NVRM) += clock_nvrm.o + +obj-y += nvddk/ diff --git a/arch/arm/mach-tegra/include/ap20/arnandflash.h b/arch/arm/mach-tegra/include/ap20/arnandflash.h new file mode 100644 index 000000000000..73075f5f8760 --- /dev/null +++ b/arch/arm/mach-tegra/include/ap20/arnandflash.h @@ -0,0 +1,4245 @@ +/* + * Copyright (c) 2009 NVIDIA Corporation. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of the NVIDIA Corporation nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + */ +// +// DO NOT EDIT - generated by simspec! +// + +#ifndef ___ARNANDFLASH_H_INC_ +#define ___ARNANDFLASH_H_INC_ +#define NDFLASH_CMDQ_FIFO_WIDTH 32 +#define NDFLASH_CMDQ_FIFO_DEPTH 8 +#define NDFLASH_ECC_FIFO_WIDTH 32 +#define NDFLASH_ECC_FIFO_DEPTH 128 +#define NDFLASH_AFIFO_WIDTH 32 +#define NDFLASH_AFIFO_DEPTH 1024 +#define NDFLASH_BFIFO_WIDTH 32 +#define NDFLASH_BFIFO_DEPTH 128 +#define NDFLASH_CS_MAX 8 +#define NDFLASH_DMA_MAX_BYTES 65536 +#define NDFLASH_DMA_PTR_ALIGN 4 +#define NDFLASH_CMDQ_MAX_PKT_LENGTH 15 +#define NDFLASH_PARITY_SZ_RS_T1_256 4 +#define NDFLASH_PARITY_SZ_RS_T4_512 12 +#define NDFLASH_PARITY_SZ_RS_T4_1024 20 +#define NDFLASH_PARITY_SZ_RS_T4_2048 36 +#define NDFLASH_PARITY_SZ_RS_T4_4096 72 +#define NDFLASH_PARITY_SZ_RS_T6_512 16 +#define NDFLASH_PARITY_SZ_RS_T6_1024 28 +#define NDFLASH_PARITY_SZ_RS_T6_2048 56 +#define NDFLASH_PARITY_SZ_RS_T6_4096 108 +#define NDFLASH_PARITY_SZ_RS_T8_512 20 +#define NDFLASH_PARITY_SZ_RS_T8_1024 36 +#define NDFLASH_PARITY_SZ_RS_T8_2048 72 +#define NDFLASH_PARITY_SZ_RS_T8_4096 144 +#define NDFLASH_PARITY_SZ_HAMMING_256 4 +#define NDFLASH_PARITY_SZ_HAMMING_512 4 +#define NDFLASH_PARITY_SZ_HAMMING_1024 8 +#define NDFLASH_PARITY_SZ_HAMMING_2048 16 +#define NDFLASH_PARITY_SZ_HAMMING_4096 32 +#define NDFLASH_PARITY_SZ_HAMMING_SPARE 4 +#define NDFLASH_PARITY_SZ_BCH_T4_512 7 +#define NDFLASH_PARITY_SZ_BCH_T8_512 13 +#define NDFLASH_PARITY_SZ_BCH_T14_512 23 +#define NDFLASH_PARITY_SZ_BCH_T16_512 26 + +// Register NAND_COMMAND_0 +#define NAND_COMMAND_0 _MK_ADDR_CONST(0x0) +#define NAND_COMMAND_0_SECURE 0x0 +#define NAND_COMMAND_0_WORD_COUNT 0x1 +#define NAND_COMMAND_0_RESET_VAL _MK_MASK_CONST(0x800004) +#define NAND_COMMAND_0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define NAND_COMMAND_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define NAND_COMMAND_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_COMMAND_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define NAND_COMMAND_0_WRITE_MASK _MK_MASK_CONST(0x7fffffff) +// 0 = HW clears when programmed nand IO +// operation is completed. +#define NAND_COMMAND_0_GO_SHIFT _MK_SHIFT_CONST(31) +#define NAND_COMMAND_0_GO_FIELD (_MK_MASK_CONST(0x1) << NAND_COMMAND_0_GO_SHIFT) +#define NAND_COMMAND_0_GO_RANGE 31:31 +#define NAND_COMMAND_0_GO_WOFFSET 0x0 +#define NAND_COMMAND_0_GO_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_COMMAND_0_GO_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_COMMAND_0_GO_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_COMMAND_0_GO_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_COMMAND_0_GO_DISABLE _MK_ENUM_CONST(0) +#define NAND_COMMAND_0_GO_ENABLE _MK_ENUM_CONST(1) + +// CLE enable +// 1 = Flash sequence has Command Cycle(CLE) enabled +// 0 = Flash sequence has Command Cycle(CLE) disabled +#define NAND_COMMAND_0_CLE_SHIFT _MK_SHIFT_CONST(30) +#define NAND_COMMAND_0_CLE_FIELD (_MK_MASK_CONST(0x1) << NAND_COMMAND_0_CLE_SHIFT) +#define NAND_COMMAND_0_CLE_RANGE 30:30 +#define NAND_COMMAND_0_CLE_WOFFSET 0x0 +#define NAND_COMMAND_0_CLE_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_COMMAND_0_CLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_COMMAND_0_CLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_COMMAND_0_CLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_COMMAND_0_CLE_DISABLE _MK_ENUM_CONST(0) +#define NAND_COMMAND_0_CLE_ENABLE _MK_ENUM_CONST(1) + +// ALE enable +// 1 = Flash sequence has Address Cycle(CLE) enabled +// 0 = Flash sequence has Address Cycle(CLE) disabled +#define NAND_COMMAND_0_ALE_SHIFT _MK_SHIFT_CONST(29) +#define NAND_COMMAND_0_ALE_FIELD (_MK_MASK_CONST(0x1) << NAND_COMMAND_0_ALE_SHIFT) +#define NAND_COMMAND_0_ALE_RANGE 29:29 +#define NAND_COMMAND_0_ALE_WOFFSET 0x0 +#define NAND_COMMAND_0_ALE_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_COMMAND_0_ALE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_COMMAND_0_ALE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_COMMAND_0_ALE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_COMMAND_0_ALE_DISABLE _MK_ENUM_CONST(0) +#define NAND_COMMAND_0_ALE_ENABLE _MK_ENUM_CONST(1) + +// PIO mode of operation enable +// 1 = Dataout is from NAND_RESP register +// and Datain is to NAND_RESP register +// 0 = Dataout is from FIFO buffer +// and Datain to FIFO buffer +#define NAND_COMMAND_0_PIO_SHIFT _MK_SHIFT_CONST(28) +#define NAND_COMMAND_0_PIO_FIELD (_MK_MASK_CONST(0x1) << NAND_COMMAND_0_PIO_SHIFT) +#define NAND_COMMAND_0_PIO_RANGE 28:28 +#define NAND_COMMAND_0_PIO_WOFFSET 0x0 +#define NAND_COMMAND_0_PIO_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_COMMAND_0_PIO_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_COMMAND_0_PIO_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_COMMAND_0_PIO_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_COMMAND_0_PIO_DISABLE _MK_ENUM_CONST(0) +#define NAND_COMMAND_0_PIO_ENABLE _MK_ENUM_CONST(1) + +// write data transfer enable - required for FLASH program +// 1 = Write data transfers to flash is enabled +// 0 = Write data transfers to flash is disabled +#define NAND_COMMAND_0_TX_SHIFT _MK_SHIFT_CONST(27) +#define NAND_COMMAND_0_TX_FIELD (_MK_MASK_CONST(0x1) << NAND_COMMAND_0_TX_SHIFT) +#define NAND_COMMAND_0_TX_RANGE 27:27 +#define NAND_COMMAND_0_TX_WOFFSET 0x0 +#define NAND_COMMAND_0_TX_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_COMMAND_0_TX_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_COMMAND_0_TX_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_COMMAND_0_TX_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_COMMAND_0_TX_DISABLE _MK_ENUM_CONST(0) +#define NAND_COMMAND_0_TX_ENABLE _MK_ENUM_CONST(1) + +// read data transfer enabled - required for FLASH read +// 1 = Read data transfers from flash is enabled +// 0 = Read data transfers from flash is disabled +#define NAND_COMMAND_0_RX_SHIFT _MK_SHIFT_CONST(26) +#define NAND_COMMAND_0_RX_FIELD (_MK_MASK_CONST(0x1) << NAND_COMMAND_0_RX_SHIFT) +#define NAND_COMMAND_0_RX_RANGE 26:26 +#define NAND_COMMAND_0_RX_WOFFSET 0x0 +#define NAND_COMMAND_0_RX_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_COMMAND_0_RX_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_COMMAND_0_RX_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_COMMAND_0_RX_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_COMMAND_0_RX_DISABLE _MK_ENUM_CONST(0) +#define NAND_COMMAND_0_RX_ENABLE _MK_ENUM_CONST(1) + +// CMD2 sequence to flash enable +// 1 = NAND command sequence have a second command(CLE) +// cycle +// 0 = NAND command sequence doesnt have second CLE cycle +#define NAND_COMMAND_0_SEC_CMD_SHIFT _MK_SHIFT_CONST(25) +#define NAND_COMMAND_0_SEC_CMD_FIELD (_MK_MASK_CONST(0x1) << NAND_COMMAND_0_SEC_CMD_SHIFT) +#define NAND_COMMAND_0_SEC_CMD_RANGE 25:25 +#define NAND_COMMAND_0_SEC_CMD_WOFFSET 0x0 +#define NAND_COMMAND_0_SEC_CMD_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_COMMAND_0_SEC_CMD_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_COMMAND_0_SEC_CMD_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_COMMAND_0_SEC_CMD_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_COMMAND_0_SEC_CMD_DISABLE _MK_ENUM_CONST(0) +#define NAND_COMMAND_0_SEC_CMD_ENABLE _MK_ENUM_CONST(1) + +// CMD2 placement control +// 1 - CMD2 CLE cycle is issued after data transfer cycles. +// this is the typical usage during FLASH program +// 0 - CMD2 CLE cycle is issued right after Address transfer +// cycles, typical usage during FLASH read +#define NAND_COMMAND_0_AFT_DAT_SHIFT _MK_SHIFT_CONST(24) +#define NAND_COMMAND_0_AFT_DAT_FIELD (_MK_MASK_CONST(0x1) << NAND_COMMAND_0_AFT_DAT_SHIFT) +#define NAND_COMMAND_0_AFT_DAT_RANGE 24:24 +#define NAND_COMMAND_0_AFT_DAT_WOFFSET 0x0 +#define NAND_COMMAND_0_AFT_DAT_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_COMMAND_0_AFT_DAT_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_COMMAND_0_AFT_DAT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_COMMAND_0_AFT_DAT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_COMMAND_0_AFT_DAT_DISABLE _MK_ENUM_CONST(0) +#define NAND_COMMAND_0_AFT_DAT_ENABLE _MK_ENUM_CONST(1) + +// Transfer size of bytes Depends on PAGE_SIZE_SEL field of CONFIG register +#define NAND_COMMAND_0_TRANS_SIZE_SHIFT _MK_SHIFT_CONST(20) +#define NAND_COMMAND_0_TRANS_SIZE_FIELD (_MK_MASK_CONST(0xf) << NAND_COMMAND_0_TRANS_SIZE_SHIFT) +#define NAND_COMMAND_0_TRANS_SIZE_RANGE 23:20 +#define NAND_COMMAND_0_TRANS_SIZE_WOFFSET 0x0 +#define NAND_COMMAND_0_TRANS_SIZE_DEFAULT _MK_MASK_CONST(0x8) +#define NAND_COMMAND_0_TRANS_SIZE_DEFAULT_MASK _MK_MASK_CONST(0xf) +#define NAND_COMMAND_0_TRANS_SIZE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_COMMAND_0_TRANS_SIZE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_COMMAND_0_TRANS_SIZE_BYTES1 _MK_ENUM_CONST(0) +#define NAND_COMMAND_0_TRANS_SIZE_BYTES2 _MK_ENUM_CONST(1) +#define NAND_COMMAND_0_TRANS_SIZE_BYTES3 _MK_ENUM_CONST(2) +#define NAND_COMMAND_0_TRANS_SIZE_BYTES4 _MK_ENUM_CONST(3) +#define NAND_COMMAND_0_TRANS_SIZE_BYTES5 _MK_ENUM_CONST(4) +#define NAND_COMMAND_0_TRANS_SIZE_BYTES6 _MK_ENUM_CONST(5) +#define NAND_COMMAND_0_TRANS_SIZE_BYTES7 _MK_ENUM_CONST(6) +#define NAND_COMMAND_0_TRANS_SIZE_BYTES8 _MK_ENUM_CONST(7) +#define NAND_COMMAND_0_TRANS_SIZE_BYTES_PAGE_SIZE_SEL _MK_ENUM_CONST(8) + +// Main data region transer enable +// 1 = Involves Main area data transfer in flash sequence +// 0 = Doesnt involve Main area data transfer +#define NAND_COMMAND_0_A_VALID_SHIFT _MK_SHIFT_CONST(19) +#define NAND_COMMAND_0_A_VALID_FIELD (_MK_MASK_CONST(0x1) << NAND_COMMAND_0_A_VALID_SHIFT) +#define NAND_COMMAND_0_A_VALID_RANGE 19:19 +#define NAND_COMMAND_0_A_VALID_WOFFSET 0x0 +#define NAND_COMMAND_0_A_VALID_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_COMMAND_0_A_VALID_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_COMMAND_0_A_VALID_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_COMMAND_0_A_VALID_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_COMMAND_0_A_VALID_DISABLE _MK_ENUM_CONST(0) +#define NAND_COMMAND_0_A_VALID_ENABLE _MK_ENUM_CONST(1) + +// Spare region (aka TAG) transfer enable +// 1 = Involves spare area data transfer in flash sequence +// 0 = Doesnt involve spare area data transfer +#define NAND_COMMAND_0_B_VALID_SHIFT _MK_SHIFT_CONST(18) +#define NAND_COMMAND_0_B_VALID_FIELD (_MK_MASK_CONST(0x1) << NAND_COMMAND_0_B_VALID_SHIFT) +#define NAND_COMMAND_0_B_VALID_RANGE 18:18 +#define NAND_COMMAND_0_B_VALID_WOFFSET 0x0 +#define NAND_COMMAND_0_B_VALID_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_COMMAND_0_B_VALID_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_COMMAND_0_B_VALID_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_COMMAND_0_B_VALID_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_COMMAND_0_B_VALID_DISABLE _MK_ENUM_CONST(0) +#define NAND_COMMAND_0_B_VALID_ENABLE _MK_ENUM_CONST(1) + +// H/W assisted read status check enable +// 1 = Indicates to controller that current IO sequence +// need RD STATUS check condition to be qualified. +// 0 = auto read status check is disabled +// notes: please refer to NAND_HWSTATUS_CMD register for +// qualifier conditon +#define NAND_COMMAND_0_RD_STATUS_CHK_SHIFT _MK_SHIFT_CONST(17) +#define NAND_COMMAND_0_RD_STATUS_CHK_FIELD (_MK_MASK_CONST(0x1) << NAND_COMMAND_0_RD_STATUS_CHK_SHIFT) +#define NAND_COMMAND_0_RD_STATUS_CHK_RANGE 17:17 +#define NAND_COMMAND_0_RD_STATUS_CHK_WOFFSET 0x0 +#define NAND_COMMAND_0_RD_STATUS_CHK_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_COMMAND_0_RD_STATUS_CHK_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_COMMAND_0_RD_STATUS_CHK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_COMMAND_0_RD_STATUS_CHK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_COMMAND_0_RD_STATUS_CHK_DISABLE _MK_ENUM_CONST(0) +#define NAND_COMMAND_0_RD_STATUS_CHK_ENABLE _MK_ENUM_CONST(1) + +// H/W assited rbsy check enable +// 1 = Indicates to controller that current IO sequence +// need RBSY check condition to be qualified. +// 0 = auto RBSY check is disabled +// notes: please refer to NAND_HWSTATUS_CMD register for +// qualifier conditon +#define NAND_COMMAND_0_RBSY_CHK_SHIFT _MK_SHIFT_CONST(16) +#define NAND_COMMAND_0_RBSY_CHK_FIELD (_MK_MASK_CONST(0x1) << NAND_COMMAND_0_RBSY_CHK_SHIFT) +#define NAND_COMMAND_0_RBSY_CHK_RANGE 16:16 +#define NAND_COMMAND_0_RBSY_CHK_WOFFSET 0x0 +#define NAND_COMMAND_0_RBSY_CHK_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_COMMAND_0_RBSY_CHK_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_COMMAND_0_RBSY_CHK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_COMMAND_0_RBSY_CHK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_COMMAND_0_RBSY_CHK_DISABLE _MK_ENUM_CONST(0) +#define NAND_COMMAND_0_RBSY_CHK_ENABLE _MK_ENUM_CONST(1) + +// Chip select enable for Flash Card 7 +// 0 = Disable 1 = Enable +#define NAND_COMMAND_0_CE7_SHIFT _MK_SHIFT_CONST(15) +#define NAND_COMMAND_0_CE7_FIELD (_MK_MASK_CONST(0x1) << NAND_COMMAND_0_CE7_SHIFT) +#define NAND_COMMAND_0_CE7_RANGE 15:15 +#define NAND_COMMAND_0_CE7_WOFFSET 0x0 +#define NAND_COMMAND_0_CE7_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_COMMAND_0_CE7_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_COMMAND_0_CE7_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_COMMAND_0_CE7_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_COMMAND_0_CE7_DISABLE _MK_ENUM_CONST(0) +#define NAND_COMMAND_0_CE7_ENABLE _MK_ENUM_CONST(1) + +// Chip select enable for Flash Card 6 +// 0 = Disable 1 = Enable +#define NAND_COMMAND_0_CE6_SHIFT _MK_SHIFT_CONST(14) +#define NAND_COMMAND_0_CE6_FIELD (_MK_MASK_CONST(0x1) << NAND_COMMAND_0_CE6_SHIFT) +#define NAND_COMMAND_0_CE6_RANGE 14:14 +#define NAND_COMMAND_0_CE6_WOFFSET 0x0 +#define NAND_COMMAND_0_CE6_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_COMMAND_0_CE6_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_COMMAND_0_CE6_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_COMMAND_0_CE6_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_COMMAND_0_CE6_DISABLE _MK_ENUM_CONST(0) +#define NAND_COMMAND_0_CE6_ENABLE _MK_ENUM_CONST(1) + +// Chip select enable for Flash Card 5 +// 0 = Disable 1 = Enable +#define NAND_COMMAND_0_CE5_SHIFT _MK_SHIFT_CONST(13) +#define NAND_COMMAND_0_CE5_FIELD (_MK_MASK_CONST(0x1) << NAND_COMMAND_0_CE5_SHIFT) +#define NAND_COMMAND_0_CE5_RANGE 13:13 +#define NAND_COMMAND_0_CE5_WOFFSET 0x0 +#define NAND_COMMAND_0_CE5_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_COMMAND_0_CE5_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_COMMAND_0_CE5_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_COMMAND_0_CE5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_COMMAND_0_CE5_DISABLE _MK_ENUM_CONST(0) +#define NAND_COMMAND_0_CE5_ENABLE _MK_ENUM_CONST(1) + +// Chip select enable for Flash Card 4 +// 0 = Disable 1 = Enable +#define NAND_COMMAND_0_CE4_SHIFT _MK_SHIFT_CONST(12) +#define NAND_COMMAND_0_CE4_FIELD (_MK_MASK_CONST(0x1) << NAND_COMMAND_0_CE4_SHIFT) +#define NAND_COMMAND_0_CE4_RANGE 12:12 +#define NAND_COMMAND_0_CE4_WOFFSET 0x0 +#define NAND_COMMAND_0_CE4_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_COMMAND_0_CE4_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_COMMAND_0_CE4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_COMMAND_0_CE4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_COMMAND_0_CE4_DISABLE _MK_ENUM_CONST(0) +#define NAND_COMMAND_0_CE4_ENABLE _MK_ENUM_CONST(1) + +// Chip select enable for Flash Card 3 +// 0 = Disable 1 = Enable +#define NAND_COMMAND_0_CE3_SHIFT _MK_SHIFT_CONST(11) +#define NAND_COMMAND_0_CE3_FIELD (_MK_MASK_CONST(0x1) << NAND_COMMAND_0_CE3_SHIFT) +#define NAND_COMMAND_0_CE3_RANGE 11:11 +#define NAND_COMMAND_0_CE3_WOFFSET 0x0 +#define NAND_COMMAND_0_CE3_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_COMMAND_0_CE3_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_COMMAND_0_CE3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_COMMAND_0_CE3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_COMMAND_0_CE3_DISABLE _MK_ENUM_CONST(0) +#define NAND_COMMAND_0_CE3_ENABLE _MK_ENUM_CONST(1) + +// Chip select enable for Flash Card 2 +// 0 = Disable 1 = Enable +#define NAND_COMMAND_0_CE2_SHIFT _MK_SHIFT_CONST(10) +#define NAND_COMMAND_0_CE2_FIELD (_MK_MASK_CONST(0x1) << NAND_COMMAND_0_CE2_SHIFT) +#define NAND_COMMAND_0_CE2_RANGE 10:10 +#define NAND_COMMAND_0_CE2_WOFFSET 0x0 +#define NAND_COMMAND_0_CE2_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_COMMAND_0_CE2_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_COMMAND_0_CE2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_COMMAND_0_CE2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_COMMAND_0_CE2_DISABLE _MK_ENUM_CONST(0) +#define NAND_COMMAND_0_CE2_ENABLE _MK_ENUM_CONST(1) + +// Chip select enable for Flash Card 1 +// 0 = Disable 1 = Enable +#define NAND_COMMAND_0_CE1_SHIFT _MK_SHIFT_CONST(9) +#define NAND_COMMAND_0_CE1_FIELD (_MK_MASK_CONST(0x1) << NAND_COMMAND_0_CE1_SHIFT) +#define NAND_COMMAND_0_CE1_RANGE 9:9 +#define NAND_COMMAND_0_CE1_WOFFSET 0x0 +#define NAND_COMMAND_0_CE1_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_COMMAND_0_CE1_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_COMMAND_0_CE1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_COMMAND_0_CE1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_COMMAND_0_CE1_DISABLE _MK_ENUM_CONST(0) +#define NAND_COMMAND_0_CE1_ENABLE _MK_ENUM_CONST(1) + +// Chip select enable for Flash Card 0 +// 0 = Disable 1 = Enable +#define NAND_COMMAND_0_CE0_SHIFT _MK_SHIFT_CONST(8) +#define NAND_COMMAND_0_CE0_FIELD (_MK_MASK_CONST(0x1) << NAND_COMMAND_0_CE0_SHIFT) +#define NAND_COMMAND_0_CE0_RANGE 8:8 +#define NAND_COMMAND_0_CE0_WOFFSET 0x0 +#define NAND_COMMAND_0_CE0_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_COMMAND_0_CE0_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_COMMAND_0_CE0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_COMMAND_0_CE0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_COMMAND_0_CE0_DISABLE _MK_ENUM_CONST(0) +#define NAND_COMMAND_0_CE0_ENABLE _MK_ENUM_CONST(1) + +#define NAND_COMMAND_0_RSVD_SHIFT _MK_SHIFT_CONST(6) +#define NAND_COMMAND_0_RSVD_FIELD (_MK_MASK_CONST(0x3) << NAND_COMMAND_0_RSVD_SHIFT) +#define NAND_COMMAND_0_RSVD_RANGE 7:6 +#define NAND_COMMAND_0_RSVD_WOFFSET 0x0 +#define NAND_COMMAND_0_RSVD_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_COMMAND_0_RSVD_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define NAND_COMMAND_0_RSVD_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_COMMAND_0_RSVD_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// Command cycle byte count +#define NAND_COMMAND_0_CLE_BYTE_SIZE_SHIFT _MK_SHIFT_CONST(4) +#define NAND_COMMAND_0_CLE_BYTE_SIZE_FIELD (_MK_MASK_CONST(0x3) << NAND_COMMAND_0_CLE_BYTE_SIZE_SHIFT) +#define NAND_COMMAND_0_CLE_BYTE_SIZE_RANGE 5:4 +#define NAND_COMMAND_0_CLE_BYTE_SIZE_WOFFSET 0x0 +#define NAND_COMMAND_0_CLE_BYTE_SIZE_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_COMMAND_0_CLE_BYTE_SIZE_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define NAND_COMMAND_0_CLE_BYTE_SIZE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_COMMAND_0_CLE_BYTE_SIZE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_COMMAND_0_CLE_BYTE_SIZE_CLE_BYTES1 _MK_ENUM_CONST(0) +#define NAND_COMMAND_0_CLE_BYTE_SIZE_CLE_BYTES2 _MK_ENUM_CONST(1) +#define NAND_COMMAND_0_CLE_BYTE_SIZE_CLE_BYTES3 _MK_ENUM_CONST(2) +#define NAND_COMMAND_0_CLE_BYTE_SIZE_CLE_BYTES4 _MK_ENUM_CONST(3) + +// Address cycle byte count Reserved +#define NAND_COMMAND_0_ALE_BYTE_SIZE_SHIFT _MK_SHIFT_CONST(0) +#define NAND_COMMAND_0_ALE_BYTE_SIZE_FIELD (_MK_MASK_CONST(0xf) << NAND_COMMAND_0_ALE_BYTE_SIZE_SHIFT) +#define NAND_COMMAND_0_ALE_BYTE_SIZE_RANGE 3:0 +#define NAND_COMMAND_0_ALE_BYTE_SIZE_WOFFSET 0x0 +#define NAND_COMMAND_0_ALE_BYTE_SIZE_DEFAULT _MK_MASK_CONST(0x4) +#define NAND_COMMAND_0_ALE_BYTE_SIZE_DEFAULT_MASK _MK_MASK_CONST(0xf) +#define NAND_COMMAND_0_ALE_BYTE_SIZE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_COMMAND_0_ALE_BYTE_SIZE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_COMMAND_0_ALE_BYTE_SIZE_ALE_BYTES1 _MK_ENUM_CONST(0) +#define NAND_COMMAND_0_ALE_BYTE_SIZE_ALE_BYTES2 _MK_ENUM_CONST(1) +#define NAND_COMMAND_0_ALE_BYTE_SIZE_ALE_BYTES3 _MK_ENUM_CONST(2) +#define NAND_COMMAND_0_ALE_BYTE_SIZE_ALE_BYTES4 _MK_ENUM_CONST(3) +#define NAND_COMMAND_0_ALE_BYTE_SIZE_ALE_BYTES5 _MK_ENUM_CONST(4) +#define NAND_COMMAND_0_ALE_BYTE_SIZE_ALE_BYTES6 _MK_ENUM_CONST(5) +#define NAND_COMMAND_0_ALE_BYTE_SIZE_ALE_BYTES7 _MK_ENUM_CONST(6) +#define NAND_COMMAND_0_ALE_BYTE_SIZE_ALE_BYTES8 _MK_ENUM_CONST(7) +#define NAND_COMMAND_0_ALE_BYTE_SIZE_ALE_BYTES9 _MK_ENUM_CONST(8) // // Reserved + +#define NAND_COMMAND_0_ALE_BYTE_SIZE_ALE_BYTES10 _MK_ENUM_CONST(9) // // Reserved + +#define NAND_COMMAND_0_ALE_BYTE_SIZE_ALE_BYTES11 _MK_ENUM_CONST(10) // // Reserved + +#define NAND_COMMAND_0_ALE_BYTE_SIZE_ALE_BYTES12 _MK_ENUM_CONST(11) // // Reserved + +#define NAND_COMMAND_0_ALE_BYTE_SIZE_ALE_BYTES13 _MK_ENUM_CONST(12) // // Reserved + +#define NAND_COMMAND_0_ALE_BYTE_SIZE_ALE_BYTES14 _MK_ENUM_CONST(13) // // Reserved + +#define NAND_COMMAND_0_ALE_BYTE_SIZE_ALE_BYTES15 _MK_ENUM_CONST(14) // // Reserved + +#define NAND_COMMAND_0_ALE_BYTE_SIZE_ALE_BYTES16 _MK_ENUM_CONST(15) + + +// Register NAND_STATUS_0 +#define NAND_STATUS_0 _MK_ADDR_CONST(0x4) +#define NAND_STATUS_0_SECURE 0x0 +#define NAND_STATUS_0_WORD_COUNT 0x1 +#define NAND_STATUS_0_RESET_VAL _MK_MASK_CONST(0x0) +#define NAND_STATUS_0_RESET_MASK _MK_MASK_CONST(0xffffffc1) +#define NAND_STATUS_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define NAND_STATUS_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_STATUS_0_READ_MASK _MK_MASK_CONST(0xffffffc1) +#define NAND_STATUS_0_WRITE_MASK _MK_MASK_CONST(0x0) +#define NAND_STATUS_0_NA2_SHIFT _MK_SHIFT_CONST(16) +#define NAND_STATUS_0_NA2_FIELD (_MK_MASK_CONST(0xffff) << NAND_STATUS_0_NA2_SHIFT) +#define NAND_STATUS_0_NA2_RANGE 31:16 +#define NAND_STATUS_0_NA2_WOFFSET 0x0 +#define NAND_STATUS_0_NA2_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_STATUS_0_NA2_DEFAULT_MASK _MK_MASK_CONST(0xffff) +#define NAND_STATUS_0_NA2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_STATUS_0_NA2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// 1 = Indicates flash7 is RDY +#define NAND_STATUS_0_RBSY7_SHIFT _MK_SHIFT_CONST(15) +#define NAND_STATUS_0_RBSY7_FIELD (_MK_MASK_CONST(0x1) << NAND_STATUS_0_RBSY7_SHIFT) +#define NAND_STATUS_0_RBSY7_RANGE 15:15 +#define NAND_STATUS_0_RBSY7_WOFFSET 0x0 +#define NAND_STATUS_0_RBSY7_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_STATUS_0_RBSY7_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_STATUS_0_RBSY7_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_STATUS_0_RBSY7_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// 1 = Indicates flash6 is RDY +#define NAND_STATUS_0_RBSY6_SHIFT _MK_SHIFT_CONST(14) +#define NAND_STATUS_0_RBSY6_FIELD (_MK_MASK_CONST(0x1) << NAND_STATUS_0_RBSY6_SHIFT) +#define NAND_STATUS_0_RBSY6_RANGE 14:14 +#define NAND_STATUS_0_RBSY6_WOFFSET 0x0 +#define NAND_STATUS_0_RBSY6_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_STATUS_0_RBSY6_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_STATUS_0_RBSY6_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_STATUS_0_RBSY6_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// 1 = Indicates flash5 is RDY +#define NAND_STATUS_0_RBSY5_SHIFT _MK_SHIFT_CONST(13) +#define NAND_STATUS_0_RBSY5_FIELD (_MK_MASK_CONST(0x1) << NAND_STATUS_0_RBSY5_SHIFT) +#define NAND_STATUS_0_RBSY5_RANGE 13:13 +#define NAND_STATUS_0_RBSY5_WOFFSET 0x0 +#define NAND_STATUS_0_RBSY5_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_STATUS_0_RBSY5_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_STATUS_0_RBSY5_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_STATUS_0_RBSY5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// 1 = Indicates flash4 is RDY +#define NAND_STATUS_0_RBSY4_SHIFT _MK_SHIFT_CONST(12) +#define NAND_STATUS_0_RBSY4_FIELD (_MK_MASK_CONST(0x1) << NAND_STATUS_0_RBSY4_SHIFT) +#define NAND_STATUS_0_RBSY4_RANGE 12:12 +#define NAND_STATUS_0_RBSY4_WOFFSET 0x0 +#define NAND_STATUS_0_RBSY4_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_STATUS_0_RBSY4_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_STATUS_0_RBSY4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_STATUS_0_RBSY4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// 1 = Indicates flash3 is RDY +#define NAND_STATUS_0_RBSY3_SHIFT _MK_SHIFT_CONST(11) +#define NAND_STATUS_0_RBSY3_FIELD (_MK_MASK_CONST(0x1) << NAND_STATUS_0_RBSY3_SHIFT) +#define NAND_STATUS_0_RBSY3_RANGE 11:11 +#define NAND_STATUS_0_RBSY3_WOFFSET 0x0 +#define NAND_STATUS_0_RBSY3_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_STATUS_0_RBSY3_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_STATUS_0_RBSY3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_STATUS_0_RBSY3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// 1 = Indicates flash2 is RDY +#define NAND_STATUS_0_RBSY2_SHIFT _MK_SHIFT_CONST(10) +#define NAND_STATUS_0_RBSY2_FIELD (_MK_MASK_CONST(0x1) << NAND_STATUS_0_RBSY2_SHIFT) +#define NAND_STATUS_0_RBSY2_RANGE 10:10 +#define NAND_STATUS_0_RBSY2_WOFFSET 0x0 +#define NAND_STATUS_0_RBSY2_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_STATUS_0_RBSY2_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_STATUS_0_RBSY2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_STATUS_0_RBSY2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// 1 = Indicates flash1 is RDY +#define NAND_STATUS_0_RBSY1_SHIFT _MK_SHIFT_CONST(9) +#define NAND_STATUS_0_RBSY1_FIELD (_MK_MASK_CONST(0x1) << NAND_STATUS_0_RBSY1_SHIFT) +#define NAND_STATUS_0_RBSY1_RANGE 9:9 +#define NAND_STATUS_0_RBSY1_WOFFSET 0x0 +#define NAND_STATUS_0_RBSY1_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_STATUS_0_RBSY1_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_STATUS_0_RBSY1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_STATUS_0_RBSY1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// 1 = Indicates flash0 is RDY +#define NAND_STATUS_0_RBSY0_SHIFT _MK_SHIFT_CONST(8) +#define NAND_STATUS_0_RBSY0_FIELD (_MK_MASK_CONST(0x1) << NAND_STATUS_0_RBSY0_SHIFT) +#define NAND_STATUS_0_RBSY0_RANGE 8:8 +#define NAND_STATUS_0_RBSY0_WOFFSET 0x0 +#define NAND_STATUS_0_RBSY0_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_STATUS_0_RBSY0_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_STATUS_0_RBSY0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_STATUS_0_RBSY0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// 1 = Indicates write cycles to flash are in progress +#define NAND_STATUS_0_WR_ACT_SHIFT _MK_SHIFT_CONST(7) +#define NAND_STATUS_0_WR_ACT_FIELD (_MK_MASK_CONST(0x1) << NAND_STATUS_0_WR_ACT_SHIFT) +#define NAND_STATUS_0_WR_ACT_RANGE 7:7 +#define NAND_STATUS_0_WR_ACT_WOFFSET 0x0 +#define NAND_STATUS_0_WR_ACT_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_STATUS_0_WR_ACT_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_STATUS_0_WR_ACT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_STATUS_0_WR_ACT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// 1 = Indicates read cycles to flash are in progress +#define NAND_STATUS_0_RD_ACT_SHIFT _MK_SHIFT_CONST(6) +#define NAND_STATUS_0_RD_ACT_FIELD (_MK_MASK_CONST(0x1) << NAND_STATUS_0_RD_ACT_SHIFT) +#define NAND_STATUS_0_RD_ACT_RANGE 6:6 +#define NAND_STATUS_0_RD_ACT_WOFFSET 0x0 +#define NAND_STATUS_0_RD_ACT_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_STATUS_0_RD_ACT_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_STATUS_0_RD_ACT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_STATUS_0_RD_ACT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// 1 = Indicates NAND controller is in IDLE state of operation, +// and there are no flash/DMA transactions are pending. +#define NAND_STATUS_0_ISEMPTY_SHIFT _MK_SHIFT_CONST(0) +#define NAND_STATUS_0_ISEMPTY_FIELD (_MK_MASK_CONST(0x1) << NAND_STATUS_0_ISEMPTY_SHIFT) +#define NAND_STATUS_0_ISEMPTY_RANGE 0:0 +#define NAND_STATUS_0_ISEMPTY_WOFFSET 0x0 +#define NAND_STATUS_0_ISEMPTY_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_STATUS_0_ISEMPTY_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_STATUS_0_ISEMPTY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_STATUS_0_ISEMPTY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register NAND_ISR_0 +#define NAND_ISR_0 _MK_ADDR_CONST(0x8) +#define NAND_ISR_0_SECURE 0x0 +#define NAND_ISR_0_WORD_COUNT 0x1 +#define NAND_ISR_0_RESET_VAL _MK_MASK_CONST(0x0) +#define NAND_ISR_0_RESET_MASK _MK_MASK_CONST(0xfffc) +#define NAND_ISR_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define NAND_ISR_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_ISR_0_READ_MASK _MK_MASK_CONST(0x100fffc) +#define NAND_ISR_0_WRITE_MASK _MK_MASK_CONST(0xfffc) +// 1 = Correctable OR Un-correctable errors occurred in the DMA transfer +// without regard to HW_ERR_CORRECTION feature is enabled or not. +// Use extended decode results in NAND_DEC_RESULT and NAND_DEC_STATUS_EXT +// to figure out further action for block replacement/wear leveling during +// file system management for s/w. +// Covers all ECC selection: RS/Hamming/BCH modes +#define NAND_ISR_0_CORRFAIL_ERR_SHIFT _MK_SHIFT_CONST(24) +#define NAND_ISR_0_CORRFAIL_ERR_FIELD (_MK_MASK_CONST(0x1) << NAND_ISR_0_CORRFAIL_ERR_SHIFT) +#define NAND_ISR_0_CORRFAIL_ERR_RANGE 24:24 +#define NAND_ISR_0_CORRFAIL_ERR_WOFFSET 0x0 +#define NAND_ISR_0_CORRFAIL_ERR_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_ISR_0_CORRFAIL_ERR_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_ISR_0_CORRFAIL_ERR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_ISR_0_CORRFAIL_ERR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// 1 = Flash7 is Ready interrupt occured +// This is SET only when NOT running in COMMAND QUEUE MODE +#define NAND_ISR_0_IS_RBSY7_SHIFT _MK_SHIFT_CONST(15) +#define NAND_ISR_0_IS_RBSY7_FIELD (_MK_MASK_CONST(0x1) << NAND_ISR_0_IS_RBSY7_SHIFT) +#define NAND_ISR_0_IS_RBSY7_RANGE 15:15 +#define NAND_ISR_0_IS_RBSY7_WOFFSET 0x0 +#define NAND_ISR_0_IS_RBSY7_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_ISR_0_IS_RBSY7_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_ISR_0_IS_RBSY7_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_ISR_0_IS_RBSY7_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// 1 = Flash6 is Ready interrupt occured +// This is SET only when NOT running in COMMAND QUEUE MODE +#define NAND_ISR_0_IS_RBSY6_SHIFT _MK_SHIFT_CONST(14) +#define NAND_ISR_0_IS_RBSY6_FIELD (_MK_MASK_CONST(0x1) << NAND_ISR_0_IS_RBSY6_SHIFT) +#define NAND_ISR_0_IS_RBSY6_RANGE 14:14 +#define NAND_ISR_0_IS_RBSY6_WOFFSET 0x0 +#define NAND_ISR_0_IS_RBSY6_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_ISR_0_IS_RBSY6_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_ISR_0_IS_RBSY6_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_ISR_0_IS_RBSY6_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// 1 = Flash5 is Ready interrupt occured +// This is SET only when NOT running in COMMAND QUEUE MODE +#define NAND_ISR_0_IS_RBSY5_SHIFT _MK_SHIFT_CONST(13) +#define NAND_ISR_0_IS_RBSY5_FIELD (_MK_MASK_CONST(0x1) << NAND_ISR_0_IS_RBSY5_SHIFT) +#define NAND_ISR_0_IS_RBSY5_RANGE 13:13 +#define NAND_ISR_0_IS_RBSY5_WOFFSET 0x0 +#define NAND_ISR_0_IS_RBSY5_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_ISR_0_IS_RBSY5_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_ISR_0_IS_RBSY5_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_ISR_0_IS_RBSY5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// 1 = Flash4 is Ready interrupt occured +// This is SET only when NOT running in COMMAND QUEUE MODE +#define NAND_ISR_0_IS_RBSY4_SHIFT _MK_SHIFT_CONST(12) +#define NAND_ISR_0_IS_RBSY4_FIELD (_MK_MASK_CONST(0x1) << NAND_ISR_0_IS_RBSY4_SHIFT) +#define NAND_ISR_0_IS_RBSY4_RANGE 12:12 +#define NAND_ISR_0_IS_RBSY4_WOFFSET 0x0 +#define NAND_ISR_0_IS_RBSY4_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_ISR_0_IS_RBSY4_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_ISR_0_IS_RBSY4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_ISR_0_IS_RBSY4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// 1 = Flash3 is Ready interrupt occured +// This is SET only when NOT running in COMMAND QUEUE MODE +#define NAND_ISR_0_IS_RBSY3_SHIFT _MK_SHIFT_CONST(11) +#define NAND_ISR_0_IS_RBSY3_FIELD (_MK_MASK_CONST(0x1) << NAND_ISR_0_IS_RBSY3_SHIFT) +#define NAND_ISR_0_IS_RBSY3_RANGE 11:11 +#define NAND_ISR_0_IS_RBSY3_WOFFSET 0x0 +#define NAND_ISR_0_IS_RBSY3_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_ISR_0_IS_RBSY3_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_ISR_0_IS_RBSY3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_ISR_0_IS_RBSY3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// 1 = Flash2 is Ready interrupt occured +// This is SET only when NOT running in COMMAND QUEUE MODE +#define NAND_ISR_0_IS_RBSY2_SHIFT _MK_SHIFT_CONST(10) +#define NAND_ISR_0_IS_RBSY2_FIELD (_MK_MASK_CONST(0x1) << NAND_ISR_0_IS_RBSY2_SHIFT) +#define NAND_ISR_0_IS_RBSY2_RANGE 10:10 +#define NAND_ISR_0_IS_RBSY2_WOFFSET 0x0 +#define NAND_ISR_0_IS_RBSY2_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_ISR_0_IS_RBSY2_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_ISR_0_IS_RBSY2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_ISR_0_IS_RBSY2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// 1 = Flash1 is Ready interrupt occured +// This is SET only when NOT running in COMMAND QUEUE MODE +#define NAND_ISR_0_IS_RBSY1_SHIFT _MK_SHIFT_CONST(9) +#define NAND_ISR_0_IS_RBSY1_FIELD (_MK_MASK_CONST(0x1) << NAND_ISR_0_IS_RBSY1_SHIFT) +#define NAND_ISR_0_IS_RBSY1_RANGE 9:9 +#define NAND_ISR_0_IS_RBSY1_WOFFSET 0x0 +#define NAND_ISR_0_IS_RBSY1_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_ISR_0_IS_RBSY1_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_ISR_0_IS_RBSY1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_ISR_0_IS_RBSY1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// 1 = Flash0 is Ready interrupt occured +// This is SET only when NOT running in COMMAND QUEUE MODE +#define NAND_ISR_0_IS_RBSY0_SHIFT _MK_SHIFT_CONST(8) +#define NAND_ISR_0_IS_RBSY0_FIELD (_MK_MASK_CONST(0x1) << NAND_ISR_0_IS_RBSY0_SHIFT) +#define NAND_ISR_0_IS_RBSY0_RANGE 8:8 +#define NAND_ISR_0_IS_RBSY0_WOFFSET 0x0 +#define NAND_ISR_0_IS_RBSY0_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_ISR_0_IS_RBSY0_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_ISR_0_IS_RBSY0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_ISR_0_IS_RBSY0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// 1 = FIFO under run interrupt occured +// this should not happen in general usage, if it happens +// there is a potential h/w issue. +#define NAND_ISR_0_IS_UND_SHIFT _MK_SHIFT_CONST(7) +#define NAND_ISR_0_IS_UND_FIELD (_MK_MASK_CONST(0x1) << NAND_ISR_0_IS_UND_SHIFT) +#define NAND_ISR_0_IS_UND_RANGE 7:7 +#define NAND_ISR_0_IS_UND_WOFFSET 0x0 +#define NAND_ISR_0_IS_UND_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_ISR_0_IS_UND_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_ISR_0_IS_UND_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_ISR_0_IS_UND_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// 1 = FIFO is Overrun +// this should not happen in general usage, if it happens +// there is potential h/w issue. +#define NAND_ISR_0_IS_OVR_SHIFT _MK_SHIFT_CONST(6) +#define NAND_ISR_0_IS_OVR_FIELD (_MK_MASK_CONST(0x1) << NAND_ISR_0_IS_OVR_SHIFT) +#define NAND_ISR_0_IS_OVR_RANGE 6:6 +#define NAND_ISR_0_IS_OVR_WOFFSET 0x0 +#define NAND_ISR_0_IS_OVR_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_ISR_0_IS_OVR_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_ISR_0_IS_OVR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_ISR_0_IS_OVR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// 1 = Command operations are completed as per NAND +// command register settings. +// This is set ONLY when not running in COMMAND QUEUE MODE +#define NAND_ISR_0_IS_CMD_DONE_SHIFT _MK_SHIFT_CONST(5) +#define NAND_ISR_0_IS_CMD_DONE_FIELD (_MK_MASK_CONST(0x1) << NAND_ISR_0_IS_CMD_DONE_SHIFT) +#define NAND_ISR_0_IS_CMD_DONE_RANGE 5:5 +#define NAND_ISR_0_IS_CMD_DONE_WOFFSET 0x0 +#define NAND_ISR_0_IS_CMD_DONE_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_ISR_0_IS_CMD_DONE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_ISR_0_IS_CMD_DONE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_ISR_0_IS_CMD_DONE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// 1 = ECC error generated for following reasons. +// ->ecc decode resulted in uncorrectable errors in one of +// sector(sub-page) +// ->ecc decode resulted in correctable errors more than +// trigger level as defined in TRIG_LVL in NAND_CONFIG +// register +// Bit is set for legacy mode of ECC selection with HW_ECC & ECC_TAG_EN only. +// i.e. for RS/Hamming selection. Will not be set for BCH selection +// +#define NAND_ISR_0_IS_ECC_ERR_SHIFT _MK_SHIFT_CONST(4) +#define NAND_ISR_0_IS_ECC_ERR_FIELD (_MK_MASK_CONST(0x1) << NAND_ISR_0_IS_ECC_ERR_SHIFT) +#define NAND_ISR_0_IS_ECC_ERR_RANGE 4:4 +#define NAND_ISR_0_IS_ECC_ERR_WOFFSET 0x0 +#define NAND_ISR_0_IS_ECC_ERR_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_ISR_0_IS_ECC_ERR_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_ISR_0_IS_ECC_ERR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_ISR_0_IS_ECC_ERR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// 1 = Command queue execution completed +#define NAND_ISR_0_IS_LL_DONE_SHIFT _MK_SHIFT_CONST(3) +#define NAND_ISR_0_IS_LL_DONE_FIELD (_MK_MASK_CONST(0x1) << NAND_ISR_0_IS_LL_DONE_SHIFT) +#define NAND_ISR_0_IS_LL_DONE_RANGE 3:3 +#define NAND_ISR_0_IS_LL_DONE_WOFFSET 0x0 +#define NAND_ISR_0_IS_LL_DONE_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_ISR_0_IS_LL_DONE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_ISR_0_IS_LL_DONE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_ISR_0_IS_LL_DONE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// 1 = One of the Command queue packet execution returned ERROR +#define NAND_ISR_0_IS_LL_ERR_SHIFT _MK_SHIFT_CONST(2) +#define NAND_ISR_0_IS_LL_ERR_FIELD (_MK_MASK_CONST(0x1) << NAND_ISR_0_IS_LL_ERR_SHIFT) +#define NAND_ISR_0_IS_LL_ERR_RANGE 2:2 +#define NAND_ISR_0_IS_LL_ERR_WOFFSET 0x0 +#define NAND_ISR_0_IS_LL_ERR_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_ISR_0_IS_LL_ERR_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_ISR_0_IS_LL_ERR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_ISR_0_IS_LL_ERR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register NAND_IER_0 +#define NAND_IER_0 _MK_ADDR_CONST(0xc) +#define NAND_IER_0_SECURE 0x0 +#define NAND_IER_0_WORD_COUNT 0x1 +#define NAND_IER_0_RESET_VAL _MK_MASK_CONST(0x0) +#define NAND_IER_0_RESET_MASK _MK_MASK_CONST(0xffffd) +#define NAND_IER_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define NAND_IER_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_IER_0_READ_MASK _MK_MASK_CONST(0xffffd) +#define NAND_IER_0_WRITE_MASK _MK_MASK_CONST(0xffffd) +// Trigger for correctable error Interrupts by main ECC RS decoder, if +// HW_ERR_CORRECTION feature is enabled. Mechansim for SW to get an idea +// on error pattern development over a period of usage. NAND controller +// will trigger interrupt if the current main page read transfer resulted +// in correctable errors reached this trigger value for Reed-Solomon selection. +// For example, of ECC_ERROR interrupt for t=4, with ERR_TRIG_VAL=3 could +// imply only one of the following. +// a) If DEC_FAIL = 1, one of the sub-page decode returned failure because no. +// of symbol errors are more than 4. +// b) If DEC_FAIL = 0, one of the sub-page decode returned 3 correctable errors. +#define NAND_IER_0_ERR_TRIG_VAL_SHIFT _MK_SHIFT_CONST(16) +#define NAND_IER_0_ERR_TRIG_VAL_FIELD (_MK_MASK_CONST(0xf) << NAND_IER_0_ERR_TRIG_VAL_SHIFT) +#define NAND_IER_0_ERR_TRIG_VAL_RANGE 19:16 +#define NAND_IER_0_ERR_TRIG_VAL_WOFFSET 0x0 +#define NAND_IER_0_ERR_TRIG_VAL_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_IER_0_ERR_TRIG_VAL_DEFAULT_MASK _MK_MASK_CONST(0xf) +#define NAND_IER_0_ERR_TRIG_VAL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_IER_0_ERR_TRIG_VAL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_IER_0_ERR_TRIG_VAL_CORR_ERRS_0 _MK_ENUM_CONST(0) // // Reports for every single error, equivalent to ECC_ERROR interrupt without +// HW_ERR_CORRECTION feature. + +#define NAND_IER_0_ERR_TRIG_VAL_CORR_ERRS_1 _MK_ENUM_CONST(1) +#define NAND_IER_0_ERR_TRIG_VAL_CORR_ERRS_2 _MK_ENUM_CONST(2) +#define NAND_IER_0_ERR_TRIG_VAL_CORR_ERRS_3 _MK_ENUM_CONST(3) +#define NAND_IER_0_ERR_TRIG_VAL_CORR_ERRS_4 _MK_ENUM_CONST(4) +#define NAND_IER_0_ERR_TRIG_VAL_CORR_ERRS_5 _MK_ENUM_CONST(5) +#define NAND_IER_0_ERR_TRIG_VAL_CORR_ERRS_6 _MK_ENUM_CONST(6) +#define NAND_IER_0_ERR_TRIG_VAL_CORR_ERRS_7 _MK_ENUM_CONST(7) +#define NAND_IER_0_ERR_TRIG_VAL_CORR_ERRS_8 _MK_ENUM_CONST(8) +#define NAND_IER_0_ERR_TRIG_VAL_CORR_ERRS_9 _MK_ENUM_CONST(9) +#define NAND_IER_0_ERR_TRIG_VAL_CORR_ERRS_10 _MK_ENUM_CONST(10) +#define NAND_IER_0_ERR_TRIG_VAL_CORR_ERRS_11 _MK_ENUM_CONST(11) +#define NAND_IER_0_ERR_TRIG_VAL_CORR_ERRS_12 _MK_ENUM_CONST(12) +#define NAND_IER_0_ERR_TRIG_VAL_CORR_ERRS_13 _MK_ENUM_CONST(13) +#define NAND_IER_0_ERR_TRIG_VAL_CORR_ERRS_14 _MK_ENUM_CONST(14) +#define NAND_IER_0_ERR_TRIG_VAL_CORR_ERRS_15 _MK_ENUM_CONST(15) + +// 1 = flash7 RBSY line High interrupt +#define NAND_IER_0_IE_RBSY7_SHIFT _MK_SHIFT_CONST(15) +#define NAND_IER_0_IE_RBSY7_FIELD (_MK_MASK_CONST(0x1) << NAND_IER_0_IE_RBSY7_SHIFT) +#define NAND_IER_0_IE_RBSY7_RANGE 15:15 +#define NAND_IER_0_IE_RBSY7_WOFFSET 0x0 +#define NAND_IER_0_IE_RBSY7_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_IER_0_IE_RBSY7_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_IER_0_IE_RBSY7_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_IER_0_IE_RBSY7_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_IER_0_IE_RBSY7_DISABLE _MK_ENUM_CONST(0) +#define NAND_IER_0_IE_RBSY7_ENABLE _MK_ENUM_CONST(1) + +// 1 = flash6 RBSY line High interrupt +#define NAND_IER_0_IE_RBSY6_SHIFT _MK_SHIFT_CONST(14) +#define NAND_IER_0_IE_RBSY6_FIELD (_MK_MASK_CONST(0x1) << NAND_IER_0_IE_RBSY6_SHIFT) +#define NAND_IER_0_IE_RBSY6_RANGE 14:14 +#define NAND_IER_0_IE_RBSY6_WOFFSET 0x0 +#define NAND_IER_0_IE_RBSY6_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_IER_0_IE_RBSY6_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_IER_0_IE_RBSY6_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_IER_0_IE_RBSY6_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_IER_0_IE_RBSY6_DISABLE _MK_ENUM_CONST(0) +#define NAND_IER_0_IE_RBSY6_ENABLE _MK_ENUM_CONST(1) + +// 1 = flash5 RBSY line High interrupt +#define NAND_IER_0_IE_RBSY5_SHIFT _MK_SHIFT_CONST(13) +#define NAND_IER_0_IE_RBSY5_FIELD (_MK_MASK_CONST(0x1) << NAND_IER_0_IE_RBSY5_SHIFT) +#define NAND_IER_0_IE_RBSY5_RANGE 13:13 +#define NAND_IER_0_IE_RBSY5_WOFFSET 0x0 +#define NAND_IER_0_IE_RBSY5_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_IER_0_IE_RBSY5_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_IER_0_IE_RBSY5_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_IER_0_IE_RBSY5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_IER_0_IE_RBSY5_DISABLE _MK_ENUM_CONST(0) +#define NAND_IER_0_IE_RBSY5_ENABLE _MK_ENUM_CONST(1) + +// 1 = flash4 RBSY line High interrupt +#define NAND_IER_0_IE_RBSY4_SHIFT _MK_SHIFT_CONST(12) +#define NAND_IER_0_IE_RBSY4_FIELD (_MK_MASK_CONST(0x1) << NAND_IER_0_IE_RBSY4_SHIFT) +#define NAND_IER_0_IE_RBSY4_RANGE 12:12 +#define NAND_IER_0_IE_RBSY4_WOFFSET 0x0 +#define NAND_IER_0_IE_RBSY4_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_IER_0_IE_RBSY4_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_IER_0_IE_RBSY4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_IER_0_IE_RBSY4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_IER_0_IE_RBSY4_DISABLE _MK_ENUM_CONST(0) +#define NAND_IER_0_IE_RBSY4_ENABLE _MK_ENUM_CONST(1) + +// 1 = flash3 RBSY line High interrupt +#define NAND_IER_0_IE_RBSY3_SHIFT _MK_SHIFT_CONST(11) +#define NAND_IER_0_IE_RBSY3_FIELD (_MK_MASK_CONST(0x1) << NAND_IER_0_IE_RBSY3_SHIFT) +#define NAND_IER_0_IE_RBSY3_RANGE 11:11 +#define NAND_IER_0_IE_RBSY3_WOFFSET 0x0 +#define NAND_IER_0_IE_RBSY3_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_IER_0_IE_RBSY3_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_IER_0_IE_RBSY3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_IER_0_IE_RBSY3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_IER_0_IE_RBSY3_DISABLE _MK_ENUM_CONST(0) +#define NAND_IER_0_IE_RBSY3_ENABLE _MK_ENUM_CONST(1) + +// 1 = flash2 RBSY line High interrupt +#define NAND_IER_0_IE_RBSY2_SHIFT _MK_SHIFT_CONST(10) +#define NAND_IER_0_IE_RBSY2_FIELD (_MK_MASK_CONST(0x1) << NAND_IER_0_IE_RBSY2_SHIFT) +#define NAND_IER_0_IE_RBSY2_RANGE 10:10 +#define NAND_IER_0_IE_RBSY2_WOFFSET 0x0 +#define NAND_IER_0_IE_RBSY2_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_IER_0_IE_RBSY2_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_IER_0_IE_RBSY2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_IER_0_IE_RBSY2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_IER_0_IE_RBSY2_DISABLE _MK_ENUM_CONST(0) +#define NAND_IER_0_IE_RBSY2_ENABLE _MK_ENUM_CONST(1) + +// 1 = flash1 RBSY line High interrupt +#define NAND_IER_0_IE_RBSY1_SHIFT _MK_SHIFT_CONST(9) +#define NAND_IER_0_IE_RBSY1_FIELD (_MK_MASK_CONST(0x1) << NAND_IER_0_IE_RBSY1_SHIFT) +#define NAND_IER_0_IE_RBSY1_RANGE 9:9 +#define NAND_IER_0_IE_RBSY1_WOFFSET 0x0 +#define NAND_IER_0_IE_RBSY1_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_IER_0_IE_RBSY1_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_IER_0_IE_RBSY1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_IER_0_IE_RBSY1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_IER_0_IE_RBSY1_DISABLE _MK_ENUM_CONST(0) +#define NAND_IER_0_IE_RBSY1_ENABLE _MK_ENUM_CONST(1) + +// 1 = flash0 RBSY line High interrupt +#define NAND_IER_0_IE_RBSY0_SHIFT _MK_SHIFT_CONST(8) +#define NAND_IER_0_IE_RBSY0_FIELD (_MK_MASK_CONST(0x1) << NAND_IER_0_IE_RBSY0_SHIFT) +#define NAND_IER_0_IE_RBSY0_RANGE 8:8 +#define NAND_IER_0_IE_RBSY0_WOFFSET 0x0 +#define NAND_IER_0_IE_RBSY0_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_IER_0_IE_RBSY0_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_IER_0_IE_RBSY0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_IER_0_IE_RBSY0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_IER_0_IE_RBSY0_DISABLE _MK_ENUM_CONST(0) +#define NAND_IER_0_IE_RBSY0_ENABLE _MK_ENUM_CONST(1) + +// 1 = FIFO underrun interrupt +#define NAND_IER_0_IE_UND_SHIFT _MK_SHIFT_CONST(7) +#define NAND_IER_0_IE_UND_FIELD (_MK_MASK_CONST(0x1) << NAND_IER_0_IE_UND_SHIFT) +#define NAND_IER_0_IE_UND_RANGE 7:7 +#define NAND_IER_0_IE_UND_WOFFSET 0x0 +#define NAND_IER_0_IE_UND_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_IER_0_IE_UND_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_IER_0_IE_UND_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_IER_0_IE_UND_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_IER_0_IE_UND_DISABLE _MK_ENUM_CONST(0) +#define NAND_IER_0_IE_UND_ENABLE _MK_ENUM_CONST(1) + +// 1 = FIFO overrun interupt +#define NAND_IER_0_IE_OVR_SHIFT _MK_SHIFT_CONST(6) +#define NAND_IER_0_IE_OVR_FIELD (_MK_MASK_CONST(0x1) << NAND_IER_0_IE_OVR_SHIFT) +#define NAND_IER_0_IE_OVR_RANGE 6:6 +#define NAND_IER_0_IE_OVR_WOFFSET 0x0 +#define NAND_IER_0_IE_OVR_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_IER_0_IE_OVR_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_IER_0_IE_OVR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_IER_0_IE_OVR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_IER_0_IE_OVR_DISABLE _MK_ENUM_CONST(0) +#define NAND_IER_0_IE_OVR_ENABLE _MK_ENUM_CONST(1) + +// 1 = Command operations are completed as per NAND +// command register settings. +#define NAND_IER_0_IE_CMD_DONE_SHIFT _MK_SHIFT_CONST(5) +#define NAND_IER_0_IE_CMD_DONE_FIELD (_MK_MASK_CONST(0x1) << NAND_IER_0_IE_CMD_DONE_SHIFT) +#define NAND_IER_0_IE_CMD_DONE_RANGE 5:5 +#define NAND_IER_0_IE_CMD_DONE_WOFFSET 0x0 +#define NAND_IER_0_IE_CMD_DONE_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_IER_0_IE_CMD_DONE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_IER_0_IE_CMD_DONE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_IER_0_IE_CMD_DONE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_IER_0_IE_CMD_DONE_DISABLE _MK_ENUM_CONST(0) +#define NAND_IER_0_IE_CMD_DONE_ENABLE _MK_ENUM_CONST(1) + +// 1 = ECC error interrupt +// please refer to IS_ECC_ERR above for interrupt event +// details +#define NAND_IER_0_IE_ECC_ERR_SHIFT _MK_SHIFT_CONST(4) +#define NAND_IER_0_IE_ECC_ERR_FIELD (_MK_MASK_CONST(0x1) << NAND_IER_0_IE_ECC_ERR_SHIFT) +#define NAND_IER_0_IE_ECC_ERR_RANGE 4:4 +#define NAND_IER_0_IE_ECC_ERR_WOFFSET 0x0 +#define NAND_IER_0_IE_ECC_ERR_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_IER_0_IE_ECC_ERR_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_IER_0_IE_ECC_ERR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_IER_0_IE_ECC_ERR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_IER_0_IE_ECC_ERR_DISABLE _MK_ENUM_CONST(0) +#define NAND_IER_0_IE_ECC_ERR_ENABLE _MK_ENUM_CONST(1) + +// Command queue execution completion interrupt +#define NAND_IER_0_IE_LL_DONE_SHIFT _MK_SHIFT_CONST(3) +#define NAND_IER_0_IE_LL_DONE_FIELD (_MK_MASK_CONST(0x1) << NAND_IER_0_IE_LL_DONE_SHIFT) +#define NAND_IER_0_IE_LL_DONE_RANGE 3:3 +#define NAND_IER_0_IE_LL_DONE_WOFFSET 0x0 +#define NAND_IER_0_IE_LL_DONE_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_IER_0_IE_LL_DONE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_IER_0_IE_LL_DONE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_IER_0_IE_LL_DONE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_IER_0_IE_LL_DONE_DISABLE _MK_ENUM_CONST(0) +#define NAND_IER_0_IE_LL_DONE_ENABLE _MK_ENUM_CONST(1) + +// Flash errors in Command queue execution interrupt +#define NAND_IER_0_IE_LL_ERR_SHIFT _MK_SHIFT_CONST(2) +#define NAND_IER_0_IE_LL_ERR_FIELD (_MK_MASK_CONST(0x1) << NAND_IER_0_IE_LL_ERR_SHIFT) +#define NAND_IER_0_IE_LL_ERR_RANGE 2:2 +#define NAND_IER_0_IE_LL_ERR_WOFFSET 0x0 +#define NAND_IER_0_IE_LL_ERR_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_IER_0_IE_LL_ERR_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_IER_0_IE_LL_ERR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_IER_0_IE_LL_ERR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_IER_0_IE_LL_ERR_DISABLE _MK_ENUM_CONST(0) +#define NAND_IER_0_IE_LL_ERR_ENABLE _MK_ENUM_CONST(1) + +// 0 = Masks all of the interrupts, and interrupt to +// signal to cpu is disabled. +#define NAND_IER_0_GIE_SHIFT _MK_SHIFT_CONST(0) +#define NAND_IER_0_GIE_FIELD (_MK_MASK_CONST(0x1) << NAND_IER_0_GIE_SHIFT) +#define NAND_IER_0_GIE_RANGE 0:0 +#define NAND_IER_0_GIE_WOFFSET 0x0 +#define NAND_IER_0_GIE_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_IER_0_GIE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_IER_0_GIE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_IER_0_GIE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_IER_0_GIE_DISABLE _MK_ENUM_CONST(0) +#define NAND_IER_0_GIE_ENABLE _MK_ENUM_CONST(1) + + +// Register NAND_CONFIG_0 +#define NAND_CONFIG_0 _MK_ADDR_CONST(0x10) +#define NAND_CONFIG_0_SECURE 0x0 +#define NAND_CONFIG_0_WORD_COUNT 0x1 +#define NAND_CONFIG_0_RESET_VAL _MK_MASK_CONST(0x10030000) +#define NAND_CONFIG_0_RESET_MASK _MK_MASK_CONST(0xfbffffff) +#define NAND_CONFIG_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define NAND_CONFIG_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_CONFIG_0_READ_MASK _MK_MASK_CONST(0xfbffffff) +#define NAND_CONFIG_0_WRITE_MASK _MK_MASK_CONST(0xfbffffff) +// HW Error detection enable for Main page read data +#define NAND_CONFIG_0_HW_ECC_SHIFT _MK_SHIFT_CONST(31) +#define NAND_CONFIG_0_HW_ECC_FIELD (_MK_MASK_CONST(0x1) << NAND_CONFIG_0_HW_ECC_SHIFT) +#define NAND_CONFIG_0_HW_ECC_RANGE 31:31 +#define NAND_CONFIG_0_HW_ECC_WOFFSET 0x0 +#define NAND_CONFIG_0_HW_ECC_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_CONFIG_0_HW_ECC_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_CONFIG_0_HW_ECC_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_CONFIG_0_HW_ECC_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_CONFIG_0_HW_ECC_DISABLE _MK_ENUM_CONST(0) +#define NAND_CONFIG_0_HW_ECC_ENABLE _MK_ENUM_CONST(1) + +// HE Error detection algorithm selection +#define NAND_CONFIG_0_ECC_SEL_SHIFT _MK_SHIFT_CONST(30) +#define NAND_CONFIG_0_ECC_SEL_FIELD (_MK_MASK_CONST(0x1) << NAND_CONFIG_0_ECC_SEL_SHIFT) +#define NAND_CONFIG_0_ECC_SEL_RANGE 30:30 +#define NAND_CONFIG_0_ECC_SEL_WOFFSET 0x0 +#define NAND_CONFIG_0_ECC_SEL_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_CONFIG_0_ECC_SEL_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_CONFIG_0_ECC_SEL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_CONFIG_0_ECC_SEL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_CONFIG_0_ECC_SEL_HAMMING _MK_ENUM_CONST(0) +#define NAND_CONFIG_0_ECC_SEL_RS _MK_ENUM_CONST(1) + +// Enable Auto HW correction. Emulates SW behavior of reading the error +// vectors from system buffer as pointed in the error vector address register, +// applies correction and updates the memory word with corrected data. +// This is done on page basis as soon as the decode information is avialable +// as the flash read is placed in memory. +#define NAND_CONFIG_0_HW_ERR_CORRECTION_SHIFT _MK_SHIFT_CONST(29) +#define NAND_CONFIG_0_HW_ERR_CORRECTION_FIELD (_MK_MASK_CONST(0x1) << NAND_CONFIG_0_HW_ERR_CORRECTION_SHIFT) +#define NAND_CONFIG_0_HW_ERR_CORRECTION_RANGE 29:29 +#define NAND_CONFIG_0_HW_ERR_CORRECTION_WOFFSET 0x0 +#define NAND_CONFIG_0_HW_ERR_CORRECTION_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_CONFIG_0_HW_ERR_CORRECTION_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_CONFIG_0_HW_ERR_CORRECTION_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_CONFIG_0_HW_ERR_CORRECTION_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_CONFIG_0_HW_ERR_CORRECTION_DISABLE _MK_ENUM_CONST(0) +#define NAND_CONFIG_0_HW_ERR_CORRECTION_ENABLE _MK_ENUM_CONST(1) + +// Enable next page flash READ data transfer even before current page ECC +// Decode is completed. If disabled, new page READ is started only +// after the previous page flash read, ECC decode(detection) are completed. +#define NAND_CONFIG_0_PIPELINE_EN_SHIFT _MK_SHIFT_CONST(28) +#define NAND_CONFIG_0_PIPELINE_EN_FIELD (_MK_MASK_CONST(0x1) << NAND_CONFIG_0_PIPELINE_EN_SHIFT) +#define NAND_CONFIG_0_PIPELINE_EN_RANGE 28:28 +#define NAND_CONFIG_0_PIPELINE_EN_WOFFSET 0x0 +#define NAND_CONFIG_0_PIPELINE_EN_DEFAULT _MK_MASK_CONST(0x1) +#define NAND_CONFIG_0_PIPELINE_EN_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_CONFIG_0_PIPELINE_EN_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_CONFIG_0_PIPELINE_EN_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_CONFIG_0_PIPELINE_EN_DISABLE _MK_ENUM_CONST(0) +#define NAND_CONFIG_0_PIPELINE_EN_ENABLE _MK_ENUM_CONST(1) + +// HW Error detection enable for Spare read data +#define NAND_CONFIG_0_ECC_EN_TAG_SHIFT _MK_SHIFT_CONST(27) +#define NAND_CONFIG_0_ECC_EN_TAG_FIELD (_MK_MASK_CONST(0x1) << NAND_CONFIG_0_ECC_EN_TAG_SHIFT) +#define NAND_CONFIG_0_ECC_EN_TAG_RANGE 27:27 +#define NAND_CONFIG_0_ECC_EN_TAG_WOFFSET 0x0 +#define NAND_CONFIG_0_ECC_EN_TAG_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_CONFIG_0_ECC_EN_TAG_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_CONFIG_0_ECC_EN_TAG_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_CONFIG_0_ECC_EN_TAG_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_CONFIG_0_ECC_EN_TAG_DISABLE _MK_ENUM_CONST(0) +#define NAND_CONFIG_0_ECC_EN_TAG_ENABLE _MK_ENUM_CONST(1) + +// HW Error correction algorithm tValue for RS EDC selction 11 = Rsvd +#define NAND_CONFIG_0_TVALUE_SHIFT _MK_SHIFT_CONST(24) +#define NAND_CONFIG_0_TVALUE_FIELD (_MK_MASK_CONST(0x3) << NAND_CONFIG_0_TVALUE_SHIFT) +#define NAND_CONFIG_0_TVALUE_RANGE 25:24 +#define NAND_CONFIG_0_TVALUE_WOFFSET 0x0 +#define NAND_CONFIG_0_TVALUE_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_CONFIG_0_TVALUE_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define NAND_CONFIG_0_TVALUE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_CONFIG_0_TVALUE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_CONFIG_0_TVALUE_TVAL4 _MK_ENUM_CONST(0) // // (t=4) 4 bit error correction per each 512 bytes of data + +#define NAND_CONFIG_0_TVALUE_TVAL6 _MK_ENUM_CONST(1) // // (t=6) 6 bit error correction per each 512 bytes of data + +#define NAND_CONFIG_0_TVALUE_TVAL8 _MK_ENUM_CONST(2) // // (t=8) 8 bit error correction per each 512 bytes of data + +#define NAND_CONFIG_0_TVALUE_TVAL_RSVD _MK_ENUM_CONST(3) + +// Skip spare region in flash to start read/write bytes after +// completing the main area transfer. +// SKIP_SPAE_SEL below indicates how many bytes in spare +// area of flash to be skipped over either for reading/writing +// all spare access will offset to this. +#define NAND_CONFIG_0_SKIP_SPARE_SHIFT _MK_SHIFT_CONST(23) +#define NAND_CONFIG_0_SKIP_SPARE_FIELD (_MK_MASK_CONST(0x1) << NAND_CONFIG_0_SKIP_SPARE_SHIFT) +#define NAND_CONFIG_0_SKIP_SPARE_RANGE 23:23 +#define NAND_CONFIG_0_SKIP_SPARE_WOFFSET 0x0 +#define NAND_CONFIG_0_SKIP_SPARE_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_CONFIG_0_SKIP_SPARE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_CONFIG_0_SKIP_SPARE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_CONFIG_0_SKIP_SPARE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_CONFIG_0_SKIP_SPARE_DISABLE _MK_ENUM_CONST(0) +#define NAND_CONFIG_0_SKIP_SPARE_ENABLE _MK_ENUM_CONST(1) + +// RBSY0 is from Flash card 0 +#define NAND_CONFIG_0_COM_BSY_SHIFT _MK_SHIFT_CONST(22) +#define NAND_CONFIG_0_COM_BSY_FIELD (_MK_MASK_CONST(0x1) << NAND_CONFIG_0_COM_BSY_SHIFT) +#define NAND_CONFIG_0_COM_BSY_RANGE 22:22 +#define NAND_CONFIG_0_COM_BSY_WOFFSET 0x0 +#define NAND_CONFIG_0_COM_BSY_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_CONFIG_0_COM_BSY_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_CONFIG_0_COM_BSY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_CONFIG_0_COM_BSY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_CONFIG_0_COM_BSY_DISABLE _MK_ENUM_CONST(0) // // RBSY0 seen by HW is wired AND of all flash cards connected + +#define NAND_CONFIG_0_COM_BSY_ENABLE _MK_ENUM_CONST(1) + +//Flash read/write databus width selection Datsbus width 8-bit +#define NAND_CONFIG_0_BUS_WIDTH_SHIFT _MK_SHIFT_CONST(21) +#define NAND_CONFIG_0_BUS_WIDTH_FIELD (_MK_MASK_CONST(0x1) << NAND_CONFIG_0_BUS_WIDTH_SHIFT) +#define NAND_CONFIG_0_BUS_WIDTH_RANGE 21:21 +#define NAND_CONFIG_0_BUS_WIDTH_WOFFSET 0x0 +#define NAND_CONFIG_0_BUS_WIDTH_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_CONFIG_0_BUS_WIDTH_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_CONFIG_0_BUS_WIDTH_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_CONFIG_0_BUS_WIDTH_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_CONFIG_0_BUS_WIDTH_BUS_WIDTH_8 _MK_ENUM_CONST(0) // // Databus width 16-bit + +#define NAND_CONFIG_0_BUS_WIDTH_BUS_WIDTH_16 _MK_ENUM_CONST(1) + +// LPDDR1 mode of pin ordering Pin ordering to be package friendly with LPDDR1 +#define NAND_CONFIG_0_LPDDR1_MODE_SHIFT _MK_SHIFT_CONST(20) +#define NAND_CONFIG_0_LPDDR1_MODE_FIELD (_MK_MASK_CONST(0x1) << NAND_CONFIG_0_LPDDR1_MODE_SHIFT) +#define NAND_CONFIG_0_LPDDR1_MODE_RANGE 20:20 +#define NAND_CONFIG_0_LPDDR1_MODE_WOFFSET 0x0 +#define NAND_CONFIG_0_LPDDR1_MODE_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_CONFIG_0_LPDDR1_MODE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_CONFIG_0_LPDDR1_MODE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_CONFIG_0_LPDDR1_MODE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_CONFIG_0_LPDDR1_MODE_DISABLE _MK_ENUM_CONST(0) // // Standard mode of pin ordering + +#define NAND_CONFIG_0_LPDDR1_MODE_ENABLE _MK_ENUM_CONST(1) + +// EDO mode of flash read data sampling sampled on posedge of REN +#define NAND_CONFIG_0_EDO_MODE_SHIFT _MK_SHIFT_CONST(19) +#define NAND_CONFIG_0_EDO_MODE_FIELD (_MK_MASK_CONST(0x1) << NAND_CONFIG_0_EDO_MODE_SHIFT) +#define NAND_CONFIG_0_EDO_MODE_RANGE 19:19 +#define NAND_CONFIG_0_EDO_MODE_WOFFSET 0x0 +#define NAND_CONFIG_0_EDO_MODE_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_CONFIG_0_EDO_MODE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_CONFIG_0_EDO_MODE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_CONFIG_0_EDO_MODE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_CONFIG_0_EDO_MODE_DISABLE _MK_ENUM_CONST(0) // // sampled on completion of read cycle time + +#define NAND_CONFIG_0_EDO_MODE_ENABLE _MK_ENUM_CONST(1) + +// Page size selection - depends on Flash used. +#define NAND_CONFIG_0_PAGE_SIZE_SEL_SHIFT _MK_SHIFT_CONST(16) +#define NAND_CONFIG_0_PAGE_SIZE_SEL_FIELD (_MK_MASK_CONST(0x7) << NAND_CONFIG_0_PAGE_SIZE_SEL_SHIFT) +#define NAND_CONFIG_0_PAGE_SIZE_SEL_RANGE 18:16 +#define NAND_CONFIG_0_PAGE_SIZE_SEL_WOFFSET 0x0 +#define NAND_CONFIG_0_PAGE_SIZE_SEL_DEFAULT _MK_MASK_CONST(0x3) +#define NAND_CONFIG_0_PAGE_SIZE_SEL_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define NAND_CONFIG_0_PAGE_SIZE_SEL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_CONFIG_0_PAGE_SIZE_SEL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_CONFIG_0_PAGE_SIZE_SEL_PAGE_SIZE_256 _MK_ENUM_CONST(0) +#define NAND_CONFIG_0_PAGE_SIZE_SEL_PAGE_SIZE_512 _MK_ENUM_CONST(1) +#define NAND_CONFIG_0_PAGE_SIZE_SEL_PAGE_SIZE_1024 _MK_ENUM_CONST(2) +#define NAND_CONFIG_0_PAGE_SIZE_SEL_PAGE_SIZE_2048 _MK_ENUM_CONST(3) +#define NAND_CONFIG_0_PAGE_SIZE_SEL_PAGE_SIZE_4096 _MK_ENUM_CONST(4) +#define NAND_CONFIG_0_PAGE_SIZE_SEL_PAGE_SIZE_RSVD1 _MK_ENUM_CONST(5) +#define NAND_CONFIG_0_PAGE_SIZE_SEL_PAGE_SIZE_RSVD2 _MK_ENUM_CONST(6) +#define NAND_CONFIG_0_PAGE_SIZE_SEL_PAGE_SIZE_RSVD3 _MK_ENUM_CONST(7) + +// Size in granularity of 4 bytes to skippedd for spare access +#define NAND_CONFIG_0_SKIP_SPARE_SEL_SHIFT _MK_SHIFT_CONST(14) +#define NAND_CONFIG_0_SKIP_SPARE_SEL_FIELD (_MK_MASK_CONST(0x3) << NAND_CONFIG_0_SKIP_SPARE_SEL_SHIFT) +#define NAND_CONFIG_0_SKIP_SPARE_SEL_RANGE 15:14 +#define NAND_CONFIG_0_SKIP_SPARE_SEL_WOFFSET 0x0 +#define NAND_CONFIG_0_SKIP_SPARE_SEL_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_CONFIG_0_SKIP_SPARE_SEL_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define NAND_CONFIG_0_SKIP_SPARE_SEL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_CONFIG_0_SKIP_SPARE_SEL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_CONFIG_0_SKIP_SPARE_SEL_SKIP_SPARE_SIZE_4 _MK_ENUM_CONST(0) +#define NAND_CONFIG_0_SKIP_SPARE_SEL_SKIP_SPARE_SIZE_8 _MK_ENUM_CONST(1) +#define NAND_CONFIG_0_SKIP_SPARE_SEL_SKIP_SPARE_SIZE_12 _MK_ENUM_CONST(2) +#define NAND_CONFIG_0_SKIP_SPARE_SEL_SKIP_SPARE_SIZE_16 _MK_ENUM_CONST(3) + +// Debug mode selection for HW debug +#define NAND_CONFIG_0_DEBUG_MODE_SHIFT _MK_SHIFT_CONST(13) +#define NAND_CONFIG_0_DEBUG_MODE_FIELD (_MK_MASK_CONST(0x1) << NAND_CONFIG_0_DEBUG_MODE_SHIFT) +#define NAND_CONFIG_0_DEBUG_MODE_RANGE 13:13 +#define NAND_CONFIG_0_DEBUG_MODE_WOFFSET 0x0 +#define NAND_CONFIG_0_DEBUG_MODE_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_CONFIG_0_DEBUG_MODE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_CONFIG_0_DEBUG_MODE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_CONFIG_0_DEBUG_MODE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// Debug selection for HW debug +#define NAND_CONFIG_0_DEBUG_SEL_SHIFT _MK_SHIFT_CONST(9) +#define NAND_CONFIG_0_DEBUG_SEL_FIELD (_MK_MASK_CONST(0xf) << NAND_CONFIG_0_DEBUG_SEL_SHIFT) +#define NAND_CONFIG_0_DEBUG_SEL_RANGE 12:9 +#define NAND_CONFIG_0_DEBUG_SEL_WOFFSET 0x0 +#define NAND_CONFIG_0_DEBUG_SEL_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_CONFIG_0_DEBUG_SEL_DEFAULT_MASK _MK_MASK_CONST(0xf) +#define NAND_CONFIG_0_DEBUG_SEL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_CONFIG_0_DEBUG_SEL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// Block Size in Bytes for TAG data from spare area of flash. +// This is used for specifying the size of the TAG Block data byets +// to be move/from to spare area. Used when B_VALID is true. +// Specified in Bytes (n-1 encoding) +#define NAND_CONFIG_0_TAG_BYTE_SIZE_SHIFT _MK_SHIFT_CONST(0) +#define NAND_CONFIG_0_TAG_BYTE_SIZE_FIELD (_MK_MASK_CONST(0x1ff) << NAND_CONFIG_0_TAG_BYTE_SIZE_SHIFT) +#define NAND_CONFIG_0_TAG_BYTE_SIZE_RANGE 8:0 +#define NAND_CONFIG_0_TAG_BYTE_SIZE_WOFFSET 0x0 +#define NAND_CONFIG_0_TAG_BYTE_SIZE_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_CONFIG_0_TAG_BYTE_SIZE_DEFAULT_MASK _MK_MASK_CONST(0x1ff) +#define NAND_CONFIG_0_TAG_BYTE_SIZE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_CONFIG_0_TAG_BYTE_SIZE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register NAND_TIMING_0 +#define NAND_TIMING_0 _MK_ADDR_CONST(0x14) +#define NAND_TIMING_0_SECURE 0x0 +#define NAND_TIMING_0_WORD_COUNT 0x1 +#define NAND_TIMING_0_RESET_VAL _MK_MASK_CONST(0x0) +#define NAND_TIMING_0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define NAND_TIMING_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define NAND_TIMING_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_TIMING_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define NAND_TIMING_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +// Read pulse width(RE Low time)timing for status read cycles +// Generated timing = (n+1) * NAND_CLK_PERIOD ns, +// +// ----------------------------------------------------------------------------- +// GUIDELINE: for tRP_RESP/tRP timing +// ----------------------------------------------------------------------------- +// +// non-EDO mode: Max(tRP, tREA) timing + 6ns (round trip delay) +// EDO mode: tRP timing from flash datasheet +// +// Notes: +// (1)"round trip delay" to account for - REN out PAD delay + REN out board delay +// + DATA driven OUT from flash to chip input + DATA INPUT pad delay. +// +// Based on AP15 timings, PAD delays attribute to 4ns and rest +// 2ns is estimated for board delays. If it's more than one need to +// increase the "round trip delay" number to come up +// with "tRP/TRP_RESP" timing requirement. +// (2)For EDO modes - since controller latches data without regard +// to `nRE' (REN) posedge tREA, round trip delay factors need not +// be considered. +#define NAND_TIMING_0_TRP_RESP_CNT_SHIFT _MK_SHIFT_CONST(28) +#define NAND_TIMING_0_TRP_RESP_CNT_FIELD (_MK_MASK_CONST(0xf) << NAND_TIMING_0_TRP_RESP_CNT_SHIFT) +#define NAND_TIMING_0_TRP_RESP_CNT_RANGE 31:28 +#define NAND_TIMING_0_TRP_RESP_CNT_WOFFSET 0x0 +#define NAND_TIMING_0_TRP_RESP_CNT_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_TIMING_0_TRP_RESP_CNT_DEFAULT_MASK _MK_MASK_CONST(0xf) +#define NAND_TIMING_0_TRP_RESP_CNT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_TIMING_0_TRP_RESP_CNT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// WE High to RBSY low asserted (by flash) timing +// Generated timing = (n+1) * NAND_CLK_PERIOD ns. +// ----------------------------------------------------------------------------- +// GUIDELINE: Refer to tWB timing from flash datasheet +// ----------------------------------------------------------------------------- +#define NAND_TIMING_0_TWB_CNT_SHIFT _MK_SHIFT_CONST(24) +#define NAND_TIMING_0_TWB_CNT_FIELD (_MK_MASK_CONST(0xf) << NAND_TIMING_0_TWB_CNT_SHIFT) +#define NAND_TIMING_0_TWB_CNT_RANGE 27:24 +#define NAND_TIMING_0_TWB_CNT_WOFFSET 0x0 +#define NAND_TIMING_0_TWB_CNT_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_TIMING_0_TWB_CNT_DEFAULT_MASK _MK_MASK_CONST(0xf) +#define NAND_TIMING_0_TWB_CNT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_TIMING_0_TWB_CNT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// RBSY High to RE low timing +// Generated timing = (n+3) * NAND_CLK_PERIOD ns. +// ----------------------------------------------------------------------------- +// GUIDELINE: Program Max(tCR, tAR, tRR) timings from flash data sheet +// ----------------------------------------------------------------------------- +#define NAND_TIMING_0_TCR_TAR_TRR_CNT_SHIFT _MK_SHIFT_CONST(20) +#define NAND_TIMING_0_TCR_TAR_TRR_CNT_FIELD (_MK_MASK_CONST(0xf) << NAND_TIMING_0_TCR_TAR_TRR_CNT_SHIFT) +#define NAND_TIMING_0_TCR_TAR_TRR_CNT_RANGE 23:20 +#define NAND_TIMING_0_TCR_TAR_TRR_CNT_WOFFSET 0x0 +#define NAND_TIMING_0_TCR_TAR_TRR_CNT_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_TIMING_0_TCR_TAR_TRR_CNT_DEFAULT_MASK _MK_MASK_CONST(0xf) +#define NAND_TIMING_0_TCR_TAR_TRR_CNT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_TIMING_0_TCR_TAR_TRR_CNT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// WE High to RE Low timing - Status Read Cycles +// Generated timing = (n+1) * NAND_CLK_PERIOD ns. +// ----------------------------------------------------------------------------- +// GUIDELINE: Refer to tWHR timing from flash data sheet +// ----------------------------------------------------------------------------- +#define NAND_TIMING_0_TWHR_CNT_SHIFT _MK_SHIFT_CONST(16) +#define NAND_TIMING_0_TWHR_CNT_FIELD (_MK_MASK_CONST(0xf) << NAND_TIMING_0_TWHR_CNT_SHIFT) +#define NAND_TIMING_0_TWHR_CNT_RANGE 19:16 +#define NAND_TIMING_0_TWHR_CNT_WOFFSET 0x0 +#define NAND_TIMING_0_TWHR_CNT_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_TIMING_0_TWHR_CNT_DEFAULT_MASK _MK_MASK_CONST(0xf) +#define NAND_TIMING_0_TWHR_CNT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_TIMING_0_TWHR_CNT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// CS/CLE/ALE Setup/Hold time. +// Generated timing: +// tCLS/tALS/tCS [for setup timing] = [tCS_CNT + tWP CNT + 2 ] * NAND_CLK_PERIOD +// tCLH/tALH/tCH [for hold timing] = [tCS_CNT + tWH CNT + 3 ] * NAND_CLK_PERIO +// ----------------------------------------------------------------------------- +// GUIDELINE: Program for Max(tCS, tCH, tALS, tALH, tCLS, TCLH) timings from +// flash datasheet +// ----------------------------------------------------------------------------- +// This timing is met timing requirements. +// 1. from CE Low -> WE posedge of CLE/ALE. +// 2. from WE posedge of CLE to-> WE posedge of ALE. +#define NAND_TIMING_0_TCS_CNT_SHIFT _MK_SHIFT_CONST(14) +#define NAND_TIMING_0_TCS_CNT_FIELD (_MK_MASK_CONST(0x3) << NAND_TIMING_0_TCS_CNT_SHIFT) +#define NAND_TIMING_0_TCS_CNT_RANGE 15:14 +#define NAND_TIMING_0_TCS_CNT_WOFFSET 0x0 +#define NAND_TIMING_0_TCS_CNT_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_TIMING_0_TCS_CNT_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define NAND_TIMING_0_TCS_CNT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_TIMING_0_TCS_CNT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// Write pulse HOLD time +// Generated timing = (n+1) * NAND_CLK_PERIOD ns. +// ----------------------------------------------------------------------------- +// GUIDELINE: Refer to tWH timing from flash datasheet +// ----------------------------------------------------------------------------- +#define NAND_TIMING_0_TWH_CNT_SHIFT _MK_SHIFT_CONST(12) +#define NAND_TIMING_0_TWH_CNT_FIELD (_MK_MASK_CONST(0x3) << NAND_TIMING_0_TWH_CNT_SHIFT) +#define NAND_TIMING_0_TWH_CNT_RANGE 13:12 +#define NAND_TIMING_0_TWH_CNT_WOFFSET 0x0 +#define NAND_TIMING_0_TWH_CNT_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_TIMING_0_TWH_CNT_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define NAND_TIMING_0_TWH_CNT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_TIMING_0_TWH_CNT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// Write pulse width time +// Generated timing = (n+1) * NAND_CLK_PERIOD ns. +// ----------------------------------------------------------------------------- +// GUIDELINE: Refer to tWP timing from flash datasheet +// ----------------------------------------------------------------------------- +#define NAND_TIMING_0_TWP_CNT_SHIFT _MK_SHIFT_CONST(8) +#define NAND_TIMING_0_TWP_CNT_FIELD (_MK_MASK_CONST(0xf) << NAND_TIMING_0_TWP_CNT_SHIFT) +#define NAND_TIMING_0_TWP_CNT_RANGE 11:8 +#define NAND_TIMING_0_TWP_CNT_WOFFSET 0x0 +#define NAND_TIMING_0_TWP_CNT_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_TIMING_0_TWP_CNT_DEFAULT_MASK _MK_MASK_CONST(0xf) +#define NAND_TIMING_0_TWP_CNT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_TIMING_0_TWP_CNT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define NAND_TIMING_0_NA1_SHIFT _MK_SHIFT_CONST(6) +#define NAND_TIMING_0_NA1_FIELD (_MK_MASK_CONST(0x3) << NAND_TIMING_0_NA1_SHIFT) +#define NAND_TIMING_0_NA1_RANGE 7:6 +#define NAND_TIMING_0_NA1_WOFFSET 0x0 +#define NAND_TIMING_0_NA1_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_TIMING_0_NA1_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define NAND_TIMING_0_NA1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_TIMING_0_NA1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// Read pulse HOLD time +// Generated timing = (n+1) * NAND_CLK_PERIOD ns. +// ----------------------------------------------------------------------------- +// GUIDELINE: Refer to tRH timing from flash datasheet +// ----------------------------------------------------------------------------- +#define NAND_TIMING_0_TRH_CNT_SHIFT _MK_SHIFT_CONST(4) +#define NAND_TIMING_0_TRH_CNT_FIELD (_MK_MASK_CONST(0x3) << NAND_TIMING_0_TRH_CNT_SHIFT) +#define NAND_TIMING_0_TRH_CNT_RANGE 5:4 +#define NAND_TIMING_0_TRH_CNT_WOFFSET 0x0 +#define NAND_TIMING_0_TRH_CNT_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_TIMING_0_TRH_CNT_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define NAND_TIMING_0_TRH_CNT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_TIMING_0_TRH_CNT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// Read pulse width(RE Low time)timing for Data read cycles +// Generated timing = (n+1) * NAND_CLKS, +// +// where n - value programmed in the tRP_RESP_CNT field of timing register. +// +// ----------------------------------------------------------------------------- +// GUIDELINE: tRP_RESP/tRP timing register programming +// ----------------------------------------------------------------------------- +// non-EDO mode: Max(tRP, tREA) timing + 6ns (round trip delay) +// EDO mode: tRP timing +//Notes: +// (1) "round trip delay" to account for - REN out PAD delay + REN out board delay +// + DATA driven OUT from flash to chip input + DATA INPUT pad delay. +// Based on AP15 timings, PAD delays attribute to 4ns and rest +// 2ns is estimated for board delays. If it's more than one need to +// increase the "round trip delay" number to come up +// with "tRP/TRP_RESP" timing requirement. +// (2) For EDO modes - since controller latches data without regard +// to `nRE' (REN) posedge tREA, round trip delay factors need not +// be considered. +#define NAND_TIMING_0_TRP_CNT_SHIFT _MK_SHIFT_CONST(0) +#define NAND_TIMING_0_TRP_CNT_FIELD (_MK_MASK_CONST(0xf) << NAND_TIMING_0_TRP_CNT_SHIFT) +#define NAND_TIMING_0_TRP_CNT_RANGE 3:0 +#define NAND_TIMING_0_TRP_CNT_WOFFSET 0x0 +#define NAND_TIMING_0_TRP_CNT_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_TIMING_0_TRP_CNT_DEFAULT_MASK _MK_MASK_CONST(0xf) +#define NAND_TIMING_0_TRP_CNT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_TIMING_0_TRP_CNT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register NAND_RESP_0 +#define NAND_RESP_0 _MK_ADDR_CONST(0x18) +#define NAND_RESP_0_SECURE 0x0 +#define NAND_RESP_0_WORD_COUNT 0x1 +#define NAND_RESP_0_RESET_VAL _MK_MASK_CONST(0x0) +#define NAND_RESP_0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define NAND_RESP_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define NAND_RESP_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_RESP_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define NAND_RESP_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +// Write/Response data byte 3 (MSB) +#define NAND_RESP_0_BYTE3_SHIFT _MK_SHIFT_CONST(24) +#define NAND_RESP_0_BYTE3_FIELD (_MK_MASK_CONST(0xff) << NAND_RESP_0_BYTE3_SHIFT) +#define NAND_RESP_0_BYTE3_RANGE 31:24 +#define NAND_RESP_0_BYTE3_WOFFSET 0x0 +#define NAND_RESP_0_BYTE3_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_RESP_0_BYTE3_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define NAND_RESP_0_BYTE3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_RESP_0_BYTE3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// Write/Response data byte 2 +#define NAND_RESP_0_BYTE2_SHIFT _MK_SHIFT_CONST(16) +#define NAND_RESP_0_BYTE2_FIELD (_MK_MASK_CONST(0xff) << NAND_RESP_0_BYTE2_SHIFT) +#define NAND_RESP_0_BYTE2_RANGE 23:16 +#define NAND_RESP_0_BYTE2_WOFFSET 0x0 +#define NAND_RESP_0_BYTE2_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_RESP_0_BYTE2_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define NAND_RESP_0_BYTE2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_RESP_0_BYTE2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// Write/Response data byte 1 +#define NAND_RESP_0_BYTE1_SHIFT _MK_SHIFT_CONST(8) +#define NAND_RESP_0_BYTE1_FIELD (_MK_MASK_CONST(0xff) << NAND_RESP_0_BYTE1_SHIFT) +#define NAND_RESP_0_BYTE1_RANGE 15:8 +#define NAND_RESP_0_BYTE1_WOFFSET 0x0 +#define NAND_RESP_0_BYTE1_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_RESP_0_BYTE1_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define NAND_RESP_0_BYTE1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_RESP_0_BYTE1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// Write/Response data byte 0 (LSB) +#define NAND_RESP_0_BYTE0_SHIFT _MK_SHIFT_CONST(0) +#define NAND_RESP_0_BYTE0_FIELD (_MK_MASK_CONST(0xff) << NAND_RESP_0_BYTE0_SHIFT) +#define NAND_RESP_0_BYTE0_RANGE 7:0 +#define NAND_RESP_0_BYTE0_WOFFSET 0x0 +#define NAND_RESP_0_BYTE0_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_RESP_0_BYTE0_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define NAND_RESP_0_BYTE0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_RESP_0_BYTE0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register NAND_TIMING2_0 +#define NAND_TIMING2_0 _MK_ADDR_CONST(0x1c) +#define NAND_TIMING2_0_SECURE 0x0 +#define NAND_TIMING2_0_WORD_COUNT 0x1 +#define NAND_TIMING2_0_RESET_VAL _MK_MASK_CONST(0x0) +#define NAND_TIMING2_0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define NAND_TIMING2_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define NAND_TIMING2_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_TIMING2_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define NAND_TIMING2_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define NAND_TIMING2_0_NA1_SHIFT _MK_SHIFT_CONST(4) +#define NAND_TIMING2_0_NA1_FIELD (_MK_MASK_CONST(0xfffffff) << NAND_TIMING2_0_NA1_SHIFT) +#define NAND_TIMING2_0_NA1_RANGE 31:4 +#define NAND_TIMING2_0_NA1_WOFFSET 0x0 +#define NAND_TIMING2_0_NA1_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_TIMING2_0_NA1_DEFAULT_MASK _MK_MASK_CONST(0xfffffff) +#define NAND_TIMING2_0_NA1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_TIMING2_0_NA1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// WE posedge of address cycle to WE posedge of data cycle +// +// Generated timing = (n+3) * NAND_CLK_PERIOD ns. +// ----------------------------------------------------------------------------- +// GUIDELINE: Refer to tADL timing from flash datasheet +// ----------------------------------------------------------------------------- +// +// Please note that timing generated from controller is for the duration from +// ALE low to WP low. In the convention of flash vendor tADL timing +// this amounts to = (n+3)*NAND_CLK_PERIOD + tWH(previous address cycle) +// + tWP(following data cycle). +// +#define NAND_TIMING2_0_TADL_CNT_SHIFT _MK_SHIFT_CONST(0) +#define NAND_TIMING2_0_TADL_CNT_FIELD (_MK_MASK_CONST(0xf) << NAND_TIMING2_0_TADL_CNT_SHIFT) +#define NAND_TIMING2_0_TADL_CNT_RANGE 3:0 +#define NAND_TIMING2_0_TADL_CNT_WOFFSET 0x0 +#define NAND_TIMING2_0_TADL_CNT_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_TIMING2_0_TADL_CNT_DEFAULT_MASK _MK_MASK_CONST(0xf) +#define NAND_TIMING2_0_TADL_CNT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_TIMING2_0_TADL_CNT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register NAND_CMD_REG1_0 // Commmand cycle generation use these during COMMAND1 time +#define NAND_CMD_REG1_0 _MK_ADDR_CONST(0x20) +#define NAND_CMD_REG1_0_SECURE 0x0 +#define NAND_CMD_REG1_0_WORD_COUNT 0x1 +#define NAND_CMD_REG1_0_RESET_VAL _MK_MASK_CONST(0x0) +#define NAND_CMD_REG1_0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define NAND_CMD_REG1_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define NAND_CMD_REG1_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_CMD_REG1_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define NAND_CMD_REG1_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +// Command byte 3(MSB) +#define NAND_CMD_REG1_0_CMD_BYTE3_SHIFT _MK_SHIFT_CONST(24) +#define NAND_CMD_REG1_0_CMD_BYTE3_FIELD (_MK_MASK_CONST(0xff) << NAND_CMD_REG1_0_CMD_BYTE3_SHIFT) +#define NAND_CMD_REG1_0_CMD_BYTE3_RANGE 31:24 +#define NAND_CMD_REG1_0_CMD_BYTE3_WOFFSET 0x0 +#define NAND_CMD_REG1_0_CMD_BYTE3_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_CMD_REG1_0_CMD_BYTE3_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define NAND_CMD_REG1_0_CMD_BYTE3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_CMD_REG1_0_CMD_BYTE3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// Command byte 2 +#define NAND_CMD_REG1_0_CMD_BYTE2_SHIFT _MK_SHIFT_CONST(16) +#define NAND_CMD_REG1_0_CMD_BYTE2_FIELD (_MK_MASK_CONST(0xff) << NAND_CMD_REG1_0_CMD_BYTE2_SHIFT) +#define NAND_CMD_REG1_0_CMD_BYTE2_RANGE 23:16 +#define NAND_CMD_REG1_0_CMD_BYTE2_WOFFSET 0x0 +#define NAND_CMD_REG1_0_CMD_BYTE2_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_CMD_REG1_0_CMD_BYTE2_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define NAND_CMD_REG1_0_CMD_BYTE2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_CMD_REG1_0_CMD_BYTE2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// Command byte 1 +#define NAND_CMD_REG1_0_CMD_BYTE1_SHIFT _MK_SHIFT_CONST(8) +#define NAND_CMD_REG1_0_CMD_BYTE1_FIELD (_MK_MASK_CONST(0xff) << NAND_CMD_REG1_0_CMD_BYTE1_SHIFT) +#define NAND_CMD_REG1_0_CMD_BYTE1_RANGE 15:8 +#define NAND_CMD_REG1_0_CMD_BYTE1_WOFFSET 0x0 +#define NAND_CMD_REG1_0_CMD_BYTE1_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_CMD_REG1_0_CMD_BYTE1_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define NAND_CMD_REG1_0_CMD_BYTE1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_CMD_REG1_0_CMD_BYTE1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// Command byte 0(LSB) +#define NAND_CMD_REG1_0_CMD_BYTE0_SHIFT _MK_SHIFT_CONST(0) +#define NAND_CMD_REG1_0_CMD_BYTE0_FIELD (_MK_MASK_CONST(0xff) << NAND_CMD_REG1_0_CMD_BYTE0_SHIFT) +#define NAND_CMD_REG1_0_CMD_BYTE0_RANGE 7:0 +#define NAND_CMD_REG1_0_CMD_BYTE0_WOFFSET 0x0 +#define NAND_CMD_REG1_0_CMD_BYTE0_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_CMD_REG1_0_CMD_BYTE0_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define NAND_CMD_REG1_0_CMD_BYTE0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_CMD_REG1_0_CMD_BYTE0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register NAND_CMD_REG2_0 // Commmand cycle generation use these during COMMAND2 time +#define NAND_CMD_REG2_0 _MK_ADDR_CONST(0x24) +#define NAND_CMD_REG2_0_SECURE 0x0 +#define NAND_CMD_REG2_0_WORD_COUNT 0x1 +#define NAND_CMD_REG2_0_RESET_VAL _MK_MASK_CONST(0x0) +#define NAND_CMD_REG2_0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define NAND_CMD_REG2_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define NAND_CMD_REG2_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_CMD_REG2_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define NAND_CMD_REG2_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +// Command byte 3(MSB) +#define NAND_CMD_REG2_0_CMD_BYTE3_SHIFT _MK_SHIFT_CONST(24) +#define NAND_CMD_REG2_0_CMD_BYTE3_FIELD (_MK_MASK_CONST(0xff) << NAND_CMD_REG2_0_CMD_BYTE3_SHIFT) +#define NAND_CMD_REG2_0_CMD_BYTE3_RANGE 31:24 +#define NAND_CMD_REG2_0_CMD_BYTE3_WOFFSET 0x0 +#define NAND_CMD_REG2_0_CMD_BYTE3_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_CMD_REG2_0_CMD_BYTE3_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define NAND_CMD_REG2_0_CMD_BYTE3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_CMD_REG2_0_CMD_BYTE3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// Command byte 2 +#define NAND_CMD_REG2_0_CMD_BYTE2_SHIFT _MK_SHIFT_CONST(16) +#define NAND_CMD_REG2_0_CMD_BYTE2_FIELD (_MK_MASK_CONST(0xff) << NAND_CMD_REG2_0_CMD_BYTE2_SHIFT) +#define NAND_CMD_REG2_0_CMD_BYTE2_RANGE 23:16 +#define NAND_CMD_REG2_0_CMD_BYTE2_WOFFSET 0x0 +#define NAND_CMD_REG2_0_CMD_BYTE2_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_CMD_REG2_0_CMD_BYTE2_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define NAND_CMD_REG2_0_CMD_BYTE2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_CMD_REG2_0_CMD_BYTE2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// Command byte 1 +#define NAND_CMD_REG2_0_CMD_BYTE1_SHIFT _MK_SHIFT_CONST(8) +#define NAND_CMD_REG2_0_CMD_BYTE1_FIELD (_MK_MASK_CONST(0xff) << NAND_CMD_REG2_0_CMD_BYTE1_SHIFT) +#define NAND_CMD_REG2_0_CMD_BYTE1_RANGE 15:8 +#define NAND_CMD_REG2_0_CMD_BYTE1_WOFFSET 0x0 +#define NAND_CMD_REG2_0_CMD_BYTE1_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_CMD_REG2_0_CMD_BYTE1_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define NAND_CMD_REG2_0_CMD_BYTE1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_CMD_REG2_0_CMD_BYTE1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// Command byte 0(LSB) +#define NAND_CMD_REG2_0_CMD_BYTE0_SHIFT _MK_SHIFT_CONST(0) +#define NAND_CMD_REG2_0_CMD_BYTE0_FIELD (_MK_MASK_CONST(0xff) << NAND_CMD_REG2_0_CMD_BYTE0_SHIFT) +#define NAND_CMD_REG2_0_CMD_BYTE0_RANGE 7:0 +#define NAND_CMD_REG2_0_CMD_BYTE0_WOFFSET 0x0 +#define NAND_CMD_REG2_0_CMD_BYTE0_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_CMD_REG2_0_CMD_BYTE0_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define NAND_CMD_REG2_0_CMD_BYTE0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_CMD_REG2_0_CMD_BYTE0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register NAND_ADDR_REG1_0 // Adderss cycle generation use these bytes +#define NAND_ADDR_REG1_0 _MK_ADDR_CONST(0x28) +#define NAND_ADDR_REG1_0_SECURE 0x0 +#define NAND_ADDR_REG1_0_WORD_COUNT 0x1 +#define NAND_ADDR_REG1_0_RESET_VAL _MK_MASK_CONST(0x0) +#define NAND_ADDR_REG1_0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define NAND_ADDR_REG1_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define NAND_ADDR_REG1_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_ADDR_REG1_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define NAND_ADDR_REG1_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +// Address byte 3 +#define NAND_ADDR_REG1_0_ADDR_BYTE3_SHIFT _MK_SHIFT_CONST(24) +#define NAND_ADDR_REG1_0_ADDR_BYTE3_FIELD (_MK_MASK_CONST(0xff) << NAND_ADDR_REG1_0_ADDR_BYTE3_SHIFT) +#define NAND_ADDR_REG1_0_ADDR_BYTE3_RANGE 31:24 +#define NAND_ADDR_REG1_0_ADDR_BYTE3_WOFFSET 0x0 +#define NAND_ADDR_REG1_0_ADDR_BYTE3_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_ADDR_REG1_0_ADDR_BYTE3_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define NAND_ADDR_REG1_0_ADDR_BYTE3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_ADDR_REG1_0_ADDR_BYTE3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// Address byte 2 +#define NAND_ADDR_REG1_0_ADDR_BYTE2_SHIFT _MK_SHIFT_CONST(16) +#define NAND_ADDR_REG1_0_ADDR_BYTE2_FIELD (_MK_MASK_CONST(0xff) << NAND_ADDR_REG1_0_ADDR_BYTE2_SHIFT) +#define NAND_ADDR_REG1_0_ADDR_BYTE2_RANGE 23:16 +#define NAND_ADDR_REG1_0_ADDR_BYTE2_WOFFSET 0x0 +#define NAND_ADDR_REG1_0_ADDR_BYTE2_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_ADDR_REG1_0_ADDR_BYTE2_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define NAND_ADDR_REG1_0_ADDR_BYTE2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_ADDR_REG1_0_ADDR_BYTE2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// Address byte 1 +#define NAND_ADDR_REG1_0_ADDR_BYTE1_SHIFT _MK_SHIFT_CONST(8) +#define NAND_ADDR_REG1_0_ADDR_BYTE1_FIELD (_MK_MASK_CONST(0xff) << NAND_ADDR_REG1_0_ADDR_BYTE1_SHIFT) +#define NAND_ADDR_REG1_0_ADDR_BYTE1_RANGE 15:8 +#define NAND_ADDR_REG1_0_ADDR_BYTE1_WOFFSET 0x0 +#define NAND_ADDR_REG1_0_ADDR_BYTE1_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_ADDR_REG1_0_ADDR_BYTE1_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define NAND_ADDR_REG1_0_ADDR_BYTE1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_ADDR_REG1_0_ADDR_BYTE1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// Address byte 0 (LSB) +#define NAND_ADDR_REG1_0_ADDR_BYTE0_SHIFT _MK_SHIFT_CONST(0) +#define NAND_ADDR_REG1_0_ADDR_BYTE0_FIELD (_MK_MASK_CONST(0xff) << NAND_ADDR_REG1_0_ADDR_BYTE0_SHIFT) +#define NAND_ADDR_REG1_0_ADDR_BYTE0_RANGE 7:0 +#define NAND_ADDR_REG1_0_ADDR_BYTE0_WOFFSET 0x0 +#define NAND_ADDR_REG1_0_ADDR_BYTE0_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_ADDR_REG1_0_ADDR_BYTE0_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define NAND_ADDR_REG1_0_ADDR_BYTE0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_ADDR_REG1_0_ADDR_BYTE0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register NAND_ADDR_REG2_0 // Adderss cycle generation use these bytes +#define NAND_ADDR_REG2_0 _MK_ADDR_CONST(0x2c) +#define NAND_ADDR_REG2_0_SECURE 0x0 +#define NAND_ADDR_REG2_0_WORD_COUNT 0x1 +#define NAND_ADDR_REG2_0_RESET_VAL _MK_MASK_CONST(0x0) +#define NAND_ADDR_REG2_0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define NAND_ADDR_REG2_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define NAND_ADDR_REG2_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_ADDR_REG2_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define NAND_ADDR_REG2_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +// Address byte 3 +#define NAND_ADDR_REG2_0_ADDR_BYTE7_SHIFT _MK_SHIFT_CONST(24) +#define NAND_ADDR_REG2_0_ADDR_BYTE7_FIELD (_MK_MASK_CONST(0xff) << NAND_ADDR_REG2_0_ADDR_BYTE7_SHIFT) +#define NAND_ADDR_REG2_0_ADDR_BYTE7_RANGE 31:24 +#define NAND_ADDR_REG2_0_ADDR_BYTE7_WOFFSET 0x0 +#define NAND_ADDR_REG2_0_ADDR_BYTE7_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_ADDR_REG2_0_ADDR_BYTE7_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define NAND_ADDR_REG2_0_ADDR_BYTE7_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_ADDR_REG2_0_ADDR_BYTE7_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// Address byte 2 +#define NAND_ADDR_REG2_0_ADDR_BYTE6_SHIFT _MK_SHIFT_CONST(16) +#define NAND_ADDR_REG2_0_ADDR_BYTE6_FIELD (_MK_MASK_CONST(0xff) << NAND_ADDR_REG2_0_ADDR_BYTE6_SHIFT) +#define NAND_ADDR_REG2_0_ADDR_BYTE6_RANGE 23:16 +#define NAND_ADDR_REG2_0_ADDR_BYTE6_WOFFSET 0x0 +#define NAND_ADDR_REG2_0_ADDR_BYTE6_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_ADDR_REG2_0_ADDR_BYTE6_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define NAND_ADDR_REG2_0_ADDR_BYTE6_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_ADDR_REG2_0_ADDR_BYTE6_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// Address byte 1 +#define NAND_ADDR_REG2_0_ADDR_BYTE5_SHIFT _MK_SHIFT_CONST(8) +#define NAND_ADDR_REG2_0_ADDR_BYTE5_FIELD (_MK_MASK_CONST(0xff) << NAND_ADDR_REG2_0_ADDR_BYTE5_SHIFT) +#define NAND_ADDR_REG2_0_ADDR_BYTE5_RANGE 15:8 +#define NAND_ADDR_REG2_0_ADDR_BYTE5_WOFFSET 0x0 +#define NAND_ADDR_REG2_0_ADDR_BYTE5_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_ADDR_REG2_0_ADDR_BYTE5_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define NAND_ADDR_REG2_0_ADDR_BYTE5_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_ADDR_REG2_0_ADDR_BYTE5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// Address byte 0 (LSB) +#define NAND_ADDR_REG2_0_ADDR_BYTE4_SHIFT _MK_SHIFT_CONST(0) +#define NAND_ADDR_REG2_0_ADDR_BYTE4_FIELD (_MK_MASK_CONST(0xff) << NAND_ADDR_REG2_0_ADDR_BYTE4_SHIFT) +#define NAND_ADDR_REG2_0_ADDR_BYTE4_RANGE 7:0 +#define NAND_ADDR_REG2_0_ADDR_BYTE4_WOFFSET 0x0 +#define NAND_ADDR_REG2_0_ADDR_BYTE4_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_ADDR_REG2_0_ADDR_BYTE4_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define NAND_ADDR_REG2_0_ADDR_BYTE4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_ADDR_REG2_0_ADDR_BYTE4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register NAND_DMA_MST_CTRL_0 +#define NAND_DMA_MST_CTRL_0 _MK_ADDR_CONST(0x30) +#define NAND_DMA_MST_CTRL_0_SECURE 0x0 +#define NAND_DMA_MST_CTRL_0_WORD_COUNT 0x1 +#define NAND_DMA_MST_CTRL_0_RESET_VAL _MK_MASK_CONST(0x24000000) +#define NAND_DMA_MST_CTRL_0_RESET_MASK _MK_MASK_CONST(0xff100006) +#define NAND_DMA_MST_CTRL_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define NAND_DMA_MST_CTRL_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_DMA_MST_CTRL_0_READ_MASK _MK_MASK_CONST(0xff100006) +#define NAND_DMA_MST_CTRL_0_WRITE_MASK _MK_MASK_CONST(0x7f100006) +// Enable NAND DMA interface for data transfers. Auto clear type. +// HW clears when programmed length of data transfer is completed. +#define NAND_DMA_MST_CTRL_0_DMA_GO_SHIFT _MK_SHIFT_CONST(31) +#define NAND_DMA_MST_CTRL_0_DMA_GO_FIELD (_MK_MASK_CONST(0x1) << NAND_DMA_MST_CTRL_0_DMA_GO_SHIFT) +#define NAND_DMA_MST_CTRL_0_DMA_GO_RANGE 31:31 +#define NAND_DMA_MST_CTRL_0_DMA_GO_WOFFSET 0x0 +#define NAND_DMA_MST_CTRL_0_DMA_GO_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_DMA_MST_CTRL_0_DMA_GO_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_DMA_MST_CTRL_0_DMA_GO_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_DMA_MST_CTRL_0_DMA_GO_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_DMA_MST_CTRL_0_DMA_GO_DISABLE _MK_ENUM_CONST(0) +#define NAND_DMA_MST_CTRL_0_DMA_GO_ENABLE _MK_ENUM_CONST(1) + +// DMA data transfer direction Read from system and write to flash +#define NAND_DMA_MST_CTRL_0_DIR_SHIFT _MK_SHIFT_CONST(30) +#define NAND_DMA_MST_CTRL_0_DIR_FIELD (_MK_MASK_CONST(0x1) << NAND_DMA_MST_CTRL_0_DIR_SHIFT) +#define NAND_DMA_MST_CTRL_0_DIR_RANGE 30:30 +#define NAND_DMA_MST_CTRL_0_DIR_WOFFSET 0x0 +#define NAND_DMA_MST_CTRL_0_DIR_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_DMA_MST_CTRL_0_DIR_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_DMA_MST_CTRL_0_DIR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_DMA_MST_CTRL_0_DIR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_DMA_MST_CTRL_0_DIR_DMA_RD _MK_ENUM_CONST(0) // // Write to system and read from flash + +#define NAND_DMA_MST_CTRL_0_DIR_DMA_WR _MK_ENUM_CONST(1) + +// DMA peformace feature enable. as soon as the Error vectors equal to BURST SIZE programmed +// received DMA suspends current data transfers and moves to +// Error vector transfer and waits till that page decode is completed. +// Potentially if Error vectors are received around each 512 sub-page +// boundary this could cause stall of next page READ data transfers +// causing performance degradation. To take advantage of +// PIPELINE_EN ECC decoder pipeline capability this should be enabled. +#define NAND_DMA_MST_CTRL_0_DMA_PERF_EN_SHIFT _MK_SHIFT_CONST(29) +#define NAND_DMA_MST_CTRL_0_DMA_PERF_EN_FIELD (_MK_MASK_CONST(0x1) << NAND_DMA_MST_CTRL_0_DMA_PERF_EN_SHIFT) +#define NAND_DMA_MST_CTRL_0_DMA_PERF_EN_RANGE 29:29 +#define NAND_DMA_MST_CTRL_0_DMA_PERF_EN_WOFFSET 0x0 +#define NAND_DMA_MST_CTRL_0_DMA_PERF_EN_DEFAULT _MK_MASK_CONST(0x1) +#define NAND_DMA_MST_CTRL_0_DMA_PERF_EN_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_DMA_MST_CTRL_0_DMA_PERF_EN_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_DMA_MST_CTRL_0_DMA_PERF_EN_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_DMA_MST_CTRL_0_DMA_PERF_EN_DISABLE _MK_ENUM_CONST(0) // // + +#define NAND_DMA_MST_CTRL_0_DMA_PERF_EN_ENABLE _MK_ENUM_CONST(1) + +// Enable interrupt on DMA transfer completion +#define NAND_DMA_MST_CTRL_0_IE_DMA_DONE_SHIFT _MK_SHIFT_CONST(28) +#define NAND_DMA_MST_CTRL_0_IE_DMA_DONE_FIELD (_MK_MASK_CONST(0x1) << NAND_DMA_MST_CTRL_0_IE_DMA_DONE_SHIFT) +#define NAND_DMA_MST_CTRL_0_IE_DMA_DONE_RANGE 28:28 +#define NAND_DMA_MST_CTRL_0_IE_DMA_DONE_WOFFSET 0x0 +#define NAND_DMA_MST_CTRL_0_IE_DMA_DONE_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_DMA_MST_CTRL_0_IE_DMA_DONE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_DMA_MST_CTRL_0_IE_DMA_DONE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_DMA_MST_CTRL_0_IE_DMA_DONE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_DMA_MST_CTRL_0_IE_DMA_DONE_DISABLE _MK_ENUM_CONST(0) +#define NAND_DMA_MST_CTRL_0_IE_DMA_DONE_ENABLE _MK_ENUM_CONST(1) + +// increments the Error Vector destination address continuously +// till the total DMA transfer size is done +#define NAND_DMA_MST_CTRL_0_REUSE_BUFFER_SHIFT _MK_SHIFT_CONST(27) +#define NAND_DMA_MST_CTRL_0_REUSE_BUFFER_FIELD (_MK_MASK_CONST(0x1) << NAND_DMA_MST_CTRL_0_REUSE_BUFFER_SHIFT) +#define NAND_DMA_MST_CTRL_0_REUSE_BUFFER_RANGE 27:27 +#define NAND_DMA_MST_CTRL_0_REUSE_BUFFER_WOFFSET 0x0 +#define NAND_DMA_MST_CTRL_0_REUSE_BUFFER_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_DMA_MST_CTRL_0_REUSE_BUFFER_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_DMA_MST_CTRL_0_REUSE_BUFFER_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_DMA_MST_CTRL_0_REUSE_BUFFER_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_DMA_MST_CTRL_0_REUSE_BUFFER_DISABLE _MK_ENUM_CONST(0) +#define NAND_DMA_MST_CTRL_0_REUSE_BUFFER_ENABLE _MK_ENUM_CONST(1) + +// DMA burst size +#define NAND_DMA_MST_CTRL_0_BURST_SIZE_SHIFT _MK_SHIFT_CONST(24) +#define NAND_DMA_MST_CTRL_0_BURST_SIZE_FIELD (_MK_MASK_CONST(0x7) << NAND_DMA_MST_CTRL_0_BURST_SIZE_SHIFT) +#define NAND_DMA_MST_CTRL_0_BURST_SIZE_RANGE 26:24 +#define NAND_DMA_MST_CTRL_0_BURST_SIZE_WOFFSET 0x0 +#define NAND_DMA_MST_CTRL_0_BURST_SIZE_DEFAULT _MK_MASK_CONST(0x4) +#define NAND_DMA_MST_CTRL_0_BURST_SIZE_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define NAND_DMA_MST_CTRL_0_BURST_SIZE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_DMA_MST_CTRL_0_BURST_SIZE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_DMA_MST_CTRL_0_BURST_SIZE_BURST_RSVD1 _MK_ENUM_CONST(0) +#define NAND_DMA_MST_CTRL_0_BURST_SIZE_BURST_RSVD2 _MK_ENUM_CONST(1) +#define NAND_DMA_MST_CTRL_0_BURST_SIZE_BURST_1WORDS _MK_ENUM_CONST(2) +#define NAND_DMA_MST_CTRL_0_BURST_SIZE_BURST_4WORDS _MK_ENUM_CONST(3) +#define NAND_DMA_MST_CTRL_0_BURST_SIZE_BURST_8WORDS _MK_ENUM_CONST(4) +#define NAND_DMA_MST_CTRL_0_BURST_SIZE_BURST_16WORDS _MK_ENUM_CONST(5) +#define NAND_DMA_MST_CTRL_0_BURST_SIZE_BURST_RSVD3 _MK_ENUM_CONST(6) +#define NAND_DMA_MST_CTRL_0_BURST_SIZE_BURST_RSVD4 _MK_ENUM_CONST(7) + +// 1 = DMA transfer completed interrupt. +// This is set ONLY when not running in COMMAND QUEUE MODE +#define NAND_DMA_MST_CTRL_0_IS_DMA_DONE_SHIFT _MK_SHIFT_CONST(20) +#define NAND_DMA_MST_CTRL_0_IS_DMA_DONE_FIELD (_MK_MASK_CONST(0x1) << NAND_DMA_MST_CTRL_0_IS_DMA_DONE_SHIFT) +#define NAND_DMA_MST_CTRL_0_IS_DMA_DONE_RANGE 20:20 +#define NAND_DMA_MST_CTRL_0_IS_DMA_DONE_WOFFSET 0x0 +#define NAND_DMA_MST_CTRL_0_IS_DMA_DONE_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_DMA_MST_CTRL_0_IS_DMA_DONE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_DMA_MST_CTRL_0_IS_DMA_DONE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_DMA_MST_CTRL_0_IS_DMA_DONE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// Enable DMA transfer for Data (A) +#define NAND_DMA_MST_CTRL_0_DMA_EN_A_SHIFT _MK_SHIFT_CONST(2) +#define NAND_DMA_MST_CTRL_0_DMA_EN_A_FIELD (_MK_MASK_CONST(0x1) << NAND_DMA_MST_CTRL_0_DMA_EN_A_SHIFT) +#define NAND_DMA_MST_CTRL_0_DMA_EN_A_RANGE 2:2 +#define NAND_DMA_MST_CTRL_0_DMA_EN_A_WOFFSET 0x0 +#define NAND_DMA_MST_CTRL_0_DMA_EN_A_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_DMA_MST_CTRL_0_DMA_EN_A_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_DMA_MST_CTRL_0_DMA_EN_A_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_DMA_MST_CTRL_0_DMA_EN_A_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_DMA_MST_CTRL_0_DMA_EN_A_DISABLE _MK_ENUM_CONST(0) +#define NAND_DMA_MST_CTRL_0_DMA_EN_A_ENABLE _MK_ENUM_CONST(1) + +// Enable DMA transfer for TAG/Spare (B) +#define NAND_DMA_MST_CTRL_0_DMA_EN_B_SHIFT _MK_SHIFT_CONST(1) +#define NAND_DMA_MST_CTRL_0_DMA_EN_B_FIELD (_MK_MASK_CONST(0x1) << NAND_DMA_MST_CTRL_0_DMA_EN_B_SHIFT) +#define NAND_DMA_MST_CTRL_0_DMA_EN_B_RANGE 1:1 +#define NAND_DMA_MST_CTRL_0_DMA_EN_B_WOFFSET 0x0 +#define NAND_DMA_MST_CTRL_0_DMA_EN_B_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_DMA_MST_CTRL_0_DMA_EN_B_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_DMA_MST_CTRL_0_DMA_EN_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_DMA_MST_CTRL_0_DMA_EN_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_DMA_MST_CTRL_0_DMA_EN_B_DISABLE _MK_ENUM_CONST(0) +#define NAND_DMA_MST_CTRL_0_DMA_EN_B_ENABLE _MK_ENUM_CONST(1) + + +// Register NAND_DMA_CFG_A_0 +#define NAND_DMA_CFG_A_0 _MK_ADDR_CONST(0x34) +#define NAND_DMA_CFG_A_0_SECURE 0x0 +#define NAND_DMA_CFG_A_0_WORD_COUNT 0x1 +#define NAND_DMA_CFG_A_0_RESET_VAL _MK_MASK_CONST(0x0) +#define NAND_DMA_CFG_A_0_RESET_MASK _MK_MASK_CONST(0xffff) +#define NAND_DMA_CFG_A_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define NAND_DMA_CFG_A_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_DMA_CFG_A_0_READ_MASK _MK_MASK_CONST(0xffff) +#define NAND_DMA_CFG_A_0_WRITE_MASK _MK_MASK_CONST(0xffff) +// DMA Data Block size in Bytes(N-1) value +#define NAND_DMA_CFG_A_0_DMA_BLOCK_SIZE_A_SHIFT _MK_SHIFT_CONST(0) +#define NAND_DMA_CFG_A_0_DMA_BLOCK_SIZE_A_FIELD (_MK_MASK_CONST(0xffff) << NAND_DMA_CFG_A_0_DMA_BLOCK_SIZE_A_SHIFT) +#define NAND_DMA_CFG_A_0_DMA_BLOCK_SIZE_A_RANGE 15:0 +#define NAND_DMA_CFG_A_0_DMA_BLOCK_SIZE_A_WOFFSET 0x0 +#define NAND_DMA_CFG_A_0_DMA_BLOCK_SIZE_A_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_DMA_CFG_A_0_DMA_BLOCK_SIZE_A_DEFAULT_MASK _MK_MASK_CONST(0xffff) +#define NAND_DMA_CFG_A_0_DMA_BLOCK_SIZE_A_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_DMA_CFG_A_0_DMA_BLOCK_SIZE_A_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register NAND_DMA_CFG_B_0 +#define NAND_DMA_CFG_B_0 _MK_ADDR_CONST(0x38) +#define NAND_DMA_CFG_B_0_SECURE 0x0 +#define NAND_DMA_CFG_B_0_WORD_COUNT 0x1 +#define NAND_DMA_CFG_B_0_RESET_VAL _MK_MASK_CONST(0x0) +#define NAND_DMA_CFG_B_0_RESET_MASK _MK_MASK_CONST(0xffff) +#define NAND_DMA_CFG_B_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define NAND_DMA_CFG_B_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_DMA_CFG_B_0_READ_MASK _MK_MASK_CONST(0xffff) +#define NAND_DMA_CFG_B_0_WRITE_MASK _MK_MASK_CONST(0xffff) +// DMA TAG Block size in Bytes(N-1) value +#define NAND_DMA_CFG_B_0_DMA_BLOCK_SIZE_B_SHIFT _MK_SHIFT_CONST(0) +#define NAND_DMA_CFG_B_0_DMA_BLOCK_SIZE_B_FIELD (_MK_MASK_CONST(0xffff) << NAND_DMA_CFG_B_0_DMA_BLOCK_SIZE_B_SHIFT) +#define NAND_DMA_CFG_B_0_DMA_BLOCK_SIZE_B_RANGE 15:0 +#define NAND_DMA_CFG_B_0_DMA_BLOCK_SIZE_B_WOFFSET 0x0 +#define NAND_DMA_CFG_B_0_DMA_BLOCK_SIZE_B_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_DMA_CFG_B_0_DMA_BLOCK_SIZE_B_DEFAULT_MASK _MK_MASK_CONST(0xffff) +#define NAND_DMA_CFG_B_0_DMA_BLOCK_SIZE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_DMA_CFG_B_0_DMA_BLOCK_SIZE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register NAND_FIFO_CTRL_0 +#define NAND_FIFO_CTRL_0 _MK_ADDR_CONST(0x3c) +#define NAND_FIFO_CTRL_0_SECURE 0x0 +#define NAND_FIFO_CTRL_0_WORD_COUNT 0x1 +#define NAND_FIFO_CTRL_0_RESET_VAL _MK_MASK_CONST(0xaa00) +#define NAND_FIFO_CTRL_0_RESET_MASK _MK_MASK_CONST(0xff0f) +#define NAND_FIFO_CTRL_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define NAND_FIFO_CTRL_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_FIFO_CTRL_0_READ_MASK _MK_MASK_CONST(0xff0f) +#define NAND_FIFO_CTRL_0_WRITE_MASK _MK_MASK_CONST(0xf) +// 1 = Indicates Command queue FIFO Empty +#define NAND_FIFO_CTRL_0_LL_BUF_EMPTY_SHIFT _MK_SHIFT_CONST(15) +#define NAND_FIFO_CTRL_0_LL_BUF_EMPTY_FIELD (_MK_MASK_CONST(0x1) << NAND_FIFO_CTRL_0_LL_BUF_EMPTY_SHIFT) +#define NAND_FIFO_CTRL_0_LL_BUF_EMPTY_RANGE 15:15 +#define NAND_FIFO_CTRL_0_LL_BUF_EMPTY_WOFFSET 0x0 +#define NAND_FIFO_CTRL_0_LL_BUF_EMPTY_DEFAULT _MK_MASK_CONST(0x1) +#define NAND_FIFO_CTRL_0_LL_BUF_EMPTY_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_FIFO_CTRL_0_LL_BUF_EMPTY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_FIFO_CTRL_0_LL_BUF_EMPTY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// 1 = Indicates Command queue FIFO Full +#define NAND_FIFO_CTRL_0_LL_BUF_FULL_SHIFT _MK_SHIFT_CONST(14) +#define NAND_FIFO_CTRL_0_LL_BUF_FULL_FIELD (_MK_MASK_CONST(0x1) << NAND_FIFO_CTRL_0_LL_BUF_FULL_SHIFT) +#define NAND_FIFO_CTRL_0_LL_BUF_FULL_RANGE 14:14 +#define NAND_FIFO_CTRL_0_LL_BUF_FULL_WOFFSET 0x0 +#define NAND_FIFO_CTRL_0_LL_BUF_FULL_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_FIFO_CTRL_0_LL_BUF_FULL_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_FIFO_CTRL_0_LL_BUF_FULL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_FIFO_CTRL_0_LL_BUF_FULL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// 1 = Indicates Data FIFO Empty +#define NAND_FIFO_CTRL_0_FIFO_A_EMPTY_SHIFT _MK_SHIFT_CONST(13) +#define NAND_FIFO_CTRL_0_FIFO_A_EMPTY_FIELD (_MK_MASK_CONST(0x1) << NAND_FIFO_CTRL_0_FIFO_A_EMPTY_SHIFT) +#define NAND_FIFO_CTRL_0_FIFO_A_EMPTY_RANGE 13:13 +#define NAND_FIFO_CTRL_0_FIFO_A_EMPTY_WOFFSET 0x0 +#define NAND_FIFO_CTRL_0_FIFO_A_EMPTY_DEFAULT _MK_MASK_CONST(0x1) +#define NAND_FIFO_CTRL_0_FIFO_A_EMPTY_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_FIFO_CTRL_0_FIFO_A_EMPTY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_FIFO_CTRL_0_FIFO_A_EMPTY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// 1 = Indicates Data FIFO Full +#define NAND_FIFO_CTRL_0_FIFO_A_FULL_SHIFT _MK_SHIFT_CONST(12) +#define NAND_FIFO_CTRL_0_FIFO_A_FULL_FIELD (_MK_MASK_CONST(0x1) << NAND_FIFO_CTRL_0_FIFO_A_FULL_SHIFT) +#define NAND_FIFO_CTRL_0_FIFO_A_FULL_RANGE 12:12 +#define NAND_FIFO_CTRL_0_FIFO_A_FULL_WOFFSET 0x0 +#define NAND_FIFO_CTRL_0_FIFO_A_FULL_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_FIFO_CTRL_0_FIFO_A_FULL_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_FIFO_CTRL_0_FIFO_A_FULL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_FIFO_CTRL_0_FIFO_A_FULL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// 1 = Indicates TAG FIFO Empty +#define NAND_FIFO_CTRL_0_FIFO_B_EMPTY_SHIFT _MK_SHIFT_CONST(11) +#define NAND_FIFO_CTRL_0_FIFO_B_EMPTY_FIELD (_MK_MASK_CONST(0x1) << NAND_FIFO_CTRL_0_FIFO_B_EMPTY_SHIFT) +#define NAND_FIFO_CTRL_0_FIFO_B_EMPTY_RANGE 11:11 +#define NAND_FIFO_CTRL_0_FIFO_B_EMPTY_WOFFSET 0x0 +#define NAND_FIFO_CTRL_0_FIFO_B_EMPTY_DEFAULT _MK_MASK_CONST(0x1) +#define NAND_FIFO_CTRL_0_FIFO_B_EMPTY_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_FIFO_CTRL_0_FIFO_B_EMPTY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_FIFO_CTRL_0_FIFO_B_EMPTY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// 1 = Indicates TAG FIFO Full +#define NAND_FIFO_CTRL_0_FIFO_B_FULL_SHIFT _MK_SHIFT_CONST(10) +#define NAND_FIFO_CTRL_0_FIFO_B_FULL_FIELD (_MK_MASK_CONST(0x1) << NAND_FIFO_CTRL_0_FIFO_B_FULL_SHIFT) +#define NAND_FIFO_CTRL_0_FIFO_B_FULL_RANGE 10:10 +#define NAND_FIFO_CTRL_0_FIFO_B_FULL_WOFFSET 0x0 +#define NAND_FIFO_CTRL_0_FIFO_B_FULL_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_FIFO_CTRL_0_FIFO_B_FULL_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_FIFO_CTRL_0_FIFO_B_FULL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_FIFO_CTRL_0_FIFO_B_FULL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// 1 = Indicates ECC FIFO Empty +#define NAND_FIFO_CTRL_0_FIFO_C_EMPTY_SHIFT _MK_SHIFT_CONST(9) +#define NAND_FIFO_CTRL_0_FIFO_C_EMPTY_FIELD (_MK_MASK_CONST(0x1) << NAND_FIFO_CTRL_0_FIFO_C_EMPTY_SHIFT) +#define NAND_FIFO_CTRL_0_FIFO_C_EMPTY_RANGE 9:9 +#define NAND_FIFO_CTRL_0_FIFO_C_EMPTY_WOFFSET 0x0 +#define NAND_FIFO_CTRL_0_FIFO_C_EMPTY_DEFAULT _MK_MASK_CONST(0x1) +#define NAND_FIFO_CTRL_0_FIFO_C_EMPTY_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_FIFO_CTRL_0_FIFO_C_EMPTY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_FIFO_CTRL_0_FIFO_C_EMPTY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// 1 = Indicates ECC FIFO Full +#define NAND_FIFO_CTRL_0_FIFO_C_FULL_SHIFT _MK_SHIFT_CONST(8) +#define NAND_FIFO_CTRL_0_FIFO_C_FULL_FIELD (_MK_MASK_CONST(0x1) << NAND_FIFO_CTRL_0_FIFO_C_FULL_SHIFT) +#define NAND_FIFO_CTRL_0_FIFO_C_FULL_RANGE 8:8 +#define NAND_FIFO_CTRL_0_FIFO_C_FULL_WOFFSET 0x0 +#define NAND_FIFO_CTRL_0_FIFO_C_FULL_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_FIFO_CTRL_0_FIFO_C_FULL_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_FIFO_CTRL_0_FIFO_C_FULL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_FIFO_CTRL_0_FIFO_C_FULL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// field set to "CLEAR_ALL_FIFO" flushs all the buffers(i.e.,LL_BUF,FIFO_A,FIFO_B,FIFO_C) +#define NAND_FIFO_CTRL_0_LL_BUF_CLR_SHIFT _MK_SHIFT_CONST(3) +#define NAND_FIFO_CTRL_0_LL_BUF_CLR_FIELD (_MK_MASK_CONST(0x1) << NAND_FIFO_CTRL_0_LL_BUF_CLR_SHIFT) +#define NAND_FIFO_CTRL_0_LL_BUF_CLR_RANGE 3:3 +#define NAND_FIFO_CTRL_0_LL_BUF_CLR_WOFFSET 0x0 +#define NAND_FIFO_CTRL_0_LL_BUF_CLR_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_FIFO_CTRL_0_LL_BUF_CLR_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_FIFO_CTRL_0_LL_BUF_CLR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_FIFO_CTRL_0_LL_BUF_CLR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_FIFO_CTRL_0_LL_BUF_CLR_CLEAR_NO_FIFO _MK_ENUM_CONST(0) +#define NAND_FIFO_CTRL_0_LL_BUF_CLR_CLEAR_ALL_FIFO _MK_ENUM_CONST(1) + +// Flush the DATA FIFO contents +#define NAND_FIFO_CTRL_0_FIFO_A_CLR_SHIFT _MK_SHIFT_CONST(2) +#define NAND_FIFO_CTRL_0_FIFO_A_CLR_FIELD (_MK_MASK_CONST(0x1) << NAND_FIFO_CTRL_0_FIFO_A_CLR_SHIFT) +#define NAND_FIFO_CTRL_0_FIFO_A_CLR_RANGE 2:2 +#define NAND_FIFO_CTRL_0_FIFO_A_CLR_WOFFSET 0x0 +#define NAND_FIFO_CTRL_0_FIFO_A_CLR_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_FIFO_CTRL_0_FIFO_A_CLR_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_FIFO_CTRL_0_FIFO_A_CLR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_FIFO_CTRL_0_FIFO_A_CLR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// Flush the TAG FIFO contents +#define NAND_FIFO_CTRL_0_FIFO_B_CLR_SHIFT _MK_SHIFT_CONST(1) +#define NAND_FIFO_CTRL_0_FIFO_B_CLR_FIELD (_MK_MASK_CONST(0x1) << NAND_FIFO_CTRL_0_FIFO_B_CLR_SHIFT) +#define NAND_FIFO_CTRL_0_FIFO_B_CLR_RANGE 1:1 +#define NAND_FIFO_CTRL_0_FIFO_B_CLR_WOFFSET 0x0 +#define NAND_FIFO_CTRL_0_FIFO_B_CLR_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_FIFO_CTRL_0_FIFO_B_CLR_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_FIFO_CTRL_0_FIFO_B_CLR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_FIFO_CTRL_0_FIFO_B_CLR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// Flush the ECC FIFO contents +#define NAND_FIFO_CTRL_0_FIFO_C_CLR_SHIFT _MK_SHIFT_CONST(0) +#define NAND_FIFO_CTRL_0_FIFO_C_CLR_FIELD (_MK_MASK_CONST(0x1) << NAND_FIFO_CTRL_0_FIFO_C_CLR_SHIFT) +#define NAND_FIFO_CTRL_0_FIFO_C_CLR_RANGE 0:0 +#define NAND_FIFO_CTRL_0_FIFO_C_CLR_WOFFSET 0x0 +#define NAND_FIFO_CTRL_0_FIFO_C_CLR_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_FIFO_CTRL_0_FIFO_C_CLR_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_FIFO_CTRL_0_FIFO_C_CLR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_FIFO_CTRL_0_FIFO_C_CLR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register NAND_DATA_BLOCK_PTR_0 +#define NAND_DATA_BLOCK_PTR_0 _MK_ADDR_CONST(0x40) +#define NAND_DATA_BLOCK_PTR_0_SECURE 0x0 +#define NAND_DATA_BLOCK_PTR_0_WORD_COUNT 0x1 +#define NAND_DATA_BLOCK_PTR_0_RESET_VAL _MK_MASK_CONST(0x0) +#define NAND_DATA_BLOCK_PTR_0_RESET_MASK _MK_MASK_CONST(0xfffffffc) +#define NAND_DATA_BLOCK_PTR_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define NAND_DATA_BLOCK_PTR_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_DATA_BLOCK_PTR_0_READ_MASK _MK_MASK_CONST(0xfffffffc) +#define NAND_DATA_BLOCK_PTR_0_WRITE_MASK _MK_MASK_CONST(0xfffffffc) +// DMA data block source/destination address pointer +#define NAND_DATA_BLOCK_PTR_0_DMA_DATA_BLOCK_PTR_SHIFT _MK_SHIFT_CONST(2) +#define NAND_DATA_BLOCK_PTR_0_DMA_DATA_BLOCK_PTR_FIELD (_MK_MASK_CONST(0x3fffffff) << NAND_DATA_BLOCK_PTR_0_DMA_DATA_BLOCK_PTR_SHIFT) +#define NAND_DATA_BLOCK_PTR_0_DMA_DATA_BLOCK_PTR_RANGE 31:2 +#define NAND_DATA_BLOCK_PTR_0_DMA_DATA_BLOCK_PTR_WOFFSET 0x0 +#define NAND_DATA_BLOCK_PTR_0_DMA_DATA_BLOCK_PTR_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_DATA_BLOCK_PTR_0_DMA_DATA_BLOCK_PTR_DEFAULT_MASK _MK_MASK_CONST(0x3fffffff) +#define NAND_DATA_BLOCK_PTR_0_DMA_DATA_BLOCK_PTR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_DATA_BLOCK_PTR_0_DMA_DATA_BLOCK_PTR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register NAND_TAG_PTR_0 +#define NAND_TAG_PTR_0 _MK_ADDR_CONST(0x44) +#define NAND_TAG_PTR_0_SECURE 0x0 +#define NAND_TAG_PTR_0_WORD_COUNT 0x1 +#define NAND_TAG_PTR_0_RESET_VAL _MK_MASK_CONST(0x0) +#define NAND_TAG_PTR_0_RESET_MASK _MK_MASK_CONST(0xfffffffc) +#define NAND_TAG_PTR_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define NAND_TAG_PTR_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_TAG_PTR_0_READ_MASK _MK_MASK_CONST(0xfffffffc) +#define NAND_TAG_PTR_0_WRITE_MASK _MK_MASK_CONST(0xfffffffc) +// DMA TAG block source/destination address pointer +#define NAND_TAG_PTR_0_DMA_TAG_PTR_SHIFT _MK_SHIFT_CONST(2) +#define NAND_TAG_PTR_0_DMA_TAG_PTR_FIELD (_MK_MASK_CONST(0x3fffffff) << NAND_TAG_PTR_0_DMA_TAG_PTR_SHIFT) +#define NAND_TAG_PTR_0_DMA_TAG_PTR_RANGE 31:2 +#define NAND_TAG_PTR_0_DMA_TAG_PTR_WOFFSET 0x0 +#define NAND_TAG_PTR_0_DMA_TAG_PTR_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_TAG_PTR_0_DMA_TAG_PTR_DEFAULT_MASK _MK_MASK_CONST(0x3fffffff) +#define NAND_TAG_PTR_0_DMA_TAG_PTR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_TAG_PTR_0_DMA_TAG_PTR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register NAND_ECC_PTR_0 +#define NAND_ECC_PTR_0 _MK_ADDR_CONST(0x48) +#define NAND_ECC_PTR_0_SECURE 0x0 +#define NAND_ECC_PTR_0_WORD_COUNT 0x1 +#define NAND_ECC_PTR_0_RESET_VAL _MK_MASK_CONST(0x0) +#define NAND_ECC_PTR_0_RESET_MASK _MK_MASK_CONST(0xfffffffc) +#define NAND_ECC_PTR_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define NAND_ECC_PTR_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_ECC_PTR_0_READ_MASK _MK_MASK_CONST(0xfffffffc) +#define NAND_ECC_PTR_0_WRITE_MASK _MK_MASK_CONST(0xfffffffc) +// DMA Error vector destination address pointer +#define NAND_ECC_PTR_0_DMA_ECC_PTR_SHIFT _MK_SHIFT_CONST(2) +#define NAND_ECC_PTR_0_DMA_ECC_PTR_FIELD (_MK_MASK_CONST(0x3fffffff) << NAND_ECC_PTR_0_DMA_ECC_PTR_SHIFT) +#define NAND_ECC_PTR_0_DMA_ECC_PTR_RANGE 31:2 +#define NAND_ECC_PTR_0_DMA_ECC_PTR_WOFFSET 0x0 +#define NAND_ECC_PTR_0_DMA_ECC_PTR_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_ECC_PTR_0_DMA_ECC_PTR_DEFAULT_MASK _MK_MASK_CONST(0x3fffffff) +#define NAND_ECC_PTR_0_DMA_ECC_PTR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_ECC_PTR_0_DMA_ECC_PTR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register NAND_DEC_STATUS_0 +#define NAND_DEC_STATUS_0 _MK_ADDR_CONST(0x4c) +#define NAND_DEC_STATUS_0_SECURE 0x0 +#define NAND_DEC_STATUS_0_WORD_COUNT 0x1 +#define NAND_DEC_STATUS_0_RESET_VAL _MK_MASK_CONST(0x0) +#define NAND_DEC_STATUS_0_RESET_MASK _MK_MASK_CONST(0xffffff03) +#define NAND_DEC_STATUS_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define NAND_DEC_STATUS_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_DEC_STATUS_0_READ_MASK _MK_MASK_CONST(0xffffff03) +#define NAND_DEC_STATUS_0_WRITE_MASK _MK_MASK_CONST(0x0) +// Indicates the reference to the PAGE for Error Correction +// to be applied. Valid when IS_ECC_ERROR is generated +#define NAND_DEC_STATUS_0_ERR_PAGE_NUMBER_SHIFT _MK_SHIFT_CONST(24) +#define NAND_DEC_STATUS_0_ERR_PAGE_NUMBER_FIELD (_MK_MASK_CONST(0xff) << NAND_DEC_STATUS_0_ERR_PAGE_NUMBER_SHIFT) +#define NAND_DEC_STATUS_0_ERR_PAGE_NUMBER_RANGE 31:24 +#define NAND_DEC_STATUS_0_ERR_PAGE_NUMBER_WOFFSET 0x0 +#define NAND_DEC_STATUS_0_ERR_PAGE_NUMBER_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_DEC_STATUS_0_ERR_PAGE_NUMBER_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define NAND_DEC_STATUS_0_ERR_PAGE_NUMBER_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_DEC_STATUS_0_ERR_PAGE_NUMBER_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// No. of Errors occurred in main block READ data plus TAG read +// data when corresponding features are enabled. +#define NAND_DEC_STATUS_0_ERR_COUNT_SHIFT _MK_SHIFT_CONST(16) +#define NAND_DEC_STATUS_0_ERR_COUNT_FIELD (_MK_MASK_CONST(0xff) << NAND_DEC_STATUS_0_ERR_COUNT_SHIFT) +#define NAND_DEC_STATUS_0_ERR_COUNT_RANGE 23:16 +#define NAND_DEC_STATUS_0_ERR_COUNT_WOFFSET 0x0 +#define NAND_DEC_STATUS_0_ERR_COUNT_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_DEC_STATUS_0_ERR_COUNT_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define NAND_DEC_STATUS_0_ERR_COUNT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_DEC_STATUS_0_ERR_COUNT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// Indicates sub-page decode failure within a page size. +// When decode failure is observed SW can use to figure +// out which sub-page (512 byte) decode failure. +// for ex: of 2K page size selection, +// bit 0 - first sub-page +// bit 1 - second sub-page +// bit 2 - third sub-page +// bit 3 - fourth sub-page +// and so on as applicable +#define NAND_DEC_STATUS_0_SUB_PAGE_FAIL_SHIFT _MK_SHIFT_CONST(8) +#define NAND_DEC_STATUS_0_SUB_PAGE_FAIL_FIELD (_MK_MASK_CONST(0xff) << NAND_DEC_STATUS_0_SUB_PAGE_FAIL_SHIFT) +#define NAND_DEC_STATUS_0_SUB_PAGE_FAIL_RANGE 15:8 +#define NAND_DEC_STATUS_0_SUB_PAGE_FAIL_WOFFSET 0x0 +#define NAND_DEC_STATUS_0_SUB_PAGE_FAIL_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_DEC_STATUS_0_SUB_PAGE_FAIL_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define NAND_DEC_STATUS_0_SUB_PAGE_FAIL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_DEC_STATUS_0_SUB_PAGE_FAIL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// 0 = Main block data decode without decode fail +#define NAND_DEC_STATUS_0_A_ECC_FAIL_SHIFT _MK_SHIFT_CONST(1) +#define NAND_DEC_STATUS_0_A_ECC_FAIL_FIELD (_MK_MASK_CONST(0x1) << NAND_DEC_STATUS_0_A_ECC_FAIL_SHIFT) +#define NAND_DEC_STATUS_0_A_ECC_FAIL_RANGE 1:1 +#define NAND_DEC_STATUS_0_A_ECC_FAIL_WOFFSET 0x0 +#define NAND_DEC_STATUS_0_A_ECC_FAIL_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_DEC_STATUS_0_A_ECC_FAIL_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_DEC_STATUS_0_A_ECC_FAIL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_DEC_STATUS_0_A_ECC_FAIL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// 0 = Tag block data decode without decode fail +#define NAND_DEC_STATUS_0_B_ECC_FAIL_SHIFT _MK_SHIFT_CONST(0) +#define NAND_DEC_STATUS_0_B_ECC_FAIL_FIELD (_MK_MASK_CONST(0x1) << NAND_DEC_STATUS_0_B_ECC_FAIL_SHIFT) +#define NAND_DEC_STATUS_0_B_ECC_FAIL_RANGE 0:0 +#define NAND_DEC_STATUS_0_B_ECC_FAIL_WOFFSET 0x0 +#define NAND_DEC_STATUS_0_B_ECC_FAIL_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_DEC_STATUS_0_B_ECC_FAIL_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_DEC_STATUS_0_B_ECC_FAIL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_DEC_STATUS_0_B_ECC_FAIL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register NAND_HWSTATUS_CMD_0 +#define NAND_HWSTATUS_CMD_0 _MK_ADDR_CONST(0x50) +#define NAND_HWSTATUS_CMD_0_SECURE 0x0 +#define NAND_HWSTATUS_CMD_0_WORD_COUNT 0x1 +#define NAND_HWSTATUS_CMD_0_RESET_VAL _MK_MASK_CONST(0x0) +#define NAND_HWSTATUS_CMD_0_RESET_MASK _MK_MASK_CONST(0xff) +#define NAND_HWSTATUS_CMD_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define NAND_HWSTATUS_CMD_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_HWSTATUS_CMD_0_READ_MASK _MK_MASK_CONST(0xff) +#define NAND_HWSTATUS_CMD_0_WRITE_MASK _MK_MASK_CONST(0xff) +// Command byte value used for READ STATUS commands when +// automatic HW RBSY_CHK or RD_STATUS_CHK are enabled. +#define NAND_HWSTATUS_CMD_0_HWSTATUS_CMD_SHIFT _MK_SHIFT_CONST(0) +#define NAND_HWSTATUS_CMD_0_HWSTATUS_CMD_FIELD (_MK_MASK_CONST(0xff) << NAND_HWSTATUS_CMD_0_HWSTATUS_CMD_SHIFT) +#define NAND_HWSTATUS_CMD_0_HWSTATUS_CMD_RANGE 7:0 +#define NAND_HWSTATUS_CMD_0_HWSTATUS_CMD_WOFFSET 0x0 +#define NAND_HWSTATUS_CMD_0_HWSTATUS_CMD_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_HWSTATUS_CMD_0_HWSTATUS_CMD_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define NAND_HWSTATUS_CMD_0_HWSTATUS_CMD_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_HWSTATUS_CMD_0_HWSTATUS_CMD_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register NAND_HWSTATUS_MASK_0 +#define NAND_HWSTATUS_MASK_0 _MK_ADDR_CONST(0x54) +#define NAND_HWSTATUS_MASK_0_SECURE 0x0 +#define NAND_HWSTATUS_MASK_0_WORD_COUNT 0x1 +#define NAND_HWSTATUS_MASK_0_RESET_VAL _MK_MASK_CONST(0xffe04040) +#define NAND_HWSTATUS_MASK_0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define NAND_HWSTATUS_MASK_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define NAND_HWSTATUS_MASK_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_HWSTATUS_MASK_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define NAND_HWSTATUS_MASK_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +// 8 bit Mask value to extract the correct bit fields +// from READ STATUS information for RD_STATUS_CHK +#define NAND_HWSTATUS_MASK_0_RDSTATUS_MASK_SHIFT _MK_SHIFT_CONST(24) +#define NAND_HWSTATUS_MASK_0_RDSTATUS_MASK_FIELD (_MK_MASK_CONST(0xff) << NAND_HWSTATUS_MASK_0_RDSTATUS_MASK_SHIFT) +#define NAND_HWSTATUS_MASK_0_RDSTATUS_MASK_RANGE 31:24 +#define NAND_HWSTATUS_MASK_0_RDSTATUS_MASK_WOFFSET 0x0 +#define NAND_HWSTATUS_MASK_0_RDSTATUS_MASK_DEFAULT _MK_MASK_CONST(0xff) +#define NAND_HWSTATUS_MASK_0_RDSTATUS_MASK_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define NAND_HWSTATUS_MASK_0_RDSTATUS_MASK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_HWSTATUS_MASK_0_RDSTATUS_MASK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// 8 bit expected RD STATUS VALUE for RD_STATUS_CHK +#define NAND_HWSTATUS_MASK_0_RDSTATUS_EXP_VAL_SHIFT _MK_SHIFT_CONST(16) +#define NAND_HWSTATUS_MASK_0_RDSTATUS_EXP_VAL_FIELD (_MK_MASK_CONST(0xff) << NAND_HWSTATUS_MASK_0_RDSTATUS_EXP_VAL_SHIFT) +#define NAND_HWSTATUS_MASK_0_RDSTATUS_EXP_VAL_RANGE 23:16 +#define NAND_HWSTATUS_MASK_0_RDSTATUS_EXP_VAL_WOFFSET 0x0 +#define NAND_HWSTATUS_MASK_0_RDSTATUS_EXP_VAL_DEFAULT _MK_MASK_CONST(0xe0) +#define NAND_HWSTATUS_MASK_0_RDSTATUS_EXP_VAL_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define NAND_HWSTATUS_MASK_0_RDSTATUS_EXP_VAL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_HWSTATUS_MASK_0_RDSTATUS_EXP_VAL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// 8 bit Mask value to extract the correct bit fields +// from READ STATUS information for RBSY_CHK +#define NAND_HWSTATUS_MASK_0_RBSY_MASK_SHIFT _MK_SHIFT_CONST(8) +#define NAND_HWSTATUS_MASK_0_RBSY_MASK_FIELD (_MK_MASK_CONST(0xff) << NAND_HWSTATUS_MASK_0_RBSY_MASK_SHIFT) +#define NAND_HWSTATUS_MASK_0_RBSY_MASK_RANGE 15:8 +#define NAND_HWSTATUS_MASK_0_RBSY_MASK_WOFFSET 0x0 +#define NAND_HWSTATUS_MASK_0_RBSY_MASK_DEFAULT _MK_MASK_CONST(0x40) +#define NAND_HWSTATUS_MASK_0_RBSY_MASK_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define NAND_HWSTATUS_MASK_0_RBSY_MASK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_HWSTATUS_MASK_0_RBSY_MASK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// 8 bit expected RD STATUS VALUE for RBSY_CHK +#define NAND_HWSTATUS_MASK_0_RBSY_EXP_VAL_SHIFT _MK_SHIFT_CONST(0) +#define NAND_HWSTATUS_MASK_0_RBSY_EXP_VAL_FIELD (_MK_MASK_CONST(0xff) << NAND_HWSTATUS_MASK_0_RBSY_EXP_VAL_SHIFT) +#define NAND_HWSTATUS_MASK_0_RBSY_EXP_VAL_RANGE 7:0 +#define NAND_HWSTATUS_MASK_0_RBSY_EXP_VAL_WOFFSET 0x0 +#define NAND_HWSTATUS_MASK_0_RBSY_EXP_VAL_DEFAULT _MK_MASK_CONST(0x40) +#define NAND_HWSTATUS_MASK_0_RBSY_EXP_VAL_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define NAND_HWSTATUS_MASK_0_RBSY_EXP_VAL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_HWSTATUS_MASK_0_RBSY_EXP_VAL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register NAND_LL_CONFIG_0 +#define NAND_LL_CONFIG_0 _MK_ADDR_CONST(0x58) +#define NAND_LL_CONFIG_0_SECURE 0x0 +#define NAND_LL_CONFIG_0_WORD_COUNT 0x1 +#define NAND_LL_CONFIG_0_RESET_VAL _MK_MASK_CONST(0xc0000) +#define NAND_LL_CONFIG_0_RESET_MASK _MK_MASK_CONST(0x800f0fff) +#define NAND_LL_CONFIG_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define NAND_LL_CONFIG_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LL_CONFIG_0_READ_MASK _MK_MASK_CONST(0x800f0fff) +#define NAND_LL_CONFIG_0_WRITE_MASK _MK_MASK_CONST(0xf0fff) +// HW clears when command queue data and flash operations +// are completed. +#define NAND_LL_CONFIG_0_LL_START_SHIFT _MK_SHIFT_CONST(31) +#define NAND_LL_CONFIG_0_LL_START_FIELD (_MK_MASK_CONST(0x1) << NAND_LL_CONFIG_0_LL_START_SHIFT) +#define NAND_LL_CONFIG_0_LL_START_RANGE 31:31 +#define NAND_LL_CONFIG_0_LL_START_WOFFSET 0x0 +#define NAND_LL_CONFIG_0_LL_START_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LL_CONFIG_0_LL_START_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_LL_CONFIG_0_LL_START_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LL_CONFIG_0_LL_START_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LL_CONFIG_0_LL_START_DISABLE _MK_ENUM_CONST(0) +#define NAND_LL_CONFIG_0_LL_START_ENABLE _MK_ENUM_CONST(1) + +// Enable word count status update in LL_STATUS register +#define NAND_LL_CONFIG_0_WORD_CNT_STATUS_EN_SHIFT _MK_SHIFT_CONST(19) +#define NAND_LL_CONFIG_0_WORD_CNT_STATUS_EN_FIELD (_MK_MASK_CONST(0x1) << NAND_LL_CONFIG_0_WORD_CNT_STATUS_EN_SHIFT) +#define NAND_LL_CONFIG_0_WORD_CNT_STATUS_EN_RANGE 19:19 +#define NAND_LL_CONFIG_0_WORD_CNT_STATUS_EN_WOFFSET 0x0 +#define NAND_LL_CONFIG_0_WORD_CNT_STATUS_EN_DEFAULT _MK_MASK_CONST(0x1) +#define NAND_LL_CONFIG_0_WORD_CNT_STATUS_EN_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_LL_CONFIG_0_WORD_CNT_STATUS_EN_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LL_CONFIG_0_WORD_CNT_STATUS_EN_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LL_CONFIG_0_WORD_CNT_STATUS_EN_DISABLE _MK_ENUM_CONST(0) +#define NAND_LL_CONFIG_0_WORD_CNT_STATUS_EN_ENABLE _MK_ENUM_CONST(1) + +//DMA burst size for Command Queue data requests +#define NAND_LL_CONFIG_0_BURST_SIZE_SHIFT _MK_SHIFT_CONST(16) +#define NAND_LL_CONFIG_0_BURST_SIZE_FIELD (_MK_MASK_CONST(0x7) << NAND_LL_CONFIG_0_BURST_SIZE_SHIFT) +#define NAND_LL_CONFIG_0_BURST_SIZE_RANGE 18:16 +#define NAND_LL_CONFIG_0_BURST_SIZE_WOFFSET 0x0 +#define NAND_LL_CONFIG_0_BURST_SIZE_DEFAULT _MK_MASK_CONST(0x4) +#define NAND_LL_CONFIG_0_BURST_SIZE_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define NAND_LL_CONFIG_0_BURST_SIZE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LL_CONFIG_0_BURST_SIZE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LL_CONFIG_0_BURST_SIZE_BURST_RSVD1 _MK_ENUM_CONST(0) +#define NAND_LL_CONFIG_0_BURST_SIZE_BURST_RSVD2 _MK_ENUM_CONST(1) +#define NAND_LL_CONFIG_0_BURST_SIZE_BURST_1WORDS _MK_ENUM_CONST(2) +#define NAND_LL_CONFIG_0_BURST_SIZE_BURST_4WORDS _MK_ENUM_CONST(3) +#define NAND_LL_CONFIG_0_BURST_SIZE_BURST_8WORDS _MK_ENUM_CONST(4) +#define NAND_LL_CONFIG_0_BURST_SIZE_BURST_16WORDS _MK_ENUM_CONST(5) +#define NAND_LL_CONFIG_0_BURST_SIZE_BURST_RSVD3 _MK_ENUM_CONST(6) +#define NAND_LL_CONFIG_0_BURST_SIZE_BURST_RSVD4 _MK_ENUM_CONST(7) + +// Command queue up word length programmed is parsed and `START is +// done when the execution is complete. However for when errors are +// detected for any case of the flash operation failure command queue +// execution is aborted immediately before this length. +#define NAND_LL_CONFIG_0_LL_LENGTH_SHIFT _MK_SHIFT_CONST(0) +#define NAND_LL_CONFIG_0_LL_LENGTH_FIELD (_MK_MASK_CONST(0xfff) << NAND_LL_CONFIG_0_LL_LENGTH_SHIFT) +#define NAND_LL_CONFIG_0_LL_LENGTH_RANGE 11:0 +#define NAND_LL_CONFIG_0_LL_LENGTH_WOFFSET 0x0 +#define NAND_LL_CONFIG_0_LL_LENGTH_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LL_CONFIG_0_LL_LENGTH_DEFAULT_MASK _MK_MASK_CONST(0xfff) +#define NAND_LL_CONFIG_0_LL_LENGTH_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LL_CONFIG_0_LL_LENGTH_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register NAND_LL_PTR_0 +#define NAND_LL_PTR_0 _MK_ADDR_CONST(0x5c) +#define NAND_LL_PTR_0_SECURE 0x0 +#define NAND_LL_PTR_0_WORD_COUNT 0x1 +#define NAND_LL_PTR_0_RESET_VAL _MK_MASK_CONST(0x0) +#define NAND_LL_PTR_0_RESET_MASK _MK_MASK_CONST(0xfffffffc) +#define NAND_LL_PTR_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define NAND_LL_PTR_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LL_PTR_0_READ_MASK _MK_MASK_CONST(0xfffffffc) +#define NAND_LL_PTR_0_WRITE_MASK _MK_MASK_CONST(0xfffffffc) +// Command queue data pointer Register +#define NAND_LL_PTR_0_LL_PTR_SHIFT _MK_SHIFT_CONST(2) +#define NAND_LL_PTR_0_LL_PTR_FIELD (_MK_MASK_CONST(0x3fffffff) << NAND_LL_PTR_0_LL_PTR_SHIFT) +#define NAND_LL_PTR_0_LL_PTR_RANGE 31:2 +#define NAND_LL_PTR_0_LL_PTR_WOFFSET 0x0 +#define NAND_LL_PTR_0_LL_PTR_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LL_PTR_0_LL_PTR_DEFAULT_MASK _MK_MASK_CONST(0x3fffffff) +#define NAND_LL_PTR_0_LL_PTR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LL_PTR_0_LL_PTR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register NAND_LL_STATUS_0 +#define NAND_LL_STATUS_0 _MK_ADDR_CONST(0x60) +#define NAND_LL_STATUS_0_SECURE 0x0 +#define NAND_LL_STATUS_0_WORD_COUNT 0x1 +#define NAND_LL_STATUS_0_RESET_VAL _MK_MASK_CONST(0x0) +#define NAND_LL_STATUS_0_RESET_MASK _MK_MASK_CONST(0xffcf0fff) +#define NAND_LL_STATUS_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define NAND_LL_STATUS_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LL_STATUS_0_READ_MASK _MK_MASK_CONST(0xffcf0fff) +#define NAND_LL_STATUS_0_WRITE_MASK _MK_MASK_CONST(0xc00000) +// Command queue PACKET ID completed at this time. S/W has write +// access to this bit field position so that any time S/W can clear +// this field. Also NAND controller reset will reset this status. +#define NAND_LL_STATUS_0_LL_PKT_ID_SHIFT _MK_SHIFT_CONST(24) +#define NAND_LL_STATUS_0_LL_PKT_ID_FIELD (_MK_MASK_CONST(0xff) << NAND_LL_STATUS_0_LL_PKT_ID_SHIFT) +#define NAND_LL_STATUS_0_LL_PKT_ID_RANGE 31:24 +#define NAND_LL_STATUS_0_LL_PKT_ID_WOFFSET 0x0 +#define NAND_LL_STATUS_0_LL_PKT_ID_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LL_STATUS_0_LL_PKT_ID_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define NAND_LL_STATUS_0_LL_PKT_ID_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LL_STATUS_0_LL_PKT_ID_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// Interrupt status of LL_DONE { Read Only} +#define NAND_LL_STATUS_0_IS_LL_DONE_SHIFT _MK_SHIFT_CONST(23) +#define NAND_LL_STATUS_0_IS_LL_DONE_FIELD (_MK_MASK_CONST(0x1) << NAND_LL_STATUS_0_IS_LL_DONE_SHIFT) +#define NAND_LL_STATUS_0_IS_LL_DONE_RANGE 23:23 +#define NAND_LL_STATUS_0_IS_LL_DONE_WOFFSET 0x0 +#define NAND_LL_STATUS_0_IS_LL_DONE_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LL_STATUS_0_IS_LL_DONE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_LL_STATUS_0_IS_LL_DONE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LL_STATUS_0_IS_LL_DONE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// Interrupt status of LL_ERR { Read Only} +#define NAND_LL_STATUS_0_IS_LL_ERR_SHIFT _MK_SHIFT_CONST(22) +#define NAND_LL_STATUS_0_IS_LL_ERR_FIELD (_MK_MASK_CONST(0x1) << NAND_LL_STATUS_0_IS_LL_ERR_SHIFT) +#define NAND_LL_STATUS_0_IS_LL_ERR_RANGE 22:22 +#define NAND_LL_STATUS_0_IS_LL_ERR_WOFFSET 0x0 +#define NAND_LL_STATUS_0_IS_LL_ERR_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LL_STATUS_0_IS_LL_ERR_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_LL_STATUS_0_IS_LL_ERR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LL_STATUS_0_IS_LL_ERR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// Command queue Word length of last packet executed in the queue. +// Please note that WORD_CNT_STATUS_EN in LL_CONFIG should be enabled +// for this status update +#define NAND_LL_STATUS_0_LL_LENGTH_LAST_PKT_SHIFT _MK_SHIFT_CONST(16) +#define NAND_LL_STATUS_0_LL_LENGTH_LAST_PKT_FIELD (_MK_MASK_CONST(0xf) << NAND_LL_STATUS_0_LL_LENGTH_LAST_PKT_SHIFT) +#define NAND_LL_STATUS_0_LL_LENGTH_LAST_PKT_RANGE 19:16 +#define NAND_LL_STATUS_0_LL_LENGTH_LAST_PKT_WOFFSET 0x0 +#define NAND_LL_STATUS_0_LL_LENGTH_LAST_PKT_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LL_STATUS_0_LL_LENGTH_LAST_PKT_DEFAULT_MASK _MK_MASK_CONST(0xf) +#define NAND_LL_STATUS_0_LL_LENGTH_LAST_PKT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LL_STATUS_0_LL_LENGTH_LAST_PKT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// Command queue Word length(32-bit) completed till this time. +// Please note that WORD_CNT_STATUS_EN in LL_CONFIG should be enabled +// for this status update +#define NAND_LL_STATUS_0_LL_LENGTH_DONE_SHIFT _MK_SHIFT_CONST(0) +#define NAND_LL_STATUS_0_LL_LENGTH_DONE_FIELD (_MK_MASK_CONST(0xfff) << NAND_LL_STATUS_0_LL_LENGTH_DONE_SHIFT) +#define NAND_LL_STATUS_0_LL_LENGTH_DONE_RANGE 11:0 +#define NAND_LL_STATUS_0_LL_LENGTH_DONE_WOFFSET 0x0 +#define NAND_LL_STATUS_0_LL_LENGTH_DONE_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LL_STATUS_0_LL_LENGTH_DONE_DEFAULT_MASK _MK_MASK_CONST(0xfff) +#define NAND_LL_STATUS_0_LL_LENGTH_DONE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LL_STATUS_0_LL_LENGTH_DONE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register NAND_LOCK_CONTROL_0 +#define NAND_LOCK_CONTROL_0 _MK_ADDR_CONST(0x64) +#define NAND_LOCK_CONTROL_0_SECURE 0x0 +#define NAND_LOCK_CONTROL_0_WORD_COUNT 0x1 +#define NAND_LOCK_CONTROL_0_RESET_VAL _MK_MASK_CONST(0x0) +#define NAND_LOCK_CONTROL_0_RESET_MASK _MK_MASK_CONST(0x1ff) +#define NAND_LOCK_CONTROL_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define NAND_LOCK_CONTROL_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_CONTROL_0_READ_MASK _MK_MASK_CONST(0x1ff) +#define NAND_LOCK_CONTROL_0_WRITE_MASK _MK_MASK_CONST(0x1ff) +// Intterrupt enable on memory range match. +#define NAND_LOCK_CONTROL_0_IE_LOCK_ERR_SHIFT _MK_SHIFT_CONST(8) +#define NAND_LOCK_CONTROL_0_IE_LOCK_ERR_FIELD (_MK_MASK_CONST(0x1) << NAND_LOCK_CONTROL_0_IE_LOCK_ERR_SHIFT) +#define NAND_LOCK_CONTROL_0_IE_LOCK_ERR_RANGE 8:8 +#define NAND_LOCK_CONTROL_0_IE_LOCK_ERR_WOFFSET 0x0 +#define NAND_LOCK_CONTROL_0_IE_LOCK_ERR_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_CONTROL_0_IE_LOCK_ERR_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_LOCK_CONTROL_0_IE_LOCK_ERR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_CONTROL_0_IE_LOCK_ERR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_CONTROL_0_IE_LOCK_ERR_DISABLE _MK_ENUM_CONST(0) +#define NAND_LOCK_CONTROL_0_IE_LOCK_ERR_ENABLE _MK_ENUM_CONST(1) + +// Enable lock feature for selected apertures 7 Can be set only once register field, h/w reset OR controller reset ONLY +// can disable this feature. +// LOCK_APER_START7, LOCK_APER_END7, LOCK_APER_CHIPID7 cant be +// programmed once this SET +#define NAND_LOCK_CONTROL_0_LOCK_APER_EN7_SHIFT _MK_SHIFT_CONST(7) +#define NAND_LOCK_CONTROL_0_LOCK_APER_EN7_FIELD (_MK_MASK_CONST(0x1) << NAND_LOCK_CONTROL_0_LOCK_APER_EN7_SHIFT) +#define NAND_LOCK_CONTROL_0_LOCK_APER_EN7_RANGE 7:7 +#define NAND_LOCK_CONTROL_0_LOCK_APER_EN7_WOFFSET 0x0 +#define NAND_LOCK_CONTROL_0_LOCK_APER_EN7_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_CONTROL_0_LOCK_APER_EN7_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_LOCK_CONTROL_0_LOCK_APER_EN7_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_CONTROL_0_LOCK_APER_EN7_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_CONTROL_0_LOCK_APER_EN7_DISABLE _MK_ENUM_CONST(0) +#define NAND_LOCK_CONTROL_0_LOCK_APER_EN7_ENABLE _MK_ENUM_CONST(1) + +// Enable lock feature for selected apertures 6 Can be set only once register field, h/w reset OR controller reset ONLY +// can disable this feature. +// LOCK_APER_START6, LOCK_APER_END6, LOCK_APER_CHIPID6 cant be +// programmed once this SET +#define NAND_LOCK_CONTROL_0_LOCK_APER_EN6_SHIFT _MK_SHIFT_CONST(6) +#define NAND_LOCK_CONTROL_0_LOCK_APER_EN6_FIELD (_MK_MASK_CONST(0x1) << NAND_LOCK_CONTROL_0_LOCK_APER_EN6_SHIFT) +#define NAND_LOCK_CONTROL_0_LOCK_APER_EN6_RANGE 6:6 +#define NAND_LOCK_CONTROL_0_LOCK_APER_EN6_WOFFSET 0x0 +#define NAND_LOCK_CONTROL_0_LOCK_APER_EN6_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_CONTROL_0_LOCK_APER_EN6_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_LOCK_CONTROL_0_LOCK_APER_EN6_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_CONTROL_0_LOCK_APER_EN6_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_CONTROL_0_LOCK_APER_EN6_DISABLE _MK_ENUM_CONST(0) +#define NAND_LOCK_CONTROL_0_LOCK_APER_EN6_ENABLE _MK_ENUM_CONST(1) + +// Enable lock feature for selected apertures 5 Can be set only once register field, h/w reset OR controller reset ONLY +// can disable this feature. +// LOCK_APER_START5, LOCK_APER_END5, LOCK_APER_CHIPID5 cant be +// programmed once this SET +#define NAND_LOCK_CONTROL_0_LOCK_APER_EN5_SHIFT _MK_SHIFT_CONST(5) +#define NAND_LOCK_CONTROL_0_LOCK_APER_EN5_FIELD (_MK_MASK_CONST(0x1) << NAND_LOCK_CONTROL_0_LOCK_APER_EN5_SHIFT) +#define NAND_LOCK_CONTROL_0_LOCK_APER_EN5_RANGE 5:5 +#define NAND_LOCK_CONTROL_0_LOCK_APER_EN5_WOFFSET 0x0 +#define NAND_LOCK_CONTROL_0_LOCK_APER_EN5_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_CONTROL_0_LOCK_APER_EN5_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_LOCK_CONTROL_0_LOCK_APER_EN5_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_CONTROL_0_LOCK_APER_EN5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_CONTROL_0_LOCK_APER_EN5_DISABLE _MK_ENUM_CONST(0) +#define NAND_LOCK_CONTROL_0_LOCK_APER_EN5_ENABLE _MK_ENUM_CONST(1) + +// Enable lock feature for selected apertures 4 Can be set only once register field, h/w reset OR controller reset ONLY +// can disable this feature. +// LOCK_APER_START4, LOCK_APER_END4, LOCK_APER_CHIPID4 cant be +// programmed once this SET +// +#define NAND_LOCK_CONTROL_0_LOCK_APER_EN4_SHIFT _MK_SHIFT_CONST(4) +#define NAND_LOCK_CONTROL_0_LOCK_APER_EN4_FIELD (_MK_MASK_CONST(0x1) << NAND_LOCK_CONTROL_0_LOCK_APER_EN4_SHIFT) +#define NAND_LOCK_CONTROL_0_LOCK_APER_EN4_RANGE 4:4 +#define NAND_LOCK_CONTROL_0_LOCK_APER_EN4_WOFFSET 0x0 +#define NAND_LOCK_CONTROL_0_LOCK_APER_EN4_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_CONTROL_0_LOCK_APER_EN4_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_LOCK_CONTROL_0_LOCK_APER_EN4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_CONTROL_0_LOCK_APER_EN4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_CONTROL_0_LOCK_APER_EN4_DISABLE _MK_ENUM_CONST(0) +#define NAND_LOCK_CONTROL_0_LOCK_APER_EN4_ENABLE _MK_ENUM_CONST(1) + +// Enable lock feature for selected apertures 3 Can be set only once register field, h/w reset OR controller reset ONLY +// can disable this feature. +// LOCK_APER_START3, LOCK_APER_END3, LOCK_APER_CHIPID3 cant be +// programmed once this SET +#define NAND_LOCK_CONTROL_0_LOCK_APER_EN3_SHIFT _MK_SHIFT_CONST(3) +#define NAND_LOCK_CONTROL_0_LOCK_APER_EN3_FIELD (_MK_MASK_CONST(0x1) << NAND_LOCK_CONTROL_0_LOCK_APER_EN3_SHIFT) +#define NAND_LOCK_CONTROL_0_LOCK_APER_EN3_RANGE 3:3 +#define NAND_LOCK_CONTROL_0_LOCK_APER_EN3_WOFFSET 0x0 +#define NAND_LOCK_CONTROL_0_LOCK_APER_EN3_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_CONTROL_0_LOCK_APER_EN3_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_LOCK_CONTROL_0_LOCK_APER_EN3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_CONTROL_0_LOCK_APER_EN3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_CONTROL_0_LOCK_APER_EN3_DISABLE _MK_ENUM_CONST(0) +#define NAND_LOCK_CONTROL_0_LOCK_APER_EN3_ENABLE _MK_ENUM_CONST(1) + +// Enable lock feature for selected apertures 2 Can be set only once register field, h/w reset OR controller reset ONLY +// can disable this feature. +// LOCK_APER_START2, LOCK_APER_END2, LOCK_APER_CHIPID2 cant be +// programmed once this SET +#define NAND_LOCK_CONTROL_0_LOCK_APER_EN2_SHIFT _MK_SHIFT_CONST(2) +#define NAND_LOCK_CONTROL_0_LOCK_APER_EN2_FIELD (_MK_MASK_CONST(0x1) << NAND_LOCK_CONTROL_0_LOCK_APER_EN2_SHIFT) +#define NAND_LOCK_CONTROL_0_LOCK_APER_EN2_RANGE 2:2 +#define NAND_LOCK_CONTROL_0_LOCK_APER_EN2_WOFFSET 0x0 +#define NAND_LOCK_CONTROL_0_LOCK_APER_EN2_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_CONTROL_0_LOCK_APER_EN2_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_LOCK_CONTROL_0_LOCK_APER_EN2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_CONTROL_0_LOCK_APER_EN2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_CONTROL_0_LOCK_APER_EN2_DISABLE _MK_ENUM_CONST(0) +#define NAND_LOCK_CONTROL_0_LOCK_APER_EN2_ENABLE _MK_ENUM_CONST(1) + +// Enable lock feature for selected apertures 1 Can be set only once register field, h/w reset OR controller reset ONLY +// can disable this feature. +// LOCK_APER_START1, LOCK_APER_END1, LOCK_APER_CHIPID1 cant be +// programmed once this SET +#define NAND_LOCK_CONTROL_0_LOCK_APER_EN1_SHIFT _MK_SHIFT_CONST(1) +#define NAND_LOCK_CONTROL_0_LOCK_APER_EN1_FIELD (_MK_MASK_CONST(0x1) << NAND_LOCK_CONTROL_0_LOCK_APER_EN1_SHIFT) +#define NAND_LOCK_CONTROL_0_LOCK_APER_EN1_RANGE 1:1 +#define NAND_LOCK_CONTROL_0_LOCK_APER_EN1_WOFFSET 0x0 +#define NAND_LOCK_CONTROL_0_LOCK_APER_EN1_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_CONTROL_0_LOCK_APER_EN1_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_LOCK_CONTROL_0_LOCK_APER_EN1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_CONTROL_0_LOCK_APER_EN1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_CONTROL_0_LOCK_APER_EN1_DISABLE _MK_ENUM_CONST(0) +#define NAND_LOCK_CONTROL_0_LOCK_APER_EN1_ENABLE _MK_ENUM_CONST(1) + +// Enable lock feature for selected apertures 0 Can be set only once register field, h/w reset OR controller reset ONLY +// can disable this feature. +// LOCK_APER_START0, LOCK_APER_END0, LOCK_APER_CHIPID0 cant be +// programmed once this SET +#define NAND_LOCK_CONTROL_0_LOCK_APER_EN0_SHIFT _MK_SHIFT_CONST(0) +#define NAND_LOCK_CONTROL_0_LOCK_APER_EN0_FIELD (_MK_MASK_CONST(0x1) << NAND_LOCK_CONTROL_0_LOCK_APER_EN0_SHIFT) +#define NAND_LOCK_CONTROL_0_LOCK_APER_EN0_RANGE 0:0 +#define NAND_LOCK_CONTROL_0_LOCK_APER_EN0_WOFFSET 0x0 +#define NAND_LOCK_CONTROL_0_LOCK_APER_EN0_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_CONTROL_0_LOCK_APER_EN0_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_LOCK_CONTROL_0_LOCK_APER_EN0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_CONTROL_0_LOCK_APER_EN0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_CONTROL_0_LOCK_APER_EN0_DISABLE _MK_ENUM_CONST(0) +#define NAND_LOCK_CONTROL_0_LOCK_APER_EN0_ENABLE _MK_ENUM_CONST(1) + + +// Register NAND_LOCK_STATUS_0 +#define NAND_LOCK_STATUS_0 _MK_ADDR_CONST(0x68) +#define NAND_LOCK_STATUS_0_SECURE 0x0 +#define NAND_LOCK_STATUS_0_WORD_COUNT 0x1 +#define NAND_LOCK_STATUS_0_RESET_VAL _MK_MASK_CONST(0x0) +#define NAND_LOCK_STATUS_0_RESET_MASK _MK_MASK_CONST(0x1ff) +#define NAND_LOCK_STATUS_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define NAND_LOCK_STATUS_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_STATUS_0_READ_MASK _MK_MASK_CONST(0x1ff) +#define NAND_LOCK_STATUS_0_WRITE_MASK _MK_MASK_CONST(0x1ff) +// 1 = Memory protection error detected +// check LOCK_STATUS register to identify +// which aperture matched. +#define NAND_LOCK_STATUS_0_IS_LOCK_ERR_SHIFT _MK_SHIFT_CONST(8) +#define NAND_LOCK_STATUS_0_IS_LOCK_ERR_FIELD (_MK_MASK_CONST(0x1) << NAND_LOCK_STATUS_0_IS_LOCK_ERR_SHIFT) +#define NAND_LOCK_STATUS_0_IS_LOCK_ERR_RANGE 8:8 +#define NAND_LOCK_STATUS_0_IS_LOCK_ERR_WOFFSET 0x0 +#define NAND_LOCK_STATUS_0_IS_LOCK_ERR_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_STATUS_0_IS_LOCK_ERR_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_LOCK_STATUS_0_IS_LOCK_ERR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_STATUS_0_IS_LOCK_ERR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// Respective bit is set by HW on protection range detection. +// Write 1 to clear IS.LOCK_ERR will clear this status information +#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS7_SHIFT _MK_SHIFT_CONST(7) +#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS7_FIELD (_MK_MASK_CONST(0x1) << NAND_LOCK_STATUS_0_LOCK_APER_STATUS7_SHIFT) +#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS7_RANGE 7:7 +#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS7_WOFFSET 0x0 +#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS7_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS7_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS7_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS7_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// Respective bit is set by HW on protection range detection. +// Write 1 to clear IS.LOCK_ERR will clear this status information +#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS6_SHIFT _MK_SHIFT_CONST(6) +#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS6_FIELD (_MK_MASK_CONST(0x1) << NAND_LOCK_STATUS_0_LOCK_APER_STATUS6_SHIFT) +#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS6_RANGE 6:6 +#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS6_WOFFSET 0x0 +#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS6_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS6_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS6_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS6_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// Respective bit is set by HW on protection range detection. +// Write 1 to clear IS.LOCK_ERR will clear this status information +#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS5_SHIFT _MK_SHIFT_CONST(5) +#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS5_FIELD (_MK_MASK_CONST(0x1) << NAND_LOCK_STATUS_0_LOCK_APER_STATUS5_SHIFT) +#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS5_RANGE 5:5 +#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS5_WOFFSET 0x0 +#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS5_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS5_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS5_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// Respective bit is set by HW on protection range detection. +// Write 1 to clear IS.LOCK_ERR will clear this status information +#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS4_SHIFT _MK_SHIFT_CONST(4) +#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS4_FIELD (_MK_MASK_CONST(0x1) << NAND_LOCK_STATUS_0_LOCK_APER_STATUS4_SHIFT) +#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS4_RANGE 4:4 +#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS4_WOFFSET 0x0 +#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS4_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS4_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// Respective bit is set by HW on protection range detection. +// Write 1 to clear IS.LOCK_ERR will clear this status information +#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS3_SHIFT _MK_SHIFT_CONST(3) +#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS3_FIELD (_MK_MASK_CONST(0x1) << NAND_LOCK_STATUS_0_LOCK_APER_STATUS3_SHIFT) +#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS3_RANGE 3:3 +#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS3_WOFFSET 0x0 +#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS3_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS3_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// Respective bit is set by HW on protection range detection. +// Write 1 to clear IS.LOCK_ERR will clear this status information +#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS2_SHIFT _MK_SHIFT_CONST(2) +#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS2_FIELD (_MK_MASK_CONST(0x1) << NAND_LOCK_STATUS_0_LOCK_APER_STATUS2_SHIFT) +#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS2_RANGE 2:2 +#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS2_WOFFSET 0x0 +#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS2_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS2_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// Respective bit is set by HW on protection range detection. +// Write 1 to clear IS.LOCK_ERR will clear this status information +#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS1_SHIFT _MK_SHIFT_CONST(1) +#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS1_FIELD (_MK_MASK_CONST(0x1) << NAND_LOCK_STATUS_0_LOCK_APER_STATUS1_SHIFT) +#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS1_RANGE 1:1 +#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS1_WOFFSET 0x0 +#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS1_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS1_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// Respective bit is set by HW on protection range detection. +// Write 1 to clear IS.LOCK_ERR will clear this status information +#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS0_SHIFT _MK_SHIFT_CONST(0) +#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS0_FIELD (_MK_MASK_CONST(0x1) << NAND_LOCK_STATUS_0_LOCK_APER_STATUS0_SHIFT) +#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS0_RANGE 0:0 +#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS0_WOFFSET 0x0 +#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS0_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS0_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register NAND_LOCK_APER_START0_0 +#define NAND_LOCK_APER_START0_0 _MK_ADDR_CONST(0x6c) +#define NAND_LOCK_APER_START0_0_SECURE 0x0 +#define NAND_LOCK_APER_START0_0_WORD_COUNT 0x1 +#define NAND_LOCK_APER_START0_0_RESET_VAL _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_START0_0_RESET_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_START0_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_START0_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_START0_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define NAND_LOCK_APER_START0_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define NAND_LOCK_APER_START0_0_ADDR_SHIFT _MK_SHIFT_CONST(0) +#define NAND_LOCK_APER_START0_0_ADDR_FIELD (_MK_MASK_CONST(0xffffffff) << NAND_LOCK_APER_START0_0_ADDR_SHIFT) +#define NAND_LOCK_APER_START0_0_ADDR_RANGE 31:0 +#define NAND_LOCK_APER_START0_0_ADDR_WOFFSET 0x0 +#define NAND_LOCK_APER_START0_0_ADDR_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_START0_0_ADDR_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_START0_0_ADDR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_START0_0_ADDR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register NAND_LOCK_APER_START1_0 +#define NAND_LOCK_APER_START1_0 _MK_ADDR_CONST(0x70) +#define NAND_LOCK_APER_START1_0_SECURE 0x0 +#define NAND_LOCK_APER_START1_0_WORD_COUNT 0x1 +#define NAND_LOCK_APER_START1_0_RESET_VAL _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_START1_0_RESET_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_START1_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_START1_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_START1_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define NAND_LOCK_APER_START1_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define NAND_LOCK_APER_START1_0_ADDR_SHIFT _MK_SHIFT_CONST(0) +#define NAND_LOCK_APER_START1_0_ADDR_FIELD (_MK_MASK_CONST(0xffffffff) << NAND_LOCK_APER_START1_0_ADDR_SHIFT) +#define NAND_LOCK_APER_START1_0_ADDR_RANGE 31:0 +#define NAND_LOCK_APER_START1_0_ADDR_WOFFSET 0x0 +#define NAND_LOCK_APER_START1_0_ADDR_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_START1_0_ADDR_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_START1_0_ADDR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_START1_0_ADDR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register NAND_LOCK_APER_START2_0 +#define NAND_LOCK_APER_START2_0 _MK_ADDR_CONST(0x74) +#define NAND_LOCK_APER_START2_0_SECURE 0x0 +#define NAND_LOCK_APER_START2_0_WORD_COUNT 0x1 +#define NAND_LOCK_APER_START2_0_RESET_VAL _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_START2_0_RESET_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_START2_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_START2_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_START2_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define NAND_LOCK_APER_START2_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define NAND_LOCK_APER_START2_0_ADDR_SHIFT _MK_SHIFT_CONST(0) +#define NAND_LOCK_APER_START2_0_ADDR_FIELD (_MK_MASK_CONST(0xffffffff) << NAND_LOCK_APER_START2_0_ADDR_SHIFT) +#define NAND_LOCK_APER_START2_0_ADDR_RANGE 31:0 +#define NAND_LOCK_APER_START2_0_ADDR_WOFFSET 0x0 +#define NAND_LOCK_APER_START2_0_ADDR_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_START2_0_ADDR_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_START2_0_ADDR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_START2_0_ADDR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register NAND_LOCK_APER_START3_0 +#define NAND_LOCK_APER_START3_0 _MK_ADDR_CONST(0x78) +#define NAND_LOCK_APER_START3_0_SECURE 0x0 +#define NAND_LOCK_APER_START3_0_WORD_COUNT 0x1 +#define NAND_LOCK_APER_START3_0_RESET_VAL _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_START3_0_RESET_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_START3_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_START3_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_START3_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define NAND_LOCK_APER_START3_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define NAND_LOCK_APER_START3_0_ADDR_SHIFT _MK_SHIFT_CONST(0) +#define NAND_LOCK_APER_START3_0_ADDR_FIELD (_MK_MASK_CONST(0xffffffff) << NAND_LOCK_APER_START3_0_ADDR_SHIFT) +#define NAND_LOCK_APER_START3_0_ADDR_RANGE 31:0 +#define NAND_LOCK_APER_START3_0_ADDR_WOFFSET 0x0 +#define NAND_LOCK_APER_START3_0_ADDR_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_START3_0_ADDR_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_START3_0_ADDR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_START3_0_ADDR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register NAND_LOCK_APER_START4_0 +#define NAND_LOCK_APER_START4_0 _MK_ADDR_CONST(0x7c) +#define NAND_LOCK_APER_START4_0_SECURE 0x0 +#define NAND_LOCK_APER_START4_0_WORD_COUNT 0x1 +#define NAND_LOCK_APER_START4_0_RESET_VAL _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_START4_0_RESET_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_START4_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_START4_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_START4_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define NAND_LOCK_APER_START4_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define NAND_LOCK_APER_START4_0_ADDR_SHIFT _MK_SHIFT_CONST(0) +#define NAND_LOCK_APER_START4_0_ADDR_FIELD (_MK_MASK_CONST(0xffffffff) << NAND_LOCK_APER_START4_0_ADDR_SHIFT) +#define NAND_LOCK_APER_START4_0_ADDR_RANGE 31:0 +#define NAND_LOCK_APER_START4_0_ADDR_WOFFSET 0x0 +#define NAND_LOCK_APER_START4_0_ADDR_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_START4_0_ADDR_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_START4_0_ADDR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_START4_0_ADDR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register NAND_LOCK_APER_START5_0 +#define NAND_LOCK_APER_START5_0 _MK_ADDR_CONST(0x80) +#define NAND_LOCK_APER_START5_0_SECURE 0x0 +#define NAND_LOCK_APER_START5_0_WORD_COUNT 0x1 +#define NAND_LOCK_APER_START5_0_RESET_VAL _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_START5_0_RESET_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_START5_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_START5_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_START5_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define NAND_LOCK_APER_START5_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define NAND_LOCK_APER_START5_0_ADDR_SHIFT _MK_SHIFT_CONST(0) +#define NAND_LOCK_APER_START5_0_ADDR_FIELD (_MK_MASK_CONST(0xffffffff) << NAND_LOCK_APER_START5_0_ADDR_SHIFT) +#define NAND_LOCK_APER_START5_0_ADDR_RANGE 31:0 +#define NAND_LOCK_APER_START5_0_ADDR_WOFFSET 0x0 +#define NAND_LOCK_APER_START5_0_ADDR_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_START5_0_ADDR_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_START5_0_ADDR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_START5_0_ADDR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register NAND_LOCK_APER_START6_0 +#define NAND_LOCK_APER_START6_0 _MK_ADDR_CONST(0x84) +#define NAND_LOCK_APER_START6_0_SECURE 0x0 +#define NAND_LOCK_APER_START6_0_WORD_COUNT 0x1 +#define NAND_LOCK_APER_START6_0_RESET_VAL _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_START6_0_RESET_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_START6_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_START6_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_START6_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define NAND_LOCK_APER_START6_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define NAND_LOCK_APER_START6_0_ADDR_SHIFT _MK_SHIFT_CONST(0) +#define NAND_LOCK_APER_START6_0_ADDR_FIELD (_MK_MASK_CONST(0xffffffff) << NAND_LOCK_APER_START6_0_ADDR_SHIFT) +#define NAND_LOCK_APER_START6_0_ADDR_RANGE 31:0 +#define NAND_LOCK_APER_START6_0_ADDR_WOFFSET 0x0 +#define NAND_LOCK_APER_START6_0_ADDR_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_START6_0_ADDR_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_START6_0_ADDR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_START6_0_ADDR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register NAND_LOCK_APER_START7_0 +#define NAND_LOCK_APER_START7_0 _MK_ADDR_CONST(0x88) +#define NAND_LOCK_APER_START7_0_SECURE 0x0 +#define NAND_LOCK_APER_START7_0_WORD_COUNT 0x1 +#define NAND_LOCK_APER_START7_0_RESET_VAL _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_START7_0_RESET_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_START7_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_START7_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_START7_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define NAND_LOCK_APER_START7_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define NAND_LOCK_APER_START7_0_ADDR_SHIFT _MK_SHIFT_CONST(0) +#define NAND_LOCK_APER_START7_0_ADDR_FIELD (_MK_MASK_CONST(0xffffffff) << NAND_LOCK_APER_START7_0_ADDR_SHIFT) +#define NAND_LOCK_APER_START7_0_ADDR_RANGE 31:0 +#define NAND_LOCK_APER_START7_0_ADDR_WOFFSET 0x0 +#define NAND_LOCK_APER_START7_0_ADDR_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_START7_0_ADDR_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_START7_0_ADDR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_START7_0_ADDR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register NAND_LOCK_APER_END0_0 +#define NAND_LOCK_APER_END0_0 _MK_ADDR_CONST(0x8c) +#define NAND_LOCK_APER_END0_0_SECURE 0x0 +#define NAND_LOCK_APER_END0_0_WORD_COUNT 0x1 +#define NAND_LOCK_APER_END0_0_RESET_VAL _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_END0_0_RESET_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_END0_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_END0_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_END0_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define NAND_LOCK_APER_END0_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define NAND_LOCK_APER_END0_0_ADDR_SHIFT _MK_SHIFT_CONST(0) +#define NAND_LOCK_APER_END0_0_ADDR_FIELD (_MK_MASK_CONST(0xffffffff) << NAND_LOCK_APER_END0_0_ADDR_SHIFT) +#define NAND_LOCK_APER_END0_0_ADDR_RANGE 31:0 +#define NAND_LOCK_APER_END0_0_ADDR_WOFFSET 0x0 +#define NAND_LOCK_APER_END0_0_ADDR_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_END0_0_ADDR_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_END0_0_ADDR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_END0_0_ADDR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register NAND_LOCK_APER_END1_0 +#define NAND_LOCK_APER_END1_0 _MK_ADDR_CONST(0x90) +#define NAND_LOCK_APER_END1_0_SECURE 0x0 +#define NAND_LOCK_APER_END1_0_WORD_COUNT 0x1 +#define NAND_LOCK_APER_END1_0_RESET_VAL _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_END1_0_RESET_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_END1_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_END1_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_END1_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define NAND_LOCK_APER_END1_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define NAND_LOCK_APER_END1_0_ADDR_SHIFT _MK_SHIFT_CONST(0) +#define NAND_LOCK_APER_END1_0_ADDR_FIELD (_MK_MASK_CONST(0xffffffff) << NAND_LOCK_APER_END1_0_ADDR_SHIFT) +#define NAND_LOCK_APER_END1_0_ADDR_RANGE 31:0 +#define NAND_LOCK_APER_END1_0_ADDR_WOFFSET 0x0 +#define NAND_LOCK_APER_END1_0_ADDR_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_END1_0_ADDR_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_END1_0_ADDR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_END1_0_ADDR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register NAND_LOCK_APER_END2_0 +#define NAND_LOCK_APER_END2_0 _MK_ADDR_CONST(0x94) +#define NAND_LOCK_APER_END2_0_SECURE 0x0 +#define NAND_LOCK_APER_END2_0_WORD_COUNT 0x1 +#define NAND_LOCK_APER_END2_0_RESET_VAL _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_END2_0_RESET_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_END2_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_END2_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_END2_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define NAND_LOCK_APER_END2_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define NAND_LOCK_APER_END2_0_ADDR_SHIFT _MK_SHIFT_CONST(0) +#define NAND_LOCK_APER_END2_0_ADDR_FIELD (_MK_MASK_CONST(0xffffffff) << NAND_LOCK_APER_END2_0_ADDR_SHIFT) +#define NAND_LOCK_APER_END2_0_ADDR_RANGE 31:0 +#define NAND_LOCK_APER_END2_0_ADDR_WOFFSET 0x0 +#define NAND_LOCK_APER_END2_0_ADDR_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_END2_0_ADDR_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_END2_0_ADDR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_END2_0_ADDR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register NAND_LOCK_APER_END3_0 +#define NAND_LOCK_APER_END3_0 _MK_ADDR_CONST(0x98) +#define NAND_LOCK_APER_END3_0_SECURE 0x0 +#define NAND_LOCK_APER_END3_0_WORD_COUNT 0x1 +#define NAND_LOCK_APER_END3_0_RESET_VAL _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_END3_0_RESET_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_END3_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_END3_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_END3_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define NAND_LOCK_APER_END3_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define NAND_LOCK_APER_END3_0_ADDR_SHIFT _MK_SHIFT_CONST(0) +#define NAND_LOCK_APER_END3_0_ADDR_FIELD (_MK_MASK_CONST(0xffffffff) << NAND_LOCK_APER_END3_0_ADDR_SHIFT) +#define NAND_LOCK_APER_END3_0_ADDR_RANGE 31:0 +#define NAND_LOCK_APER_END3_0_ADDR_WOFFSET 0x0 +#define NAND_LOCK_APER_END3_0_ADDR_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_END3_0_ADDR_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_END3_0_ADDR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_END3_0_ADDR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register NAND_LOCK_APER_END4_0 +#define NAND_LOCK_APER_END4_0 _MK_ADDR_CONST(0x9c) +#define NAND_LOCK_APER_END4_0_SECURE 0x0 +#define NAND_LOCK_APER_END4_0_WORD_COUNT 0x1 +#define NAND_LOCK_APER_END4_0_RESET_VAL _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_END4_0_RESET_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_END4_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_END4_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_END4_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define NAND_LOCK_APER_END4_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define NAND_LOCK_APER_END4_0_ADDR_SHIFT _MK_SHIFT_CONST(0) +#define NAND_LOCK_APER_END4_0_ADDR_FIELD (_MK_MASK_CONST(0xffffffff) << NAND_LOCK_APER_END4_0_ADDR_SHIFT) +#define NAND_LOCK_APER_END4_0_ADDR_RANGE 31:0 +#define NAND_LOCK_APER_END4_0_ADDR_WOFFSET 0x0 +#define NAND_LOCK_APER_END4_0_ADDR_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_END4_0_ADDR_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_END4_0_ADDR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_END4_0_ADDR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register NAND_LOCK_APER_END5_0 +#define NAND_LOCK_APER_END5_0 _MK_ADDR_CONST(0xa0) +#define NAND_LOCK_APER_END5_0_SECURE 0x0 +#define NAND_LOCK_APER_END5_0_WORD_COUNT 0x1 +#define NAND_LOCK_APER_END5_0_RESET_VAL _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_END5_0_RESET_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_END5_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_END5_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_END5_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define NAND_LOCK_APER_END5_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define NAND_LOCK_APER_END5_0_ADDR_SHIFT _MK_SHIFT_CONST(0) +#define NAND_LOCK_APER_END5_0_ADDR_FIELD (_MK_MASK_CONST(0xffffffff) << NAND_LOCK_APER_END5_0_ADDR_SHIFT) +#define NAND_LOCK_APER_END5_0_ADDR_RANGE 31:0 +#define NAND_LOCK_APER_END5_0_ADDR_WOFFSET 0x0 +#define NAND_LOCK_APER_END5_0_ADDR_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_END5_0_ADDR_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_END5_0_ADDR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_END5_0_ADDR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register NAND_LOCK_APER_END6_0 +#define NAND_LOCK_APER_END6_0 _MK_ADDR_CONST(0xa4) +#define NAND_LOCK_APER_END6_0_SECURE 0x0 +#define NAND_LOCK_APER_END6_0_WORD_COUNT 0x1 +#define NAND_LOCK_APER_END6_0_RESET_VAL _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_END6_0_RESET_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_END6_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_END6_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_END6_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define NAND_LOCK_APER_END6_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define NAND_LOCK_APER_END6_0_ADDR_SHIFT _MK_SHIFT_CONST(0) +#define NAND_LOCK_APER_END6_0_ADDR_FIELD (_MK_MASK_CONST(0xffffffff) << NAND_LOCK_APER_END6_0_ADDR_SHIFT) +#define NAND_LOCK_APER_END6_0_ADDR_RANGE 31:0 +#define NAND_LOCK_APER_END6_0_ADDR_WOFFSET 0x0 +#define NAND_LOCK_APER_END6_0_ADDR_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_END6_0_ADDR_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_END6_0_ADDR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_END6_0_ADDR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register NAND_LOCK_APER_END7_0 +#define NAND_LOCK_APER_END7_0 _MK_ADDR_CONST(0xa8) +#define NAND_LOCK_APER_END7_0_SECURE 0x0 +#define NAND_LOCK_APER_END7_0_WORD_COUNT 0x1 +#define NAND_LOCK_APER_END7_0_RESET_VAL _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_END7_0_RESET_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_END7_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_END7_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_END7_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define NAND_LOCK_APER_END7_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define NAND_LOCK_APER_END7_0_ADDR_SHIFT _MK_SHIFT_CONST(0) +#define NAND_LOCK_APER_END7_0_ADDR_FIELD (_MK_MASK_CONST(0xffffffff) << NAND_LOCK_APER_END7_0_ADDR_SHIFT) +#define NAND_LOCK_APER_END7_0_ADDR_RANGE 31:0 +#define NAND_LOCK_APER_END7_0_ADDR_WOFFSET 0x0 +#define NAND_LOCK_APER_END7_0_ADDR_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_END7_0_ADDR_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_END7_0_ADDR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_END7_0_ADDR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register NAND_LOCK_APER_CHIPID0_0 +#define NAND_LOCK_APER_CHIPID0_0 _MK_ADDR_CONST(0xac) +#define NAND_LOCK_APER_CHIPID0_0_SECURE 0x0 +#define NAND_LOCK_APER_CHIPID0_0_WORD_COUNT 0x1 +#define NAND_LOCK_APER_CHIPID0_0_RESET_VAL _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID0_0_RESET_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID0_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID0_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID0_0_READ_MASK _MK_MASK_CONST(0xff) +#define NAND_LOCK_APER_CHIPID0_0_WRITE_MASK _MK_MASK_CONST(0xff) +// Memory Protection of aperture[0-7] valid for Chip select7 +#define NAND_LOCK_APER_CHIPID0_0_CS7_SHIFT _MK_SHIFT_CONST(7) +#define NAND_LOCK_APER_CHIPID0_0_CS7_FIELD (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID0_0_CS7_SHIFT) +#define NAND_LOCK_APER_CHIPID0_0_CS7_RANGE 7:7 +#define NAND_LOCK_APER_CHIPID0_0_CS7_WOFFSET 0x0 +#define NAND_LOCK_APER_CHIPID0_0_CS7_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID0_0_CS7_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID0_0_CS7_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID0_0_CS7_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID0_0_CS7_DISABLE _MK_ENUM_CONST(0) // // Memory Protection of aperture[0-7] not valid for Chip select7 + +#define NAND_LOCK_APER_CHIPID0_0_CS7_ENABLE _MK_ENUM_CONST(1) + +// Memory Protection of aperture[0-7] valid for Chip select6 +#define NAND_LOCK_APER_CHIPID0_0_CS6_SHIFT _MK_SHIFT_CONST(6) +#define NAND_LOCK_APER_CHIPID0_0_CS6_FIELD (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID0_0_CS6_SHIFT) +#define NAND_LOCK_APER_CHIPID0_0_CS6_RANGE 6:6 +#define NAND_LOCK_APER_CHIPID0_0_CS6_WOFFSET 0x0 +#define NAND_LOCK_APER_CHIPID0_0_CS6_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID0_0_CS6_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID0_0_CS6_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID0_0_CS6_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID0_0_CS6_DISABLE _MK_ENUM_CONST(0) // // Memory Protection of aperture[0-7] not valid for Chip select6 + +#define NAND_LOCK_APER_CHIPID0_0_CS6_ENABLE _MK_ENUM_CONST(1) + +// Memory Protection of aperture[0-7] valid for Chip select5 +#define NAND_LOCK_APER_CHIPID0_0_CS5_SHIFT _MK_SHIFT_CONST(5) +#define NAND_LOCK_APER_CHIPID0_0_CS5_FIELD (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID0_0_CS5_SHIFT) +#define NAND_LOCK_APER_CHIPID0_0_CS5_RANGE 5:5 +#define NAND_LOCK_APER_CHIPID0_0_CS5_WOFFSET 0x0 +#define NAND_LOCK_APER_CHIPID0_0_CS5_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID0_0_CS5_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID0_0_CS5_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID0_0_CS5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID0_0_CS5_DISABLE _MK_ENUM_CONST(0) // // Memory Protection of aperture[0-7] not valid for Chip select5 + +#define NAND_LOCK_APER_CHIPID0_0_CS5_ENABLE _MK_ENUM_CONST(1) + +// Memory Protection of aperture[0-7] valid for Chip select4 +#define NAND_LOCK_APER_CHIPID0_0_CS4_SHIFT _MK_SHIFT_CONST(4) +#define NAND_LOCK_APER_CHIPID0_0_CS4_FIELD (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID0_0_CS4_SHIFT) +#define NAND_LOCK_APER_CHIPID0_0_CS4_RANGE 4:4 +#define NAND_LOCK_APER_CHIPID0_0_CS4_WOFFSET 0x0 +#define NAND_LOCK_APER_CHIPID0_0_CS4_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID0_0_CS4_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID0_0_CS4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID0_0_CS4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID0_0_CS4_DISABLE _MK_ENUM_CONST(0) // // Memory Protection of aperture[0-7] not valid for Chip select4 + +#define NAND_LOCK_APER_CHIPID0_0_CS4_ENABLE _MK_ENUM_CONST(1) + +// Memory Protection of aperture[0-7] valid for Chip select3 +#define NAND_LOCK_APER_CHIPID0_0_CS3_SHIFT _MK_SHIFT_CONST(3) +#define NAND_LOCK_APER_CHIPID0_0_CS3_FIELD (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID0_0_CS3_SHIFT) +#define NAND_LOCK_APER_CHIPID0_0_CS3_RANGE 3:3 +#define NAND_LOCK_APER_CHIPID0_0_CS3_WOFFSET 0x0 +#define NAND_LOCK_APER_CHIPID0_0_CS3_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID0_0_CS3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID0_0_CS3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID0_0_CS3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID0_0_CS3_DISABLE _MK_ENUM_CONST(0) // // Memory Protection of aperture[0-7] not valid for Chip select3 + +#define NAND_LOCK_APER_CHIPID0_0_CS3_ENABLE _MK_ENUM_CONST(1) + +// Memory Protection of aperture[0-7] valid for Chip select2 +#define NAND_LOCK_APER_CHIPID0_0_CS2_SHIFT _MK_SHIFT_CONST(2) +#define NAND_LOCK_APER_CHIPID0_0_CS2_FIELD (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID0_0_CS2_SHIFT) +#define NAND_LOCK_APER_CHIPID0_0_CS2_RANGE 2:2 +#define NAND_LOCK_APER_CHIPID0_0_CS2_WOFFSET 0x0 +#define NAND_LOCK_APER_CHIPID0_0_CS2_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID0_0_CS2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID0_0_CS2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID0_0_CS2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID0_0_CS2_DISABLE _MK_ENUM_CONST(0) // // Memory Protection of aperture[0-7] not valid for Chip select2 + +#define NAND_LOCK_APER_CHIPID0_0_CS2_ENABLE _MK_ENUM_CONST(1) + +// Memory Protection of aperture[0-7] valid for Chip select1 +#define NAND_LOCK_APER_CHIPID0_0_CS1_SHIFT _MK_SHIFT_CONST(1) +#define NAND_LOCK_APER_CHIPID0_0_CS1_FIELD (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID0_0_CS1_SHIFT) +#define NAND_LOCK_APER_CHIPID0_0_CS1_RANGE 1:1 +#define NAND_LOCK_APER_CHIPID0_0_CS1_WOFFSET 0x0 +#define NAND_LOCK_APER_CHIPID0_0_CS1_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID0_0_CS1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID0_0_CS1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID0_0_CS1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID0_0_CS1_DISABLE _MK_ENUM_CONST(0) // // Memory Protection of aperture[0-7] not valid for Chip select1 + +#define NAND_LOCK_APER_CHIPID0_0_CS1_ENABLE _MK_ENUM_CONST(1) + +// Memory Protection of aperture[0-7] valid for Chip select0 +#define NAND_LOCK_APER_CHIPID0_0_CS0_SHIFT _MK_SHIFT_CONST(0) +#define NAND_LOCK_APER_CHIPID0_0_CS0_FIELD (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID0_0_CS0_SHIFT) +#define NAND_LOCK_APER_CHIPID0_0_CS0_RANGE 0:0 +#define NAND_LOCK_APER_CHIPID0_0_CS0_WOFFSET 0x0 +#define NAND_LOCK_APER_CHIPID0_0_CS0_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID0_0_CS0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID0_0_CS0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID0_0_CS0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID0_0_CS0_DISABLE _MK_ENUM_CONST(0) // // Memory Protection of aperture[0-7] not valid for Chip select0 + +#define NAND_LOCK_APER_CHIPID0_0_CS0_ENABLE _MK_ENUM_CONST(1) + + +// Register NAND_LOCK_APER_CHIPID1_0 +#define NAND_LOCK_APER_CHIPID1_0 _MK_ADDR_CONST(0xb0) +#define NAND_LOCK_APER_CHIPID1_0_SECURE 0x0 +#define NAND_LOCK_APER_CHIPID1_0_WORD_COUNT 0x1 +#define NAND_LOCK_APER_CHIPID1_0_RESET_VAL _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID1_0_RESET_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID1_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID1_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID1_0_READ_MASK _MK_MASK_CONST(0xff) +#define NAND_LOCK_APER_CHIPID1_0_WRITE_MASK _MK_MASK_CONST(0xff) +// Memory Protection of aperture[0-7] valid for Chip select7 +#define NAND_LOCK_APER_CHIPID1_0_CS7_SHIFT _MK_SHIFT_CONST(7) +#define NAND_LOCK_APER_CHIPID1_0_CS7_FIELD (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID1_0_CS7_SHIFT) +#define NAND_LOCK_APER_CHIPID1_0_CS7_RANGE 7:7 +#define NAND_LOCK_APER_CHIPID1_0_CS7_WOFFSET 0x0 +#define NAND_LOCK_APER_CHIPID1_0_CS7_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID1_0_CS7_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID1_0_CS7_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID1_0_CS7_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID1_0_CS7_DISABLE _MK_ENUM_CONST(0) // // Memory Protection of aperture[0-7] not valid for Chip select7 + +#define NAND_LOCK_APER_CHIPID1_0_CS7_ENABLE _MK_ENUM_CONST(1) + +// Memory Protection of aperture[0-7] valid for Chip select6 +#define NAND_LOCK_APER_CHIPID1_0_CS6_SHIFT _MK_SHIFT_CONST(6) +#define NAND_LOCK_APER_CHIPID1_0_CS6_FIELD (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID1_0_CS6_SHIFT) +#define NAND_LOCK_APER_CHIPID1_0_CS6_RANGE 6:6 +#define NAND_LOCK_APER_CHIPID1_0_CS6_WOFFSET 0x0 +#define NAND_LOCK_APER_CHIPID1_0_CS6_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID1_0_CS6_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID1_0_CS6_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID1_0_CS6_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID1_0_CS6_DISABLE _MK_ENUM_CONST(0) // // Memory Protection of aperture[0-7] not valid for Chip select6 + +#define NAND_LOCK_APER_CHIPID1_0_CS6_ENABLE _MK_ENUM_CONST(1) + +// Memory Protection of aperture[0-7] valid for Chip select5 +#define NAND_LOCK_APER_CHIPID1_0_CS5_SHIFT _MK_SHIFT_CONST(5) +#define NAND_LOCK_APER_CHIPID1_0_CS5_FIELD (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID1_0_CS5_SHIFT) +#define NAND_LOCK_APER_CHIPID1_0_CS5_RANGE 5:5 +#define NAND_LOCK_APER_CHIPID1_0_CS5_WOFFSET 0x0 +#define NAND_LOCK_APER_CHIPID1_0_CS5_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID1_0_CS5_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID1_0_CS5_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID1_0_CS5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID1_0_CS5_DISABLE _MK_ENUM_CONST(0) // // Memory Protection of aperture[0-7] not valid for Chip select5 + +#define NAND_LOCK_APER_CHIPID1_0_CS5_ENABLE _MK_ENUM_CONST(1) + +// Memory Protection of aperture[0-7] valid for Chip select4 +#define NAND_LOCK_APER_CHIPID1_0_CS4_SHIFT _MK_SHIFT_CONST(4) +#define NAND_LOCK_APER_CHIPID1_0_CS4_FIELD (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID1_0_CS4_SHIFT) +#define NAND_LOCK_APER_CHIPID1_0_CS4_RANGE 4:4 +#define NAND_LOCK_APER_CHIPID1_0_CS4_WOFFSET 0x0 +#define NAND_LOCK_APER_CHIPID1_0_CS4_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID1_0_CS4_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID1_0_CS4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID1_0_CS4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID1_0_CS4_DISABLE _MK_ENUM_CONST(0) // // Memory Protection of aperture[0-7] not valid for Chip select4 + +#define NAND_LOCK_APER_CHIPID1_0_CS4_ENABLE _MK_ENUM_CONST(1) + +// Memory Protection of aperture[0-7] valid for Chip select3 +#define NAND_LOCK_APER_CHIPID1_0_CS3_SHIFT _MK_SHIFT_CONST(3) +#define NAND_LOCK_APER_CHIPID1_0_CS3_FIELD (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID1_0_CS3_SHIFT) +#define NAND_LOCK_APER_CHIPID1_0_CS3_RANGE 3:3 +#define NAND_LOCK_APER_CHIPID1_0_CS3_WOFFSET 0x0 +#define NAND_LOCK_APER_CHIPID1_0_CS3_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID1_0_CS3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID1_0_CS3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID1_0_CS3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID1_0_CS3_DISABLE _MK_ENUM_CONST(0) // // Memory Protection of aperture[0-7] not valid for Chip select3 + +#define NAND_LOCK_APER_CHIPID1_0_CS3_ENABLE _MK_ENUM_CONST(1) + +// Memory Protection of aperture[0-7] valid for Chip select2 +#define NAND_LOCK_APER_CHIPID1_0_CS2_SHIFT _MK_SHIFT_CONST(2) +#define NAND_LOCK_APER_CHIPID1_0_CS2_FIELD (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID1_0_CS2_SHIFT) +#define NAND_LOCK_APER_CHIPID1_0_CS2_RANGE 2:2 +#define NAND_LOCK_APER_CHIPID1_0_CS2_WOFFSET 0x0 +#define NAND_LOCK_APER_CHIPID1_0_CS2_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID1_0_CS2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID1_0_CS2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID1_0_CS2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID1_0_CS2_DISABLE _MK_ENUM_CONST(0) // // Memory Protection of aperture[0-7] not valid for Chip select2 + +#define NAND_LOCK_APER_CHIPID1_0_CS2_ENABLE _MK_ENUM_CONST(1) + +// Memory Protection of aperture[0-7] valid for Chip select1 +#define NAND_LOCK_APER_CHIPID1_0_CS1_SHIFT _MK_SHIFT_CONST(1) +#define NAND_LOCK_APER_CHIPID1_0_CS1_FIELD (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID1_0_CS1_SHIFT) +#define NAND_LOCK_APER_CHIPID1_0_CS1_RANGE 1:1 +#define NAND_LOCK_APER_CHIPID1_0_CS1_WOFFSET 0x0 +#define NAND_LOCK_APER_CHIPID1_0_CS1_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID1_0_CS1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID1_0_CS1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID1_0_CS1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID1_0_CS1_DISABLE _MK_ENUM_CONST(0) // // Memory Protection of aperture[0-7] not valid for Chip select1 + +#define NAND_LOCK_APER_CHIPID1_0_CS1_ENABLE _MK_ENUM_CONST(1) + +// Memory Protection of aperture[0-7] valid for Chip select0 +#define NAND_LOCK_APER_CHIPID1_0_CS0_SHIFT _MK_SHIFT_CONST(0) +#define NAND_LOCK_APER_CHIPID1_0_CS0_FIELD (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID1_0_CS0_SHIFT) +#define NAND_LOCK_APER_CHIPID1_0_CS0_RANGE 0:0 +#define NAND_LOCK_APER_CHIPID1_0_CS0_WOFFSET 0x0 +#define NAND_LOCK_APER_CHIPID1_0_CS0_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID1_0_CS0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID1_0_CS0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID1_0_CS0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID1_0_CS0_DISABLE _MK_ENUM_CONST(0) // // Memory Protection of aperture[0-7] not valid for Chip select0 + +#define NAND_LOCK_APER_CHIPID1_0_CS0_ENABLE _MK_ENUM_CONST(1) + + +// Register NAND_LOCK_APER_CHIPID2_0 +#define NAND_LOCK_APER_CHIPID2_0 _MK_ADDR_CONST(0xb4) +#define NAND_LOCK_APER_CHIPID2_0_SECURE 0x0 +#define NAND_LOCK_APER_CHIPID2_0_WORD_COUNT 0x1 +#define NAND_LOCK_APER_CHIPID2_0_RESET_VAL _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID2_0_RESET_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID2_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID2_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID2_0_READ_MASK _MK_MASK_CONST(0xff) +#define NAND_LOCK_APER_CHIPID2_0_WRITE_MASK _MK_MASK_CONST(0xff) +// Memory Protection of aperture[0-7] valid for Chip select7 +#define NAND_LOCK_APER_CHIPID2_0_CS7_SHIFT _MK_SHIFT_CONST(7) +#define NAND_LOCK_APER_CHIPID2_0_CS7_FIELD (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID2_0_CS7_SHIFT) +#define NAND_LOCK_APER_CHIPID2_0_CS7_RANGE 7:7 +#define NAND_LOCK_APER_CHIPID2_0_CS7_WOFFSET 0x0 +#define NAND_LOCK_APER_CHIPID2_0_CS7_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID2_0_CS7_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID2_0_CS7_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID2_0_CS7_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID2_0_CS7_DISABLE _MK_ENUM_CONST(0) // // Memory Protection of aperture[0-7] not valid for Chip select7 + +#define NAND_LOCK_APER_CHIPID2_0_CS7_ENABLE _MK_ENUM_CONST(1) + +// Memory Protection of aperture[0-7] valid for Chip select6 +#define NAND_LOCK_APER_CHIPID2_0_CS6_SHIFT _MK_SHIFT_CONST(6) +#define NAND_LOCK_APER_CHIPID2_0_CS6_FIELD (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID2_0_CS6_SHIFT) +#define NAND_LOCK_APER_CHIPID2_0_CS6_RANGE 6:6 +#define NAND_LOCK_APER_CHIPID2_0_CS6_WOFFSET 0x0 +#define NAND_LOCK_APER_CHIPID2_0_CS6_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID2_0_CS6_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID2_0_CS6_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID2_0_CS6_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID2_0_CS6_DISABLE _MK_ENUM_CONST(0) // // Memory Protection of aperture[0-7] not valid for Chip select6 + +#define NAND_LOCK_APER_CHIPID2_0_CS6_ENABLE _MK_ENUM_CONST(1) + +// Memory Protection of aperture[0-7] valid for Chip select5 +#define NAND_LOCK_APER_CHIPID2_0_CS5_SHIFT _MK_SHIFT_CONST(5) +#define NAND_LOCK_APER_CHIPID2_0_CS5_FIELD (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID2_0_CS5_SHIFT) +#define NAND_LOCK_APER_CHIPID2_0_CS5_RANGE 5:5 +#define NAND_LOCK_APER_CHIPID2_0_CS5_WOFFSET 0x0 +#define NAND_LOCK_APER_CHIPID2_0_CS5_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID2_0_CS5_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID2_0_CS5_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID2_0_CS5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID2_0_CS5_DISABLE _MK_ENUM_CONST(0) // // Memory Protection of aperture[0-7] not valid for Chip select5 + +#define NAND_LOCK_APER_CHIPID2_0_CS5_ENABLE _MK_ENUM_CONST(1) + +// Memory Protection of aperture[0-7] valid for Chip select4 +#define NAND_LOCK_APER_CHIPID2_0_CS4_SHIFT _MK_SHIFT_CONST(4) +#define NAND_LOCK_APER_CHIPID2_0_CS4_FIELD (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID2_0_CS4_SHIFT) +#define NAND_LOCK_APER_CHIPID2_0_CS4_RANGE 4:4 +#define NAND_LOCK_APER_CHIPID2_0_CS4_WOFFSET 0x0 +#define NAND_LOCK_APER_CHIPID2_0_CS4_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID2_0_CS4_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID2_0_CS4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID2_0_CS4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID2_0_CS4_DISABLE _MK_ENUM_CONST(0) // // Memory Protection of aperture[0-7] not valid for Chip select4 + +#define NAND_LOCK_APER_CHIPID2_0_CS4_ENABLE _MK_ENUM_CONST(1) + +// Memory Protection of aperture[0-7] valid for Chip select3 +#define NAND_LOCK_APER_CHIPID2_0_CS3_SHIFT _MK_SHIFT_CONST(3) +#define NAND_LOCK_APER_CHIPID2_0_CS3_FIELD (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID2_0_CS3_SHIFT) +#define NAND_LOCK_APER_CHIPID2_0_CS3_RANGE 3:3 +#define NAND_LOCK_APER_CHIPID2_0_CS3_WOFFSET 0x0 +#define NAND_LOCK_APER_CHIPID2_0_CS3_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID2_0_CS3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID2_0_CS3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID2_0_CS3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID2_0_CS3_DISABLE _MK_ENUM_CONST(0) // // Memory Protection of aperture[0-7] not valid for Chip select3 + +#define NAND_LOCK_APER_CHIPID2_0_CS3_ENABLE _MK_ENUM_CONST(1) + +// Memory Protection of aperture[0-7] valid for Chip select2 +#define NAND_LOCK_APER_CHIPID2_0_CS2_SHIFT _MK_SHIFT_CONST(2) +#define NAND_LOCK_APER_CHIPID2_0_CS2_FIELD (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID2_0_CS2_SHIFT) +#define NAND_LOCK_APER_CHIPID2_0_CS2_RANGE 2:2 +#define NAND_LOCK_APER_CHIPID2_0_CS2_WOFFSET 0x0 +#define NAND_LOCK_APER_CHIPID2_0_CS2_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID2_0_CS2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID2_0_CS2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID2_0_CS2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID2_0_CS2_DISABLE _MK_ENUM_CONST(0) // // Memory Protection of aperture[0-7] not valid for Chip select2 + +#define NAND_LOCK_APER_CHIPID2_0_CS2_ENABLE _MK_ENUM_CONST(1) + +// Memory Protection of aperture[0-7] valid for Chip select1 +#define NAND_LOCK_APER_CHIPID2_0_CS1_SHIFT _MK_SHIFT_CONST(1) +#define NAND_LOCK_APER_CHIPID2_0_CS1_FIELD (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID2_0_CS1_SHIFT) +#define NAND_LOCK_APER_CHIPID2_0_CS1_RANGE 1:1 +#define NAND_LOCK_APER_CHIPID2_0_CS1_WOFFSET 0x0 +#define NAND_LOCK_APER_CHIPID2_0_CS1_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID2_0_CS1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID2_0_CS1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID2_0_CS1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID2_0_CS1_DISABLE _MK_ENUM_CONST(0) // // Memory Protection of aperture[0-7] not valid for Chip select1 + +#define NAND_LOCK_APER_CHIPID2_0_CS1_ENABLE _MK_ENUM_CONST(1) + +// Memory Protection of aperture[0-7] valid for Chip select0 +#define NAND_LOCK_APER_CHIPID2_0_CS0_SHIFT _MK_SHIFT_CONST(0) +#define NAND_LOCK_APER_CHIPID2_0_CS0_FIELD (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID2_0_CS0_SHIFT) +#define NAND_LOCK_APER_CHIPID2_0_CS0_RANGE 0:0 +#define NAND_LOCK_APER_CHIPID2_0_CS0_WOFFSET 0x0 +#define NAND_LOCK_APER_CHIPID2_0_CS0_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID2_0_CS0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID2_0_CS0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID2_0_CS0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID2_0_CS0_DISABLE _MK_ENUM_CONST(0) // // Memory Protection of aperture[0-7] not valid for Chip select0 + +#define NAND_LOCK_APER_CHIPID2_0_CS0_ENABLE _MK_ENUM_CONST(1) + + +// Register NAND_LOCK_APER_CHIPID3_0 +#define NAND_LOCK_APER_CHIPID3_0 _MK_ADDR_CONST(0xb8) +#define NAND_LOCK_APER_CHIPID3_0_SECURE 0x0 +#define NAND_LOCK_APER_CHIPID3_0_WORD_COUNT 0x1 +#define NAND_LOCK_APER_CHIPID3_0_RESET_VAL _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID3_0_RESET_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID3_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID3_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID3_0_READ_MASK _MK_MASK_CONST(0xff) +#define NAND_LOCK_APER_CHIPID3_0_WRITE_MASK _MK_MASK_CONST(0xff) +// Memory Protection of aperture[0-7] valid for Chip select7 +#define NAND_LOCK_APER_CHIPID3_0_CS7_SHIFT _MK_SHIFT_CONST(7) +#define NAND_LOCK_APER_CHIPID3_0_CS7_FIELD (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID3_0_CS7_SHIFT) +#define NAND_LOCK_APER_CHIPID3_0_CS7_RANGE 7:7 +#define NAND_LOCK_APER_CHIPID3_0_CS7_WOFFSET 0x0 +#define NAND_LOCK_APER_CHIPID3_0_CS7_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID3_0_CS7_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID3_0_CS7_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID3_0_CS7_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID3_0_CS7_DISABLE _MK_ENUM_CONST(0) // // Memory Protection of aperture[0-7] not valid for Chip select7 + +#define NAND_LOCK_APER_CHIPID3_0_CS7_ENABLE _MK_ENUM_CONST(1) + +// Memory Protection of aperture[0-7] valid for Chip select6 +#define NAND_LOCK_APER_CHIPID3_0_CS6_SHIFT _MK_SHIFT_CONST(6) +#define NAND_LOCK_APER_CHIPID3_0_CS6_FIELD (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID3_0_CS6_SHIFT) +#define NAND_LOCK_APER_CHIPID3_0_CS6_RANGE 6:6 +#define NAND_LOCK_APER_CHIPID3_0_CS6_WOFFSET 0x0 +#define NAND_LOCK_APER_CHIPID3_0_CS6_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID3_0_CS6_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID3_0_CS6_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID3_0_CS6_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID3_0_CS6_DISABLE _MK_ENUM_CONST(0) // // Memory Protection of aperture[0-7] not valid for Chip select6 + +#define NAND_LOCK_APER_CHIPID3_0_CS6_ENABLE _MK_ENUM_CONST(1) + +// Memory Protection of aperture[0-7] valid for Chip select5 +#define NAND_LOCK_APER_CHIPID3_0_CS5_SHIFT _MK_SHIFT_CONST(5) +#define NAND_LOCK_APER_CHIPID3_0_CS5_FIELD (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID3_0_CS5_SHIFT) +#define NAND_LOCK_APER_CHIPID3_0_CS5_RANGE 5:5 +#define NAND_LOCK_APER_CHIPID3_0_CS5_WOFFSET 0x0 +#define NAND_LOCK_APER_CHIPID3_0_CS5_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID3_0_CS5_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID3_0_CS5_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID3_0_CS5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID3_0_CS5_DISABLE _MK_ENUM_CONST(0) // // Memory Protection of aperture[0-7] not valid for Chip select5 + +#define NAND_LOCK_APER_CHIPID3_0_CS5_ENABLE _MK_ENUM_CONST(1) + +// Memory Protection of aperture[0-7] valid for Chip select4 +#define NAND_LOCK_APER_CHIPID3_0_CS4_SHIFT _MK_SHIFT_CONST(4) +#define NAND_LOCK_APER_CHIPID3_0_CS4_FIELD (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID3_0_CS4_SHIFT) +#define NAND_LOCK_APER_CHIPID3_0_CS4_RANGE 4:4 +#define NAND_LOCK_APER_CHIPID3_0_CS4_WOFFSET 0x0 +#define NAND_LOCK_APER_CHIPID3_0_CS4_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID3_0_CS4_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID3_0_CS4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID3_0_CS4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID3_0_CS4_DISABLE _MK_ENUM_CONST(0) // // Memory Protection of aperture[0-7] not valid for Chip select4 + +#define NAND_LOCK_APER_CHIPID3_0_CS4_ENABLE _MK_ENUM_CONST(1) + +// Memory Protection of aperture[0-7] valid for Chip select3 +#define NAND_LOCK_APER_CHIPID3_0_CS3_SHIFT _MK_SHIFT_CONST(3) +#define NAND_LOCK_APER_CHIPID3_0_CS3_FIELD (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID3_0_CS3_SHIFT) +#define NAND_LOCK_APER_CHIPID3_0_CS3_RANGE 3:3 +#define NAND_LOCK_APER_CHIPID3_0_CS3_WOFFSET 0x0 +#define NAND_LOCK_APER_CHIPID3_0_CS3_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID3_0_CS3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID3_0_CS3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID3_0_CS3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID3_0_CS3_DISABLE _MK_ENUM_CONST(0) // // Memory Protection of aperture[0-7] not valid for Chip select3 + +#define NAND_LOCK_APER_CHIPID3_0_CS3_ENABLE _MK_ENUM_CONST(1) + +// Memory Protection of aperture[0-7] valid for Chip select2 +#define NAND_LOCK_APER_CHIPID3_0_CS2_SHIFT _MK_SHIFT_CONST(2) +#define NAND_LOCK_APER_CHIPID3_0_CS2_FIELD (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID3_0_CS2_SHIFT) +#define NAND_LOCK_APER_CHIPID3_0_CS2_RANGE 2:2 +#define NAND_LOCK_APER_CHIPID3_0_CS2_WOFFSET 0x0 +#define NAND_LOCK_APER_CHIPID3_0_CS2_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID3_0_CS2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID3_0_CS2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID3_0_CS2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID3_0_CS2_DISABLE _MK_ENUM_CONST(0) // // Memory Protection of aperture[0-7] not valid for Chip select2 + +#define NAND_LOCK_APER_CHIPID3_0_CS2_ENABLE _MK_ENUM_CONST(1) + +// Memory Protection of aperture[0-7] valid for Chip select1 +#define NAND_LOCK_APER_CHIPID3_0_CS1_SHIFT _MK_SHIFT_CONST(1) +#define NAND_LOCK_APER_CHIPID3_0_CS1_FIELD (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID3_0_CS1_SHIFT) +#define NAND_LOCK_APER_CHIPID3_0_CS1_RANGE 1:1 +#define NAND_LOCK_APER_CHIPID3_0_CS1_WOFFSET 0x0 +#define NAND_LOCK_APER_CHIPID3_0_CS1_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID3_0_CS1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID3_0_CS1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID3_0_CS1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID3_0_CS1_DISABLE _MK_ENUM_CONST(0) // // Memory Protection of aperture[0-7] not valid for Chip select1 + +#define NAND_LOCK_APER_CHIPID3_0_CS1_ENABLE _MK_ENUM_CONST(1) + +// Memory Protection of aperture[0-7] valid for Chip select0 +#define NAND_LOCK_APER_CHIPID3_0_CS0_SHIFT _MK_SHIFT_CONST(0) +#define NAND_LOCK_APER_CHIPID3_0_CS0_FIELD (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID3_0_CS0_SHIFT) +#define NAND_LOCK_APER_CHIPID3_0_CS0_RANGE 0:0 +#define NAND_LOCK_APER_CHIPID3_0_CS0_WOFFSET 0x0 +#define NAND_LOCK_APER_CHIPID3_0_CS0_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID3_0_CS0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID3_0_CS0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID3_0_CS0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID3_0_CS0_DISABLE _MK_ENUM_CONST(0) // // Memory Protection of aperture[0-7] not valid for Chip select0 + +#define NAND_LOCK_APER_CHIPID3_0_CS0_ENABLE _MK_ENUM_CONST(1) + + +// Register NAND_LOCK_APER_CHIPID4_0 +#define NAND_LOCK_APER_CHIPID4_0 _MK_ADDR_CONST(0xbc) +#define NAND_LOCK_APER_CHIPID4_0_SECURE 0x0 +#define NAND_LOCK_APER_CHIPID4_0_WORD_COUNT 0x1 +#define NAND_LOCK_APER_CHIPID4_0_RESET_VAL _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID4_0_RESET_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID4_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID4_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID4_0_READ_MASK _MK_MASK_CONST(0xff) +#define NAND_LOCK_APER_CHIPID4_0_WRITE_MASK _MK_MASK_CONST(0xff) +// Memory Protection of aperture[0-7] valid for Chip select7 +#define NAND_LOCK_APER_CHIPID4_0_CS7_SHIFT _MK_SHIFT_CONST(7) +#define NAND_LOCK_APER_CHIPID4_0_CS7_FIELD (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID4_0_CS7_SHIFT) +#define NAND_LOCK_APER_CHIPID4_0_CS7_RANGE 7:7 +#define NAND_LOCK_APER_CHIPID4_0_CS7_WOFFSET 0x0 +#define NAND_LOCK_APER_CHIPID4_0_CS7_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID4_0_CS7_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID4_0_CS7_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID4_0_CS7_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID4_0_CS7_DISABLE _MK_ENUM_CONST(0) // // Memory Protection of aperture[0-7] not valid for Chip select7 + +#define NAND_LOCK_APER_CHIPID4_0_CS7_ENABLE _MK_ENUM_CONST(1) + +// Memory Protection of aperture[0-7] valid for Chip select6 +#define NAND_LOCK_APER_CHIPID4_0_CS6_SHIFT _MK_SHIFT_CONST(6) +#define NAND_LOCK_APER_CHIPID4_0_CS6_FIELD (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID4_0_CS6_SHIFT) +#define NAND_LOCK_APER_CHIPID4_0_CS6_RANGE 6:6 +#define NAND_LOCK_APER_CHIPID4_0_CS6_WOFFSET 0x0 +#define NAND_LOCK_APER_CHIPID4_0_CS6_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID4_0_CS6_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID4_0_CS6_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID4_0_CS6_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID4_0_CS6_DISABLE _MK_ENUM_CONST(0) // // Memory Protection of aperture[0-7] not valid for Chip select6 + +#define NAND_LOCK_APER_CHIPID4_0_CS6_ENABLE _MK_ENUM_CONST(1) + +// Memory Protection of aperture[0-7] valid for Chip select5 +#define NAND_LOCK_APER_CHIPID4_0_CS5_SHIFT _MK_SHIFT_CONST(5) +#define NAND_LOCK_APER_CHIPID4_0_CS5_FIELD (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID4_0_CS5_SHIFT) +#define NAND_LOCK_APER_CHIPID4_0_CS5_RANGE 5:5 +#define NAND_LOCK_APER_CHIPID4_0_CS5_WOFFSET 0x0 +#define NAND_LOCK_APER_CHIPID4_0_CS5_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID4_0_CS5_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID4_0_CS5_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID4_0_CS5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID4_0_CS5_DISABLE _MK_ENUM_CONST(0) // // Memory Protection of aperture[0-7] not valid for Chip select5 + +#define NAND_LOCK_APER_CHIPID4_0_CS5_ENABLE _MK_ENUM_CONST(1) + +// Memory Protection of aperture[0-7] valid for Chip select4 +#define NAND_LOCK_APER_CHIPID4_0_CS4_SHIFT _MK_SHIFT_CONST(4) +#define NAND_LOCK_APER_CHIPID4_0_CS4_FIELD (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID4_0_CS4_SHIFT) +#define NAND_LOCK_APER_CHIPID4_0_CS4_RANGE 4:4 +#define NAND_LOCK_APER_CHIPID4_0_CS4_WOFFSET 0x0 +#define NAND_LOCK_APER_CHIPID4_0_CS4_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID4_0_CS4_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID4_0_CS4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID4_0_CS4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID4_0_CS4_DISABLE _MK_ENUM_CONST(0) // // Memory Protection of aperture[0-7] not valid for Chip select4 + +#define NAND_LOCK_APER_CHIPID4_0_CS4_ENABLE _MK_ENUM_CONST(1) + +// Memory Protection of aperture[0-7] valid for Chip select3 +#define NAND_LOCK_APER_CHIPID4_0_CS3_SHIFT _MK_SHIFT_CONST(3) +#define NAND_LOCK_APER_CHIPID4_0_CS3_FIELD (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID4_0_CS3_SHIFT) +#define NAND_LOCK_APER_CHIPID4_0_CS3_RANGE 3:3 +#define NAND_LOCK_APER_CHIPID4_0_CS3_WOFFSET 0x0 +#define NAND_LOCK_APER_CHIPID4_0_CS3_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID4_0_CS3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID4_0_CS3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID4_0_CS3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID4_0_CS3_DISABLE _MK_ENUM_CONST(0) // // Memory Protection of aperture[0-7] not valid for Chip select3 + +#define NAND_LOCK_APER_CHIPID4_0_CS3_ENABLE _MK_ENUM_CONST(1) + +// Memory Protection of aperture[0-7] valid for Chip select2 +#define NAND_LOCK_APER_CHIPID4_0_CS2_SHIFT _MK_SHIFT_CONST(2) +#define NAND_LOCK_APER_CHIPID4_0_CS2_FIELD (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID4_0_CS2_SHIFT) +#define NAND_LOCK_APER_CHIPID4_0_CS2_RANGE 2:2 +#define NAND_LOCK_APER_CHIPID4_0_CS2_WOFFSET 0x0 +#define NAND_LOCK_APER_CHIPID4_0_CS2_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID4_0_CS2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID4_0_CS2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID4_0_CS2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID4_0_CS2_DISABLE _MK_ENUM_CONST(0) // // Memory Protection of aperture[0-7] not valid for Chip select2 + +#define NAND_LOCK_APER_CHIPID4_0_CS2_ENABLE _MK_ENUM_CONST(1) + +// Memory Protection of aperture[0-7] valid for Chip select1 +#define NAND_LOCK_APER_CHIPID4_0_CS1_SHIFT _MK_SHIFT_CONST(1) +#define NAND_LOCK_APER_CHIPID4_0_CS1_FIELD (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID4_0_CS1_SHIFT) +#define NAND_LOCK_APER_CHIPID4_0_CS1_RANGE 1:1 +#define NAND_LOCK_APER_CHIPID4_0_CS1_WOFFSET 0x0 +#define NAND_LOCK_APER_CHIPID4_0_CS1_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID4_0_CS1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID4_0_CS1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID4_0_CS1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID4_0_CS1_DISABLE _MK_ENUM_CONST(0) // // Memory Protection of aperture[0-7] not valid for Chip select1 + +#define NAND_LOCK_APER_CHIPID4_0_CS1_ENABLE _MK_ENUM_CONST(1) + +// Memory Protection of aperture[0-7] valid for Chip select0 +#define NAND_LOCK_APER_CHIPID4_0_CS0_SHIFT _MK_SHIFT_CONST(0) +#define NAND_LOCK_APER_CHIPID4_0_CS0_FIELD (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID4_0_CS0_SHIFT) +#define NAND_LOCK_APER_CHIPID4_0_CS0_RANGE 0:0 +#define NAND_LOCK_APER_CHIPID4_0_CS0_WOFFSET 0x0 +#define NAND_LOCK_APER_CHIPID4_0_CS0_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID4_0_CS0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID4_0_CS0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID4_0_CS0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID4_0_CS0_DISABLE _MK_ENUM_CONST(0) // // Memory Protection of aperture[0-7] not valid for Chip select0 + +#define NAND_LOCK_APER_CHIPID4_0_CS0_ENABLE _MK_ENUM_CONST(1) + + +// Register NAND_LOCK_APER_CHIPID5_0 +#define NAND_LOCK_APER_CHIPID5_0 _MK_ADDR_CONST(0xc0) +#define NAND_LOCK_APER_CHIPID5_0_SECURE 0x0 +#define NAND_LOCK_APER_CHIPID5_0_WORD_COUNT 0x1 +#define NAND_LOCK_APER_CHIPID5_0_RESET_VAL _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID5_0_RESET_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID5_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID5_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID5_0_READ_MASK _MK_MASK_CONST(0xff) +#define NAND_LOCK_APER_CHIPID5_0_WRITE_MASK _MK_MASK_CONST(0xff) +// Memory Protection of aperture[0-7] valid for Chip select7 +#define NAND_LOCK_APER_CHIPID5_0_CS7_SHIFT _MK_SHIFT_CONST(7) +#define NAND_LOCK_APER_CHIPID5_0_CS7_FIELD (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID5_0_CS7_SHIFT) +#define NAND_LOCK_APER_CHIPID5_0_CS7_RANGE 7:7 +#define NAND_LOCK_APER_CHIPID5_0_CS7_WOFFSET 0x0 +#define NAND_LOCK_APER_CHIPID5_0_CS7_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID5_0_CS7_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID5_0_CS7_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID5_0_CS7_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID5_0_CS7_DISABLE _MK_ENUM_CONST(0) // // Memory Protection of aperture[0-7] not valid for Chip select7 + +#define NAND_LOCK_APER_CHIPID5_0_CS7_ENABLE _MK_ENUM_CONST(1) + +// Memory Protection of aperture[0-7] valid for Chip select6 +#define NAND_LOCK_APER_CHIPID5_0_CS6_SHIFT _MK_SHIFT_CONST(6) +#define NAND_LOCK_APER_CHIPID5_0_CS6_FIELD (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID5_0_CS6_SHIFT) +#define NAND_LOCK_APER_CHIPID5_0_CS6_RANGE 6:6 +#define NAND_LOCK_APER_CHIPID5_0_CS6_WOFFSET 0x0 +#define NAND_LOCK_APER_CHIPID5_0_CS6_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID5_0_CS6_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID5_0_CS6_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID5_0_CS6_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID5_0_CS6_DISABLE _MK_ENUM_CONST(0) // // Memory Protection of aperture[0-7] not valid for Chip select6 + +#define NAND_LOCK_APER_CHIPID5_0_CS6_ENABLE _MK_ENUM_CONST(1) + +// Memory Protection of aperture[0-7] valid for Chip select5 +#define NAND_LOCK_APER_CHIPID5_0_CS5_SHIFT _MK_SHIFT_CONST(5) +#define NAND_LOCK_APER_CHIPID5_0_CS5_FIELD (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID5_0_CS5_SHIFT) +#define NAND_LOCK_APER_CHIPID5_0_CS5_RANGE 5:5 +#define NAND_LOCK_APER_CHIPID5_0_CS5_WOFFSET 0x0 +#define NAND_LOCK_APER_CHIPID5_0_CS5_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID5_0_CS5_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID5_0_CS5_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID5_0_CS5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID5_0_CS5_DISABLE _MK_ENUM_CONST(0) // // Memory Protection of aperture[0-7] not valid for Chip select5 + +#define NAND_LOCK_APER_CHIPID5_0_CS5_ENABLE _MK_ENUM_CONST(1) + +// Memory Protection of aperture[0-7] valid for Chip select4 +#define NAND_LOCK_APER_CHIPID5_0_CS4_SHIFT _MK_SHIFT_CONST(4) +#define NAND_LOCK_APER_CHIPID5_0_CS4_FIELD (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID5_0_CS4_SHIFT) +#define NAND_LOCK_APER_CHIPID5_0_CS4_RANGE 4:4 +#define NAND_LOCK_APER_CHIPID5_0_CS4_WOFFSET 0x0 +#define NAND_LOCK_APER_CHIPID5_0_CS4_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID5_0_CS4_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID5_0_CS4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID5_0_CS4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID5_0_CS4_DISABLE _MK_ENUM_CONST(0) // // Memory Protection of aperture[0-7] not valid for Chip select4 + +#define NAND_LOCK_APER_CHIPID5_0_CS4_ENABLE _MK_ENUM_CONST(1) + +// Memory Protection of aperture[0-7] valid for Chip select3 +#define NAND_LOCK_APER_CHIPID5_0_CS3_SHIFT _MK_SHIFT_CONST(3) +#define NAND_LOCK_APER_CHIPID5_0_CS3_FIELD (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID5_0_CS3_SHIFT) +#define NAND_LOCK_APER_CHIPID5_0_CS3_RANGE 3:3 +#define NAND_LOCK_APER_CHIPID5_0_CS3_WOFFSET 0x0 +#define NAND_LOCK_APER_CHIPID5_0_CS3_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID5_0_CS3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID5_0_CS3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID5_0_CS3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID5_0_CS3_DISABLE _MK_ENUM_CONST(0) // // Memory Protection of aperture[0-7] not valid for Chip select3 + +#define NAND_LOCK_APER_CHIPID5_0_CS3_ENABLE _MK_ENUM_CONST(1) + +// Memory Protection of aperture[0-7] valid for Chip select2 +#define NAND_LOCK_APER_CHIPID5_0_CS2_SHIFT _MK_SHIFT_CONST(2) +#define NAND_LOCK_APER_CHIPID5_0_CS2_FIELD (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID5_0_CS2_SHIFT) +#define NAND_LOCK_APER_CHIPID5_0_CS2_RANGE 2:2 +#define NAND_LOCK_APER_CHIPID5_0_CS2_WOFFSET 0x0 +#define NAND_LOCK_APER_CHIPID5_0_CS2_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID5_0_CS2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID5_0_CS2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID5_0_CS2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID5_0_CS2_DISABLE _MK_ENUM_CONST(0) // // Memory Protection of aperture[0-7] not valid for Chip select2 + +#define NAND_LOCK_APER_CHIPID5_0_CS2_ENABLE _MK_ENUM_CONST(1) + +// Memory Protection of aperture[0-7] valid for Chip select1 +#define NAND_LOCK_APER_CHIPID5_0_CS1_SHIFT _MK_SHIFT_CONST(1) +#define NAND_LOCK_APER_CHIPID5_0_CS1_FIELD (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID5_0_CS1_SHIFT) +#define NAND_LOCK_APER_CHIPID5_0_CS1_RANGE 1:1 +#define NAND_LOCK_APER_CHIPID5_0_CS1_WOFFSET 0x0 +#define NAND_LOCK_APER_CHIPID5_0_CS1_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID5_0_CS1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID5_0_CS1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID5_0_CS1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID5_0_CS1_DISABLE _MK_ENUM_CONST(0) // // Memory Protection of aperture[0-7] not valid for Chip select1 + +#define NAND_LOCK_APER_CHIPID5_0_CS1_ENABLE _MK_ENUM_CONST(1) + +// Memory Protection of aperture[0-7] valid for Chip select0 +#define NAND_LOCK_APER_CHIPID5_0_CS0_SHIFT _MK_SHIFT_CONST(0) +#define NAND_LOCK_APER_CHIPID5_0_CS0_FIELD (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID5_0_CS0_SHIFT) +#define NAND_LOCK_APER_CHIPID5_0_CS0_RANGE 0:0 +#define NAND_LOCK_APER_CHIPID5_0_CS0_WOFFSET 0x0 +#define NAND_LOCK_APER_CHIPID5_0_CS0_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID5_0_CS0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID5_0_CS0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID5_0_CS0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID5_0_CS0_DISABLE _MK_ENUM_CONST(0) // // Memory Protection of aperture[0-7] not valid for Chip select0 + +#define NAND_LOCK_APER_CHIPID5_0_CS0_ENABLE _MK_ENUM_CONST(1) + + +// Register NAND_LOCK_APER_CHIPID6_0 +#define NAND_LOCK_APER_CHIPID6_0 _MK_ADDR_CONST(0xc4) +#define NAND_LOCK_APER_CHIPID6_0_SECURE 0x0 +#define NAND_LOCK_APER_CHIPID6_0_WORD_COUNT 0x1 +#define NAND_LOCK_APER_CHIPID6_0_RESET_VAL _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID6_0_RESET_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID6_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID6_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID6_0_READ_MASK _MK_MASK_CONST(0xff) +#define NAND_LOCK_APER_CHIPID6_0_WRITE_MASK _MK_MASK_CONST(0xff) +// Memory Protection of aperture[0-7] valid for Chip select7 +#define NAND_LOCK_APER_CHIPID6_0_CS7_SHIFT _MK_SHIFT_CONST(7) +#define NAND_LOCK_APER_CHIPID6_0_CS7_FIELD (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID6_0_CS7_SHIFT) +#define NAND_LOCK_APER_CHIPID6_0_CS7_RANGE 7:7 +#define NAND_LOCK_APER_CHIPID6_0_CS7_WOFFSET 0x0 +#define NAND_LOCK_APER_CHIPID6_0_CS7_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID6_0_CS7_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID6_0_CS7_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID6_0_CS7_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID6_0_CS7_DISABLE _MK_ENUM_CONST(0) // // Memory Protection of aperture[0-7] not valid for Chip select7 + +#define NAND_LOCK_APER_CHIPID6_0_CS7_ENABLE _MK_ENUM_CONST(1) + +// Memory Protection of aperture[0-7] valid for Chip select6 +#define NAND_LOCK_APER_CHIPID6_0_CS6_SHIFT _MK_SHIFT_CONST(6) +#define NAND_LOCK_APER_CHIPID6_0_CS6_FIELD (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID6_0_CS6_SHIFT) +#define NAND_LOCK_APER_CHIPID6_0_CS6_RANGE 6:6 +#define NAND_LOCK_APER_CHIPID6_0_CS6_WOFFSET 0x0 +#define NAND_LOCK_APER_CHIPID6_0_CS6_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID6_0_CS6_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID6_0_CS6_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID6_0_CS6_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID6_0_CS6_DISABLE _MK_ENUM_CONST(0) // // Memory Protection of aperture[0-7] not valid for Chip select6 + +#define NAND_LOCK_APER_CHIPID6_0_CS6_ENABLE _MK_ENUM_CONST(1) + +// Memory Protection of aperture[0-7] valid for Chip select5 +#define NAND_LOCK_APER_CHIPID6_0_CS5_SHIFT _MK_SHIFT_CONST(5) +#define NAND_LOCK_APER_CHIPID6_0_CS5_FIELD (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID6_0_CS5_SHIFT) +#define NAND_LOCK_APER_CHIPID6_0_CS5_RANGE 5:5 +#define NAND_LOCK_APER_CHIPID6_0_CS5_WOFFSET 0x0 +#define NAND_LOCK_APER_CHIPID6_0_CS5_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID6_0_CS5_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID6_0_CS5_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID6_0_CS5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID6_0_CS5_DISABLE _MK_ENUM_CONST(0) // // Memory Protection of aperture[0-7] not valid for Chip select5 + +#define NAND_LOCK_APER_CHIPID6_0_CS5_ENABLE _MK_ENUM_CONST(1) + +// Memory Protection of aperture[0-7] valid for Chip select4 +#define NAND_LOCK_APER_CHIPID6_0_CS4_SHIFT _MK_SHIFT_CONST(4) +#define NAND_LOCK_APER_CHIPID6_0_CS4_FIELD (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID6_0_CS4_SHIFT) +#define NAND_LOCK_APER_CHIPID6_0_CS4_RANGE 4:4 +#define NAND_LOCK_APER_CHIPID6_0_CS4_WOFFSET 0x0 +#define NAND_LOCK_APER_CHIPID6_0_CS4_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID6_0_CS4_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID6_0_CS4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID6_0_CS4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID6_0_CS4_DISABLE _MK_ENUM_CONST(0) // // Memory Protection of aperture[0-7] not valid for Chip select4 + +#define NAND_LOCK_APER_CHIPID6_0_CS4_ENABLE _MK_ENUM_CONST(1) + +// Memory Protection of aperture[0-7] valid for Chip select3 +#define NAND_LOCK_APER_CHIPID6_0_CS3_SHIFT _MK_SHIFT_CONST(3) +#define NAND_LOCK_APER_CHIPID6_0_CS3_FIELD (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID6_0_CS3_SHIFT) +#define NAND_LOCK_APER_CHIPID6_0_CS3_RANGE 3:3 +#define NAND_LOCK_APER_CHIPID6_0_CS3_WOFFSET 0x0 +#define NAND_LOCK_APER_CHIPID6_0_CS3_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID6_0_CS3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID6_0_CS3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID6_0_CS3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID6_0_CS3_DISABLE _MK_ENUM_CONST(0) // // Memory Protection of aperture[0-7] not valid for Chip select3 + +#define NAND_LOCK_APER_CHIPID6_0_CS3_ENABLE _MK_ENUM_CONST(1) + +// Memory Protection of aperture[0-7] valid for Chip select2 +#define NAND_LOCK_APER_CHIPID6_0_CS2_SHIFT _MK_SHIFT_CONST(2) +#define NAND_LOCK_APER_CHIPID6_0_CS2_FIELD (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID6_0_CS2_SHIFT) +#define NAND_LOCK_APER_CHIPID6_0_CS2_RANGE 2:2 +#define NAND_LOCK_APER_CHIPID6_0_CS2_WOFFSET 0x0 +#define NAND_LOCK_APER_CHIPID6_0_CS2_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID6_0_CS2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID6_0_CS2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID6_0_CS2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID6_0_CS2_DISABLE _MK_ENUM_CONST(0) // // Memory Protection of aperture[0-7] not valid for Chip select2 + +#define NAND_LOCK_APER_CHIPID6_0_CS2_ENABLE _MK_ENUM_CONST(1) + +// Memory Protection of aperture[0-7] valid for Chip select1 +#define NAND_LOCK_APER_CHIPID6_0_CS1_SHIFT _MK_SHIFT_CONST(1) +#define NAND_LOCK_APER_CHIPID6_0_CS1_FIELD (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID6_0_CS1_SHIFT) +#define NAND_LOCK_APER_CHIPID6_0_CS1_RANGE 1:1 +#define NAND_LOCK_APER_CHIPID6_0_CS1_WOFFSET 0x0 +#define NAND_LOCK_APER_CHIPID6_0_CS1_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID6_0_CS1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID6_0_CS1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID6_0_CS1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID6_0_CS1_DISABLE _MK_ENUM_CONST(0) // // Memory Protection of aperture[0-7] not valid for Chip select1 + +#define NAND_LOCK_APER_CHIPID6_0_CS1_ENABLE _MK_ENUM_CONST(1) + +// Memory Protection of aperture[0-7] valid for Chip select0 +#define NAND_LOCK_APER_CHIPID6_0_CS0_SHIFT _MK_SHIFT_CONST(0) +#define NAND_LOCK_APER_CHIPID6_0_CS0_FIELD (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID6_0_CS0_SHIFT) +#define NAND_LOCK_APER_CHIPID6_0_CS0_RANGE 0:0 +#define NAND_LOCK_APER_CHIPID6_0_CS0_WOFFSET 0x0 +#define NAND_LOCK_APER_CHIPID6_0_CS0_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID6_0_CS0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID6_0_CS0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID6_0_CS0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID6_0_CS0_DISABLE _MK_ENUM_CONST(0) // // Memory Protection of aperture[0-7] not valid for Chip select0 + +#define NAND_LOCK_APER_CHIPID6_0_CS0_ENABLE _MK_ENUM_CONST(1) + + +// Register NAND_LOCK_APER_CHIPID7_0 +#define NAND_LOCK_APER_CHIPID7_0 _MK_ADDR_CONST(0xc8) +#define NAND_LOCK_APER_CHIPID7_0_SECURE 0x0 +#define NAND_LOCK_APER_CHIPID7_0_WORD_COUNT 0x1 +#define NAND_LOCK_APER_CHIPID7_0_RESET_VAL _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID7_0_RESET_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID7_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID7_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID7_0_READ_MASK _MK_MASK_CONST(0xff) +#define NAND_LOCK_APER_CHIPID7_0_WRITE_MASK _MK_MASK_CONST(0xff) +// Memory Protection of aperture[0-7] valid for Chip select7 +#define NAND_LOCK_APER_CHIPID7_0_CS7_SHIFT _MK_SHIFT_CONST(7) +#define NAND_LOCK_APER_CHIPID7_0_CS7_FIELD (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID7_0_CS7_SHIFT) +#define NAND_LOCK_APER_CHIPID7_0_CS7_RANGE 7:7 +#define NAND_LOCK_APER_CHIPID7_0_CS7_WOFFSET 0x0 +#define NAND_LOCK_APER_CHIPID7_0_CS7_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID7_0_CS7_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID7_0_CS7_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID7_0_CS7_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID7_0_CS7_DISABLE _MK_ENUM_CONST(0) // // Memory Protection of aperture[0-7] not valid for Chip select7 + +#define NAND_LOCK_APER_CHIPID7_0_CS7_ENABLE _MK_ENUM_CONST(1) + +// Memory Protection of aperture[0-7] valid for Chip select6 +#define NAND_LOCK_APER_CHIPID7_0_CS6_SHIFT _MK_SHIFT_CONST(6) +#define NAND_LOCK_APER_CHIPID7_0_CS6_FIELD (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID7_0_CS6_SHIFT) +#define NAND_LOCK_APER_CHIPID7_0_CS6_RANGE 6:6 +#define NAND_LOCK_APER_CHIPID7_0_CS6_WOFFSET 0x0 +#define NAND_LOCK_APER_CHIPID7_0_CS6_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID7_0_CS6_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID7_0_CS6_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID7_0_CS6_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID7_0_CS6_DISABLE _MK_ENUM_CONST(0) // // Memory Protection of aperture[0-7] not valid for Chip select6 + +#define NAND_LOCK_APER_CHIPID7_0_CS6_ENABLE _MK_ENUM_CONST(1) + +// Memory Protection of aperture[0-7] valid for Chip select5 +#define NAND_LOCK_APER_CHIPID7_0_CS5_SHIFT _MK_SHIFT_CONST(5) +#define NAND_LOCK_APER_CHIPID7_0_CS5_FIELD (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID7_0_CS5_SHIFT) +#define NAND_LOCK_APER_CHIPID7_0_CS5_RANGE 5:5 +#define NAND_LOCK_APER_CHIPID7_0_CS5_WOFFSET 0x0 +#define NAND_LOCK_APER_CHIPID7_0_CS5_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID7_0_CS5_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID7_0_CS5_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID7_0_CS5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID7_0_CS5_DISABLE _MK_ENUM_CONST(0) // // Memory Protection of aperture[0-7] not valid for Chip select5 + +#define NAND_LOCK_APER_CHIPID7_0_CS5_ENABLE _MK_ENUM_CONST(1) + +// Memory Protection of aperture[0-7] valid for Chip select4 +#define NAND_LOCK_APER_CHIPID7_0_CS4_SHIFT _MK_SHIFT_CONST(4) +#define NAND_LOCK_APER_CHIPID7_0_CS4_FIELD (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID7_0_CS4_SHIFT) +#define NAND_LOCK_APER_CHIPID7_0_CS4_RANGE 4:4 +#define NAND_LOCK_APER_CHIPID7_0_CS4_WOFFSET 0x0 +#define NAND_LOCK_APER_CHIPID7_0_CS4_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID7_0_CS4_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID7_0_CS4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID7_0_CS4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID7_0_CS4_DISABLE _MK_ENUM_CONST(0) // // Memory Protection of aperture[0-7] not valid for Chip select4 + +#define NAND_LOCK_APER_CHIPID7_0_CS4_ENABLE _MK_ENUM_CONST(1) + +// Memory Protection of aperture[0-7] valid for Chip select3 +#define NAND_LOCK_APER_CHIPID7_0_CS3_SHIFT _MK_SHIFT_CONST(3) +#define NAND_LOCK_APER_CHIPID7_0_CS3_FIELD (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID7_0_CS3_SHIFT) +#define NAND_LOCK_APER_CHIPID7_0_CS3_RANGE 3:3 +#define NAND_LOCK_APER_CHIPID7_0_CS3_WOFFSET 0x0 +#define NAND_LOCK_APER_CHIPID7_0_CS3_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID7_0_CS3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID7_0_CS3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID7_0_CS3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID7_0_CS3_DISABLE _MK_ENUM_CONST(0) // // Memory Protection of aperture[0-7] not valid for Chip select3 + +#define NAND_LOCK_APER_CHIPID7_0_CS3_ENABLE _MK_ENUM_CONST(1) + +// Memory Protection of aperture[0-7] valid for Chip select2 +#define NAND_LOCK_APER_CHIPID7_0_CS2_SHIFT _MK_SHIFT_CONST(2) +#define NAND_LOCK_APER_CHIPID7_0_CS2_FIELD (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID7_0_CS2_SHIFT) +#define NAND_LOCK_APER_CHIPID7_0_CS2_RANGE 2:2 +#define NAND_LOCK_APER_CHIPID7_0_CS2_WOFFSET 0x0 +#define NAND_LOCK_APER_CHIPID7_0_CS2_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID7_0_CS2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID7_0_CS2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID7_0_CS2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID7_0_CS2_DISABLE _MK_ENUM_CONST(0) // // Memory Protection of aperture[0-7] not valid for Chip select2 + +#define NAND_LOCK_APER_CHIPID7_0_CS2_ENABLE _MK_ENUM_CONST(1) + +// Memory Protection of aperture[0-7] valid for Chip select1 +#define NAND_LOCK_APER_CHIPID7_0_CS1_SHIFT _MK_SHIFT_CONST(1) +#define NAND_LOCK_APER_CHIPID7_0_CS1_FIELD (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID7_0_CS1_SHIFT) +#define NAND_LOCK_APER_CHIPID7_0_CS1_RANGE 1:1 +#define NAND_LOCK_APER_CHIPID7_0_CS1_WOFFSET 0x0 +#define NAND_LOCK_APER_CHIPID7_0_CS1_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID7_0_CS1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID7_0_CS1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID7_0_CS1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID7_0_CS1_DISABLE _MK_ENUM_CONST(0) // // Memory Protection of aperture[0-7] not valid for Chip select1 + +#define NAND_LOCK_APER_CHIPID7_0_CS1_ENABLE _MK_ENUM_CONST(1) + +// Memory Protection of aperture[0-7] valid for Chip select0 +#define NAND_LOCK_APER_CHIPID7_0_CS0_SHIFT _MK_SHIFT_CONST(0) +#define NAND_LOCK_APER_CHIPID7_0_CS0_FIELD (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID7_0_CS0_SHIFT) +#define NAND_LOCK_APER_CHIPID7_0_CS0_RANGE 0:0 +#define NAND_LOCK_APER_CHIPID7_0_CS0_WOFFSET 0x0 +#define NAND_LOCK_APER_CHIPID7_0_CS0_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID7_0_CS0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID7_0_CS0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID7_0_CS0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_LOCK_APER_CHIPID7_0_CS0_DISABLE _MK_ENUM_CONST(0) // // Memory Protection of aperture[0-7] not valid for Chip select0 + +#define NAND_LOCK_APER_CHIPID7_0_CS0_ENABLE _MK_ENUM_CONST(1) + + +// Register NAND_BCH_CONFIG_0 +#define NAND_BCH_CONFIG_0 _MK_ADDR_CONST(0xcc) +#define NAND_BCH_CONFIG_0_SECURE 0x0 +#define NAND_BCH_CONFIG_0_WORD_COUNT 0x1 +#define NAND_BCH_CONFIG_0_RESET_VAL _MK_MASK_CONST(0x0) +#define NAND_BCH_CONFIG_0_RESET_MASK _MK_MASK_CONST(0x31) +#define NAND_BCH_CONFIG_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define NAND_BCH_CONFIG_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_BCH_CONFIG_0_READ_MASK _MK_MASK_CONST(0x31) +#define NAND_BCH_CONFIG_0_WRITE_MASK _MK_MASK_CONST(0x31) +// BCH error correction strength selection 16 single bit random errors per sector +#define NAND_BCH_CONFIG_0_BCH_TVALUE_SHIFT _MK_SHIFT_CONST(4) +#define NAND_BCH_CONFIG_0_BCH_TVALUE_FIELD (_MK_MASK_CONST(0x3) << NAND_BCH_CONFIG_0_BCH_TVALUE_SHIFT) +#define NAND_BCH_CONFIG_0_BCH_TVALUE_RANGE 5:4 +#define NAND_BCH_CONFIG_0_BCH_TVALUE_WOFFSET 0x0 +#define NAND_BCH_CONFIG_0_BCH_TVALUE_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_BCH_CONFIG_0_BCH_TVALUE_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define NAND_BCH_CONFIG_0_BCH_TVALUE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_BCH_CONFIG_0_BCH_TVALUE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_BCH_CONFIG_0_BCH_TVALUE_BCH_TVAL4 _MK_ENUM_CONST(0) // // 4 single bit random errors per sector + +#define NAND_BCH_CONFIG_0_BCH_TVALUE_BCH_TVAL8 _MK_ENUM_CONST(1) // // 8 single bit random errors per sector + +#define NAND_BCH_CONFIG_0_BCH_TVALUE_BCH_TVAL14 _MK_ENUM_CONST(2) // // 14 single bit random errors per sector + +#define NAND_BCH_CONFIG_0_BCH_TVALUE_BCH_TVAL16 _MK_ENUM_CONST(3) + +// BCH encoder & decoder is enabled +#define NAND_BCH_CONFIG_0_BCH_ECC_SHIFT _MK_SHIFT_CONST(0) +#define NAND_BCH_CONFIG_0_BCH_ECC_FIELD (_MK_MASK_CONST(0x1) << NAND_BCH_CONFIG_0_BCH_ECC_SHIFT) +#define NAND_BCH_CONFIG_0_BCH_ECC_RANGE 0:0 +#define NAND_BCH_CONFIG_0_BCH_ECC_WOFFSET 0x0 +#define NAND_BCH_CONFIG_0_BCH_ECC_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_BCH_CONFIG_0_BCH_ECC_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define NAND_BCH_CONFIG_0_BCH_ECC_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_BCH_CONFIG_0_BCH_ECC_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_BCH_CONFIG_0_BCH_ECC_DISABLE _MK_ENUM_CONST(0) // // BCH encoder & decoder is not enabled + +#define NAND_BCH_CONFIG_0_BCH_ECC_ENABLE _MK_ENUM_CONST(1) + + +// Register NAND_BCH_DEC_RESULT_0 +#define NAND_BCH_DEC_RESULT_0 _MK_ADDR_CONST(0xd0) +#define NAND_BCH_DEC_RESULT_0_SECURE 0x0 +#define NAND_BCH_DEC_RESULT_0_WORD_COUNT 0x1 +#define NAND_BCH_DEC_RESULT_0_RESET_VAL _MK_MASK_CONST(0x0) +#define NAND_BCH_DEC_RESULT_0_RESET_MASK _MK_MASK_CONST(0x0) +#define NAND_BCH_DEC_RESULT_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define NAND_BCH_DEC_RESULT_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_BCH_DEC_RESULT_0_READ_MASK _MK_MASK_CONST(0x1ff) +#define NAND_BCH_DEC_RESULT_0_WRITE_MASK _MK_MASK_CONST(0x0) +// 1 = Correctable OR Un-correctable errors occurred in the DMA transfer +// without regard to HW_ERR_CORRECTION feature is enabled or not. +// Use extended decode results in NAND_DEC_RESULT and NAND_DEC_STATUS_EXT +// to figure out further action for block replacement/wear leveling during +// file system management for s/w. +#define NAND_BCH_DEC_RESULT_0_CORRFAIL_ERR_SHIFT _MK_SHIFT_CONST(8) +#define NAND_BCH_DEC_RESULT_0_CORRFAIL_ERR_FIELD (_MK_MASK_CONST(0x1) << NAND_BCH_DEC_RESULT_0_CORRFAIL_ERR_SHIFT) +#define NAND_BCH_DEC_RESULT_0_CORRFAIL_ERR_RANGE 8:8 +#define NAND_BCH_DEC_RESULT_0_CORRFAIL_ERR_WOFFSET 0x0 +#define NAND_BCH_DEC_RESULT_0_CORRFAIL_ERR_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_BCH_DEC_RESULT_0_CORRFAIL_ERR_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_BCH_DEC_RESULT_0_CORRFAIL_ERR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_BCH_DEC_RESULT_0_CORRFAIL_ERR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// No. of pages resulted either in un-correctable or correctable errors +#define NAND_BCH_DEC_RESULT_0_PAGE_COUNT_SHIFT _MK_SHIFT_CONST(0) +#define NAND_BCH_DEC_RESULT_0_PAGE_COUNT_FIELD (_MK_MASK_CONST(0xff) << NAND_BCH_DEC_RESULT_0_PAGE_COUNT_SHIFT) +#define NAND_BCH_DEC_RESULT_0_PAGE_COUNT_RANGE 7:0 +#define NAND_BCH_DEC_RESULT_0_PAGE_COUNT_WOFFSET 0x0 +#define NAND_BCH_DEC_RESULT_0_PAGE_COUNT_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_BCH_DEC_RESULT_0_PAGE_COUNT_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_BCH_DEC_RESULT_0_PAGE_COUNT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_BCH_DEC_RESULT_0_PAGE_COUNT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register NAND_BCH_DEC_STATUS_BUF_0 +#define NAND_BCH_DEC_STATUS_BUF_0 _MK_ADDR_CONST(0xd4) +#define NAND_BCH_DEC_STATUS_BUF_0_SECURE 0x0 +#define NAND_BCH_DEC_STATUS_BUF_0_WORD_COUNT 0x1 +#define NAND_BCH_DEC_STATUS_BUF_0_RESET_VAL _MK_MASK_CONST(0x0) +#define NAND_BCH_DEC_STATUS_BUF_0_RESET_MASK _MK_MASK_CONST(0x0) +#define NAND_BCH_DEC_STATUS_BUF_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define NAND_BCH_DEC_STATUS_BUF_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_BCH_DEC_STATUS_BUF_0_READ_MASK _MK_MASK_CONST(0xffff7fff) +#define NAND_BCH_DEC_STATUS_BUF_0_WRITE_MASK _MK_MASK_CONST(0x0) +// Sector wise un-correctable error indicator +// Bit 31 = 1, sector 7 has un-correctable errors +// Bit 31 = 0, sector 7 has no un-correctable errors +// ... +// Bit 24 = 1, sector 0 has un-correctable errors +// Bit 24 = 0, sector 0 has no un-correctable errors +#define NAND_BCH_DEC_STATUS_BUF_0_FAIL_SEC_FLAG_SHIFT _MK_SHIFT_CONST(24) +#define NAND_BCH_DEC_STATUS_BUF_0_FAIL_SEC_FLAG_FIELD (_MK_MASK_CONST(0xff) << NAND_BCH_DEC_STATUS_BUF_0_FAIL_SEC_FLAG_SHIFT) +#define NAND_BCH_DEC_STATUS_BUF_0_FAIL_SEC_FLAG_RANGE 31:24 +#define NAND_BCH_DEC_STATUS_BUF_0_FAIL_SEC_FLAG_WOFFSET 0x0 +#define NAND_BCH_DEC_STATUS_BUF_0_FAIL_SEC_FLAG_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_BCH_DEC_STATUS_BUF_0_FAIL_SEC_FLAG_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_BCH_DEC_STATUS_BUF_0_FAIL_SEC_FLAG_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_BCH_DEC_STATUS_BUF_0_FAIL_SEC_FLAG_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// Sector wise correctable error indicator +// Bit 23 = 1, sector 7 has correctable errors +// Bit 23 = 0, sector 7 has no correctable errors +// ... +// Bit 16 = 1, sector 0 has correctable errors +// Bit 16 = 0, sector 0 has no correctable errors +#define NAND_BCH_DEC_STATUS_BUF_0_CORR_SEC_FLAG_SHIFT _MK_SHIFT_CONST(16) +#define NAND_BCH_DEC_STATUS_BUF_0_CORR_SEC_FLAG_FIELD (_MK_MASK_CONST(0xff) << NAND_BCH_DEC_STATUS_BUF_0_CORR_SEC_FLAG_SHIFT) +#define NAND_BCH_DEC_STATUS_BUF_0_CORR_SEC_FLAG_RANGE 23:16 +#define NAND_BCH_DEC_STATUS_BUF_0_CORR_SEC_FLAG_WOFFSET 0x0 +#define NAND_BCH_DEC_STATUS_BUF_0_CORR_SEC_FLAG_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_BCH_DEC_STATUS_BUF_0_CORR_SEC_FLAG_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_BCH_DEC_STATUS_BUF_0_CORR_SEC_FLAG_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_BCH_DEC_STATUS_BUF_0_CORR_SEC_FLAG_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// Spare area error decode resulted in un-correctable errors +// in case of RS/Hamming ECC selection. +// For BCH this field is not applicable. +#define NAND_BCH_DEC_STATUS_BUF_0_FAIL_TAG_SHIFT _MK_SHIFT_CONST(14) +#define NAND_BCH_DEC_STATUS_BUF_0_FAIL_TAG_FIELD (_MK_MASK_CONST(0x1) << NAND_BCH_DEC_STATUS_BUF_0_FAIL_TAG_SHIFT) +#define NAND_BCH_DEC_STATUS_BUF_0_FAIL_TAG_RANGE 14:14 +#define NAND_BCH_DEC_STATUS_BUF_0_FAIL_TAG_WOFFSET 0x0 +#define NAND_BCH_DEC_STATUS_BUF_0_FAIL_TAG_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_BCH_DEC_STATUS_BUF_0_FAIL_TAG_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_BCH_DEC_STATUS_BUF_0_FAIL_TAG_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_BCH_DEC_STATUS_BUF_0_FAIL_TAG_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// Spare area error decode resulted in correctable errors +// in case of RS/Hamming ECC selection. +// For BCH this field is not applicable. +#define NAND_BCH_DEC_STATUS_BUF_0_CORR_TAG_SHIFT _MK_SHIFT_CONST(13) +#define NAND_BCH_DEC_STATUS_BUF_0_CORR_TAG_FIELD (_MK_MASK_CONST(0x1) << NAND_BCH_DEC_STATUS_BUF_0_CORR_TAG_SHIFT) +#define NAND_BCH_DEC_STATUS_BUF_0_CORR_TAG_RANGE 13:13 +#define NAND_BCH_DEC_STATUS_BUF_0_CORR_TAG_WOFFSET 0x0 +#define NAND_BCH_DEC_STATUS_BUF_0_CORR_TAG_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_BCH_DEC_STATUS_BUF_0_CORR_TAG_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_BCH_DEC_STATUS_BUF_0_CORR_TAG_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_BCH_DEC_STATUS_BUF_0_CORR_TAG_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// Maximum no. of correctable errors occurred out of all sectors. +// For example of 2K page, if sector 0 has 2 correctable errors +// and sector3 has 4 errors MAX_ERR_CNT will reflect as 4 +#define NAND_BCH_DEC_STATUS_BUF_0_MAX_CORR_CNT_SHIFT _MK_SHIFT_CONST(8) +#define NAND_BCH_DEC_STATUS_BUF_0_MAX_CORR_CNT_FIELD (_MK_MASK_CONST(0x1f) << NAND_BCH_DEC_STATUS_BUF_0_MAX_CORR_CNT_SHIFT) +#define NAND_BCH_DEC_STATUS_BUF_0_MAX_CORR_CNT_RANGE 12:8 +#define NAND_BCH_DEC_STATUS_BUF_0_MAX_CORR_CNT_WOFFSET 0x0 +#define NAND_BCH_DEC_STATUS_BUF_0_MAX_CORR_CNT_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_BCH_DEC_STATUS_BUF_0_MAX_CORR_CNT_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_BCH_DEC_STATUS_BUF_0_MAX_CORR_CNT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_BCH_DEC_STATUS_BUF_0_MAX_CORR_CNT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +// Page number which resulted in either correctable/un-correctable errors +// 0 to 63 indicattion for 64 pages of DMA transfer. +#define NAND_BCH_DEC_STATUS_BUF_0_PAGE_NUMBER_SHIFT _MK_SHIFT_CONST(0) +#define NAND_BCH_DEC_STATUS_BUF_0_PAGE_NUMBER_FIELD (_MK_MASK_CONST(0xff) << NAND_BCH_DEC_STATUS_BUF_0_PAGE_NUMBER_SHIFT) +#define NAND_BCH_DEC_STATUS_BUF_0_PAGE_NUMBER_RANGE 7:0 +#define NAND_BCH_DEC_STATUS_BUF_0_PAGE_NUMBER_WOFFSET 0x0 +#define NAND_BCH_DEC_STATUS_BUF_0_PAGE_NUMBER_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_BCH_DEC_STATUS_BUF_0_PAGE_NUMBER_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define NAND_BCH_DEC_STATUS_BUF_0_PAGE_NUMBER_SW_DEFAULT _MK_MASK_CONST(0x0) +#define NAND_BCH_DEC_STATUS_BUF_0_PAGE_NUMBER_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Packet CMDQ_CMD +#define CMDQ_CMD_SIZE 32 + +// Pakcet ID +#define CMDQ_CMD_PKT_ID_SHIFT _MK_SHIFT_CONST(24) +#define CMDQ_CMD_PKT_ID_FIELD (_MK_MASK_CONST(0xff) << CMDQ_CMD_PKT_ID_SHIFT) +#define CMDQ_CMD_PKT_ID_RANGE _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(24) +#define CMDQ_CMD_PKT_ID_ROW 0 + +// not used range +#define CMDQ_CMD_RSVD_SHIFT _MK_SHIFT_CONST(14) +#define CMDQ_CMD_RSVD_FIELD (_MK_MASK_CONST(0x3ff) << CMDQ_CMD_RSVD_SHIFT) +#define CMDQ_CMD_RSVD_RANGE _MK_SHIFT_CONST(23):_MK_SHIFT_CONST(14) +#define CMDQ_CMD_RSVD_ROW 0 + +// ENABLE = NAND_COMMAND register requires update in this packet execution +#define CMDQ_CMD_COMMAND_SHIFT _MK_SHIFT_CONST(13) +#define CMDQ_CMD_COMMAND_FIELD (_MK_MASK_CONST(0x1) << CMDQ_CMD_COMMAND_SHIFT) +#define CMDQ_CMD_COMMAND_RANGE _MK_SHIFT_CONST(13):_MK_SHIFT_CONST(13) +#define CMDQ_CMD_COMMAND_ROW 0 +#define CMDQ_CMD_COMMAND_DISABLE _MK_ENUM_CONST(0) +#define CMDQ_CMD_COMMAND_ENABLE _MK_ENUM_CONST(1) + +// ENABLE = NAND_HWSTATUS_MASK register requires update in this packet execution +#define CMDQ_CMD_HWSTATUS_MASK_SHIFT _MK_SHIFT_CONST(12) +#define CMDQ_CMD_HWSTATUS_MASK_FIELD (_MK_MASK_CONST(0x1) << CMDQ_CMD_HWSTATUS_MASK_SHIFT) +#define CMDQ_CMD_HWSTATUS_MASK_RANGE _MK_SHIFT_CONST(12):_MK_SHIFT_CONST(12) +#define CMDQ_CMD_HWSTATUS_MASK_ROW 0 +#define CMDQ_CMD_HWSTATUS_MASK_DISABLE _MK_ENUM_CONST(0) +#define CMDQ_CMD_HWSTATUS_MASK_ENABLE _MK_ENUM_CONST(1) + +// +#define CMDQ_CMD_HWSTATUS_CMD_SHIFT _MK_SHIFT_CONST(11) +#define CMDQ_CMD_HWSTATUS_CMD_FIELD (_MK_MASK_CONST(0x1) << CMDQ_CMD_HWSTATUS_CMD_SHIFT) +#define CMDQ_CMD_HWSTATUS_CMD_RANGE _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(11) +#define CMDQ_CMD_HWSTATUS_CMD_ROW 0 +#define CMDQ_CMD_HWSTATUS_CMD_DISABLE _MK_ENUM_CONST(0) +#define CMDQ_CMD_HWSTATUS_CMD_ENABLE _MK_ENUM_CONST(1) + +// +#define CMDQ_CMD_CMD_REG2_SHIFT _MK_SHIFT_CONST(10) +#define CMDQ_CMD_CMD_REG2_FIELD (_MK_MASK_CONST(0x1) << CMDQ_CMD_CMD_REG2_SHIFT) +#define CMDQ_CMD_CMD_REG2_RANGE _MK_SHIFT_CONST(10):_MK_SHIFT_CONST(10) +#define CMDQ_CMD_CMD_REG2_ROW 0 +#define CMDQ_CMD_CMD_REG2_DISABLE _MK_ENUM_CONST(0) +#define CMDQ_CMD_CMD_REG2_ENABLE _MK_ENUM_CONST(1) + +// +#define CMDQ_CMD_CMD_REG1_SHIFT _MK_SHIFT_CONST(9) +#define CMDQ_CMD_CMD_REG1_FIELD (_MK_MASK_CONST(0x1) << CMDQ_CMD_CMD_REG1_SHIFT) +#define CMDQ_CMD_CMD_REG1_RANGE _MK_SHIFT_CONST(9):_MK_SHIFT_CONST(9) +#define CMDQ_CMD_CMD_REG1_ROW 0 +#define CMDQ_CMD_CMD_REG1_DISABLE _MK_ENUM_CONST(0) +#define CMDQ_CMD_CMD_REG1_ENABLE _MK_ENUM_CONST(1) + +// +#define CMDQ_CMD_ADDR_REG2_SHIFT _MK_SHIFT_CONST(8) +#define CMDQ_CMD_ADDR_REG2_FIELD (_MK_MASK_CONST(0x1) << CMDQ_CMD_ADDR_REG2_SHIFT) +#define CMDQ_CMD_ADDR_REG2_RANGE _MK_SHIFT_CONST(8):_MK_SHIFT_CONST(8) +#define CMDQ_CMD_ADDR_REG2_ROW 0 +#define CMDQ_CMD_ADDR_REG2_DISABLE _MK_ENUM_CONST(0) +#define CMDQ_CMD_ADDR_REG2_ENABLE _MK_ENUM_CONST(1) + +// +#define CMDQ_CMD_ADDR_REG1_SHIFT _MK_SHIFT_CONST(7) +#define CMDQ_CMD_ADDR_REG1_FIELD (_MK_MASK_CONST(0x1) << CMDQ_CMD_ADDR_REG1_SHIFT) +#define CMDQ_CMD_ADDR_REG1_RANGE _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(7) +#define CMDQ_CMD_ADDR_REG1_ROW 0 +#define CMDQ_CMD_ADDR_REG1_DISABLE _MK_ENUM_CONST(0) +#define CMDQ_CMD_ADDR_REG1_ENABLE _MK_ENUM_CONST(1) + +// +#define CMDQ_CMD_MST_CTRL_SHIFT _MK_SHIFT_CONST(6) +#define CMDQ_CMD_MST_CTRL_FIELD (_MK_MASK_CONST(0x1) << CMDQ_CMD_MST_CTRL_SHIFT) +#define CMDQ_CMD_MST_CTRL_RANGE _MK_SHIFT_CONST(6):_MK_SHIFT_CONST(6) +#define CMDQ_CMD_MST_CTRL_ROW 0 +#define CMDQ_CMD_MST_CTRL_DISABLE _MK_ENUM_CONST(0) +#define CMDQ_CMD_MST_CTRL_ENABLE _MK_ENUM_CONST(1) + +// +#define CMDQ_CMD_ECC_PTR_SHIFT _MK_SHIFT_CONST(5) +#define CMDQ_CMD_ECC_PTR_FIELD (_MK_MASK_CONST(0x1) << CMDQ_CMD_ECC_PTR_SHIFT) +#define CMDQ_CMD_ECC_PTR_RANGE _MK_SHIFT_CONST(5):_MK_SHIFT_CONST(5) +#define CMDQ_CMD_ECC_PTR_ROW 0 +#define CMDQ_CMD_ECC_PTR_DISABLE _MK_ENUM_CONST(0) +#define CMDQ_CMD_ECC_PTR_ENABLE _MK_ENUM_CONST(1) + +// +#define CMDQ_CMD_TAG_PTR_SHIFT _MK_SHIFT_CONST(4) +#define CMDQ_CMD_TAG_PTR_FIELD (_MK_MASK_CONST(0x1) << CMDQ_CMD_TAG_PTR_SHIFT) +#define CMDQ_CMD_TAG_PTR_RANGE _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(4) +#define CMDQ_CMD_TAG_PTR_ROW 0 +#define CMDQ_CMD_TAG_PTR_DISABLE _MK_ENUM_CONST(0) +#define CMDQ_CMD_TAG_PTR_ENABLE _MK_ENUM_CONST(1) + +// +#define CMDQ_CMD_DATA_BLOCK_PTR_SHIFT _MK_SHIFT_CONST(3) +#define CMDQ_CMD_DATA_BLOCK_PTR_FIELD (_MK_MASK_CONST(0x1) << CMDQ_CMD_DATA_BLOCK_PTR_SHIFT) +#define CMDQ_CMD_DATA_BLOCK_PTR_RANGE _MK_SHIFT_CONST(3):_MK_SHIFT_CONST(3) +#define CMDQ_CMD_DATA_BLOCK_PTR_ROW 0 +#define CMDQ_CMD_DATA_BLOCK_PTR_DISABLE _MK_ENUM_CONST(0) +#define CMDQ_CMD_DATA_BLOCK_PTR_ENABLE _MK_ENUM_CONST(1) + +// +#define CMDQ_CMD_DMA_CNFGB_SHIFT _MK_SHIFT_CONST(2) +#define CMDQ_CMD_DMA_CNFGB_FIELD (_MK_MASK_CONST(0x1) << CMDQ_CMD_DMA_CNFGB_SHIFT) +#define CMDQ_CMD_DMA_CNFGB_RANGE _MK_SHIFT_CONST(2):_MK_SHIFT_CONST(2) +#define CMDQ_CMD_DMA_CNFGB_ROW 0 +#define CMDQ_CMD_DMA_CNFGB_DISABLE _MK_ENUM_CONST(0) +#define CMDQ_CMD_DMA_CNFGB_ENABLE _MK_ENUM_CONST(1) + +// +#define CMDQ_CMD_DMA_CNFGA_SHIFT _MK_SHIFT_CONST(1) +#define CMDQ_CMD_DMA_CNFGA_FIELD (_MK_MASK_CONST(0x1) << CMDQ_CMD_DMA_CNFGA_SHIFT) +#define CMDQ_CMD_DMA_CNFGA_RANGE _MK_SHIFT_CONST(1):_MK_SHIFT_CONST(1) +#define CMDQ_CMD_DMA_CNFGA_ROW 0 +#define CMDQ_CMD_DMA_CNFGA_DISABLE _MK_ENUM_CONST(0) +#define CMDQ_CMD_DMA_CNFGA_ENABLE _MK_ENUM_CONST(1) + +// +#define CMDQ_CMD_CONFIG_SHIFT _MK_SHIFT_CONST(0) +#define CMDQ_CMD_CONFIG_FIELD (_MK_MASK_CONST(0x1) << CMDQ_CMD_CONFIG_SHIFT) +#define CMDQ_CMD_CONFIG_RANGE _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0) +#define CMDQ_CMD_CONFIG_ROW 0 +#define CMDQ_CMD_CONFIG_DISABLE _MK_ENUM_CONST(0) +#define CMDQ_CMD_CONFIG_ENABLE _MK_ENUM_CONST(1) + + +// +// REGISTER LIST +// +#define LIST_ARNANDFLASH_REGS(_op_) \ +_op_(NAND_COMMAND_0) \ +_op_(NAND_STATUS_0) \ +_op_(NAND_ISR_0) \ +_op_(NAND_IER_0) \ +_op_(NAND_CONFIG_0) \ +_op_(NAND_TIMING_0) \ +_op_(NAND_RESP_0) \ +_op_(NAND_TIMING2_0) \ +_op_(NAND_CMD_REG1_0) \ +_op_(NAND_CMD_REG2_0) \ +_op_(NAND_ADDR_REG1_0) \ +_op_(NAND_ADDR_REG2_0) \ +_op_(NAND_DMA_MST_CTRL_0) \ +_op_(NAND_DMA_CFG_A_0) \ +_op_(NAND_DMA_CFG_B_0) \ +_op_(NAND_FIFO_CTRL_0) \ +_op_(NAND_DATA_BLOCK_PTR_0) \ +_op_(NAND_TAG_PTR_0) \ +_op_(NAND_ECC_PTR_0) \ +_op_(NAND_DEC_STATUS_0) \ +_op_(NAND_HWSTATUS_CMD_0) \ +_op_(NAND_HWSTATUS_MASK_0) \ +_op_(NAND_LL_CONFIG_0) \ +_op_(NAND_LL_PTR_0) \ +_op_(NAND_LL_STATUS_0) \ +_op_(NAND_LOCK_CONTROL_0) \ +_op_(NAND_LOCK_STATUS_0) \ +_op_(NAND_LOCK_APER_START0_0) \ +_op_(NAND_LOCK_APER_START1_0) \ +_op_(NAND_LOCK_APER_START2_0) \ +_op_(NAND_LOCK_APER_START3_0) \ +_op_(NAND_LOCK_APER_START4_0) \ +_op_(NAND_LOCK_APER_START5_0) \ +_op_(NAND_LOCK_APER_START6_0) \ +_op_(NAND_LOCK_APER_START7_0) \ +_op_(NAND_LOCK_APER_END0_0) \ +_op_(NAND_LOCK_APER_END1_0) \ +_op_(NAND_LOCK_APER_END2_0) \ +_op_(NAND_LOCK_APER_END3_0) \ +_op_(NAND_LOCK_APER_END4_0) \ +_op_(NAND_LOCK_APER_END5_0) \ +_op_(NAND_LOCK_APER_END6_0) \ +_op_(NAND_LOCK_APER_END7_0) \ +_op_(NAND_LOCK_APER_CHIPID0_0) \ +_op_(NAND_LOCK_APER_CHIPID1_0) \ +_op_(NAND_LOCK_APER_CHIPID2_0) \ +_op_(NAND_LOCK_APER_CHIPID3_0) \ +_op_(NAND_LOCK_APER_CHIPID4_0) \ +_op_(NAND_LOCK_APER_CHIPID5_0) \ +_op_(NAND_LOCK_APER_CHIPID6_0) \ +_op_(NAND_LOCK_APER_CHIPID7_0) \ +_op_(NAND_BCH_CONFIG_0) \ +_op_(NAND_BCH_DEC_RESULT_0) \ +_op_(NAND_BCH_DEC_STATUS_BUF_0) + + +// +// ADDRESS SPACES +// + +#define BASE_ADDRESS_NAND 0x00000000 + +// +// ARNANDFLASH REGISTER BANKS +// + +#define NAND0_FIRST_REG 0x0000 // NAND_COMMAND_0 +#define NAND0_LAST_REG 0x00d4 // NAND_BCH_DEC_STATUS_BUF_0 + +#ifndef _MK_SHIFT_CONST + #define _MK_SHIFT_CONST(_constant_) _constant_ +#endif +#ifndef _MK_MASK_CONST + #define _MK_MASK_CONST(_constant_) _constant_ +#endif +#ifndef _MK_ENUM_CONST + #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL) +#endif +#ifndef _MK_ADDR_CONST + #define _MK_ADDR_CONST(_constant_) _constant_ +#endif + +#endif // ifndef ___ARNANDFLASH_H_INC_ diff --git a/arch/arm/mach-tegra/include/mach/nand.h b/arch/arm/mach-tegra/include/mach/nand.h new file mode 100644 index 000000000000..6f0e95b13662 --- /dev/null +++ b/arch/arm/mach-tegra/include/mach/nand.h @@ -0,0 +1,31 @@ +/* + * arch/arm/mach-tegra/include/mach/nand.h + * + * Copyright (c) 2009, NVIDIA Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#ifndef __MACH_TEGRA_NAND_H +#define __MACH_TEGRA_NAND_H + +#include <linux/mtd/partitions.h> + +struct tegra_nand_platform { + struct mtd_partition *parts; + unsigned int nr_parts; +}; + +#endif diff --git a/arch/arm/mach-tegra/include/nvddk_nand.h b/arch/arm/mach-tegra/include/nvddk_nand.h new file mode 100644 index 000000000000..84d963b02d40 --- /dev/null +++ b/arch/arm/mach-tegra/include/nvddk_nand.h @@ -0,0 +1,599 @@ +/* + * Copyright (c) 2008-2009 NVIDIA Corporation. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of the NVIDIA Corporation nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + */ + +/** + * @file + * <b> NVIDIA Driver Development Kit: NAND Flash Controller Interface</b> + * + * @b Description: This file declares the interface for the NAND module. + */ + +#ifndef INCLUDED_NVDDK_NAND_H +#define INCLUDED_NVDDK_NAND_H + +/** + * @defgroup nvddk_nand NAND Flash Controller Interface + * + * This driver provides the interface to access external NAND flash devices + * that are interfaced to the SOC. + * It provides the APIs to access the NAND flash physically (in raw block number + * and page numbers) and logically (in logical block number through + * block device interface). + * It does not support any software ECC algorithms. It makes use of hardware ECC + * features supported by NAND Controller for validating the data. + * It supports accessing NAND flash devices in interleave mode. + * + * @ingroup nvddk_modules + * @{ + */ + +#include "nvcommon.h" +#include "nvos.h" +#include "nvrm_init.h" +#include "nvodm_query_nand.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * NvDdkNandHandle is an opaque context to the NvDdkNandRec interface. + */ +typedef struct NvDdkNandRec *NvDdkNandHandle; + + +enum{ MAX_NAND_SUPPORTED = 8}; + + +/** + * NAND flash device information. + */ +typedef struct +{ + /// Vendor ID. + NvU8 VendorId; + /// Device ID. + NvU8 DeviceId; + /** + * Redundant area size per page to write any tag information. This will + * be calculated as: + * <pre> TagSize = spareAreaSize - mainAreaEcc - SpareAreaEcc </pre> + * Shim layer is always supposed to request in multiples + * of this number when spare area operations are requested. + */ + NvU8 TagSize; + /// Bus width of the chip: can be 8- or 16-bit. + NvU8 BusWidth; + /// Page size in bytes, includes only data area, no redundant area. + NvU32 PageSize; + /// Number of Pages per block. + NvU32 PagesPerBlock; + /// Total number of blocks that are present in the NAND flash device. + NvU32 NoOfBlocks; + /** + * Holds the zones per flash device--minimum value possible is 1. + * Zone is a group of contiguous blocks among which internal copy back can + * be performed, if the chip supports copy-back operation. + * Zone is also referred as plane or district by some flashes. + */ + NvU32 ZonesPerDevice; + /** + * Total device capacity in kilobytes. + * Includes only data area, no redundant area. + */ + NvU32 DeviceCapacityInKBytes; + /// Interleave capability of the flash. + NvOdmNandInterleaveCapability InterleaveCapability; + /// Device type: SLC or MLC. + NvOdmNandFlashType NandType; + /// Number of NAND flash devices present on the board. + NvU8 NumberOfDevices; + // Size of Spare area + NvU32 NumSpareAreaBytes; + // Offset of Tag data in the spare area. + NvU32 TagOffset; +}NvDdkNandDeviceInfo; + +/** + * Information related to a physical block. + */ +typedef struct +{ + /// Tag information of the block. + NvU8* pTagBuffer; + /// Number of bytes to copy in tag buffer. + NvU32 TagBufferSize; + /// Determines whether the block is factory good block or not. + /// - NV_TRUE if factory good block. + /// - NV_FALSE if factory bad block. + NvBool IsFactoryGoodBlock; + /// Gives the lock status of the block. + NvBool IsBlockLocked; +}NandBlockInfo; + + +/** + * NAND DDK capabilities. + */ +typedef struct +{ + /** + * Flag indicating whether or not ECC is supported by the driver. + * NV_TRUE means it supports ECC, else not supported. + */ + NvBool IsEccSupported; + /** + * Flag indicating whether or not interleaving operation is + * supported by the driver. + * NV_TRUE means it supports interleaving, else not supported. + */ + NvBool IsInterleavingSupported; + /// Whether the command queue mode is supported by the SOC. + NvBool IsCommandQueueModeSupported; + /// Whether EDO mode is suported by the SOC. + NvBool IsEdoModeSupported; + /// Number of ECC parity bytes per spare area. + NvU8 TagEccParitySize; + /// Total number of NAND devices supported by SOC. + NvU32 NumberOfDevicesSupported; + /// Maximum data size that DMA can transfer. + NvU32 MaxDataTransferSize; + /// NAND controller default timing register value. + NvU32 ControllerDefaultTiming; + NvBool IsBCHEccSupported; +}NvDdkNandDriverCapabilities; + +/** + * The structure for locking of required NAND flash pages. + */ +typedef struct +{ + /// Device number of the flash being protected by lock feature. + NvU8 DeviceNumber; + /// Starting page number, from where NAND lock feature should protect data. + NvU32 StartPageNumber; + /// Ending page number, up to where NAND lock feature should protect data. + NvU32 EndPageNumber; +}LockParams; + +/* + * Macro to get expression for modulo value that is power of 2 + * Expression: DIVIDEND % (pow(2, Log2X)) + */ +#define MACRO_MOD_LOG2NUM(DIVIDEND, Log2X) \ + ((DIVIDEND) & ((1 << (Log2X)) - 1)) + +/* + * Macro to get expression for multiply by number which is power of 2 + * Expression: VAL * (1 << Log2Num) + */ +#define MACRO_POW2_LOG2NUM(Log2Num) \ + (1 << (Log2Num)) + +/* + * Macro to get expression for multiply by number which is power of 2 + * Expression: VAL * (1 << Log2Num) + */ +#define MACRO_MULT_POW2_LOG2NUM(VAL, Log2Num) \ + ((VAL) << (Log2Num)) + +/* + * Macro to get expression for div by number that is power of 2 + * Expression: VAL / (1 << Log2Num) + */ +#define MACRO_DIV_POW2_LOG2NUM(VAL, Log2Num) \ + ((VAL) >> (Log2Num)) + +/** + * Initializes the NAND Controller and returns a created handle to the client. + * Only one instance of the handle can be created. + * + * @pre NAND client must call this API first before calling any further NAND APIs. + * + * @param hRmDevice Handle to RM device. + * @param phNand Returns the created handle. + * + * @retval NvSuccess Initialization is successful. + * @retval NvError_AlreadyAllocated The NAND device is already in use. + */ +NvError NvDdkNandOpen(NvRmDeviceHandle hRmDevice, NvDdkNandHandle *phNand); + +/** + * Closes the NAND controller and frees the handle. + * + * @param hNand Handle to the NAND, which is returned by NvDdkNandOpen(). + * + */ +void NvDdkNandClose(NvDdkNandHandle hNand); + +/** + * Reads the data from the selected NAND device(s) synchronously. + * + * @param hNand Handle to the NAND, which is returned by NvDdkNandOpen(). + * @param StartDeviceNum The Device number, which read operation has to be + * started from. It starts from value '0'. + * @param pPageNumbers A pointer to an array containing page numbers for + * each NAND Device. If there are (n + 1) NAND Devices, then + * array size should be (n + 1). + * - pPageNumbers[0] gives page number to access in NAND Device 0. + * - pPageNumbers[1] gives page number to access in NAND Device 1. + * - .................................... + * - pPageNumbers[n] gives page number to access in NAND Device n. + * + * If NAND Device 'n' should not be accessed, fill pPageNumbers[n] as + * 0xFFFFFFFF. + * If the read starts from NAND Device 'n', all the page numbers + * in the array should correspond to the same row, even though we don't + * access the same row pages for '0' to 'n-1' Devices. + * @param pDataBuffer A pointer to read the page data into. The size of buffer + * should be (*pNoOfPages * PageSize). + * @param pTagBuffer Pointer to read the tag data into. The size of buffer + * should be (*pNoOfPages * TagSize). + * @param pNoOfPages The number of pages to read. This count should include + * only valid page count. Consder that total NAND devices present is 4, + * Need to read 1 page from Device1 and 1 page from Device3. In this case, + * \a StartDeviceNum should be 1 and Number of pages should be 2. + * \a pPageNumbers[0] and \a pPageNumbers[2] should have 0xFFFFFFFF. + * \a pPageNumbers[1] and \a pPageNumbers[3] should have valid page numbers. + * The same pointer returns the number of pages read successfully. + * @param IgnoreEccError If set to NV_TRUE, it ignores the ECC error and + * continues to read the subsequent pages with out aborting read operation. + * This is required during bad block replacements. + * + * @retval NvSuccess NAND read operation completed successfully. + * @retval NvError_NandReadEccFailed Indicates NAND read encountered ECC + * errors that cannot be corrected. + * @retval NvError_NandErrorThresholdReached Indicates NAND read encountered + * correctable ECC errors and they are equal to the threshold value set. + * @retval NvError_NandOperationFailed NAND read operation failed. + */ +NvError +NvDdkNandRead( + NvDdkNandHandle hNand, + NvU8 StartDeviceNum, + NvU32* pPageNumbers, + NvU8* const pDataBuffer, + NvU8* const pTagBuffer, + NvU32 *pNoOfPages, + NvBool IgnoreEccError); + +/** + * Writes the data to the selected NAND device(s) synchronously. + * + * @param hNand Handle to the NAND, which is returned by NvDdkNandOpen(). + * @param StartDeviceNum The device number, which write operation has to be + * started from. It starts from value '0'. + * @param pPageNumbers A pointer to an array containing page numbers for + * each NAND Device. If there are (n + 1) NAND Devices, then + * array size should be (n + 1). + * - pPageNumbers[0] gives page number to access in NAND Device 0. + * - pPageNumbers[1] gives page number to access in NAND Device 1. + * - .................................... + * - pPageNumbers[n] gives page number to access in NAND Device n. + * + * If NAND Device 'n' should not be accessed, fill \a pPageNumbers[n] as + * 0xFFFFFFFF. + * If the read starts from NAND device 'n', all the page numbers + * in the array should correspond to the same row, even though we don't + * access the same row pages for '0' to 'n-1' Devices. + * @param pDataBuffer A pointer to read the page data into. The size of buffer + * should be (*pNoOfPages * PageSize). + * @param pTagBuffer Pointer to read the tag data into. The size of buffer + * should be (*pNoOfPages * TagSize). + * @param pNoOfPages The number of pages to write. This count should include + * only valid page count. Consder that total NAND devices present is 4, + * Need to write 1 page to Device1 and 1 page to Device3. In this case, + * \a StartDeviceNum should be 1 and Number of pages should be 2. + * \a pPageNumbers[0] and \a pPageNumbers[2] should have 0xFFFFFFFF. + * \a pPageNumbers[1] and \a pPageNumbers[3] should have valid page numbers. + * The same pointer returns the number of pages written successfully. + * + * @retval NvSuccess Operation completed successfully. + * @retval NvError_NandOperationFailed Operation failed. + */ +NvError +NvDdkNandWrite( + NvDdkNandHandle hNand, + NvU8 StartDeviceNum, + NvU32* pPageNumbers, + const NvU8* pDataBuffer, + const NvU8* pTagBuffer, + NvU32 *pNoOfPages); + +/** + * Erases the selected blocks from the NAND device(s) synchronously. + * + * @param hNand Handle to the NAND, which is returned by NvDdkNandOpen(). + * @param StartDeviceNum The Device number, which erase operation has to be + * started from. It starts from value '0'. + * @param pPageNumbers A pointer to an array containing page numbers for + * each NAND Device. If there are (n + 1) NAND Devices, then + * array size should be (n + 1). + * - pPageNumbers[0] gives page number to access in NAND Device 0. + * - pPageNumbers[1] gives page number to access in NAND Device 1. + * - .................................... + * - pPageNumbers[n] gives page number to access in NAND Device n. + * + * If NAND Device 'n' should not be accessed, fill pPageNumbers[n] as + * 0xFFFFFFFF. + * If the read starts from NAND device 'n', all the page numbers + * in the array should correspond to the same row, even though we don't + * access the same row pages for '0' to 'n-1' Devices. + * @param pNumberOfBlocks The number of blocks to erase. This count should include + * only valid block count. Consder that total NAND devices present is 4, + * Need to erase 1 block from Device1 and 1 block from Device3. In this case, + * \a StartDeviceNum should be 1 and Number of blocks should be 2. + * \a pPageNumbers[0] and \a pPageNumbers[2] should have 0xFFFFFFFF. + * \a pPageNumbers[1] and \a pPageNumbers[3] should have valid page numbers + * corresponding to blocks. + * The same pointer returns the number of blocks erased successfully. + * + * @retval NvSuccess Operation completed successfully. + * @retval NvError_NandOperationFailed Operation failed. + */ +NvError +NvDdkNandErase( + NvDdkNandHandle hNand, + NvU8 StartDeviceNum, + NvU32* pPageNumbers, + NvU32* pNumberOfBlocks); + +/** + * Copies the data in the source page(s) to the destination page(s) + * synchronously. + * + * @param hNand Handle to the NAND, which is returned by NvDdkNandOpen(). + * @param SrcStartDeviceNum The device number, from which data has to be read + * for the copy back operation. It starts from value '0'. + * @param DstStartDeviceNum The device number, to which data has to be copied + * for the copy back operation. It starts from value '0'. + * @param pSrcPageNumbers A pointer to an array containing page numbers for + * each NAND Device. If there are (n + 1) NAND Devices, then + * array size should be (n + 1). + * - pSrcPageNumbers[0] gives page number to access in NAND Device 0. + * - pSrcPageNumbers[1] gives page number to access in NAND Device 1. + * - .................................... + * - pSrcPageNumbers[n] gives page number to access in NAND Device n. + * + * If NAND Device 'n' should not be accessed, fill \a pSrcPageNumbers[n] as + * 0xFFFFFFFF. + * If the copy-back starts from NAND devices 'n', all the page numbers + * in the array should correspond to the same row, even though we don't + * access the same row pages for '0' to 'n-1' Devices. + * @param pDestPageNumbers A pointer to an array containing page numbers for + * each NAND Device. If there are (n + 1) NAND Devices, then + * array size should be (n + 1). + * - pDestPageNumbers[0] gives page number to access in NAND Device 0. + * - pDestPageNumbers[1] gives page number to access in NAND Device 1. + * - .................................... + * - pDestPageNumbers[n] gives page number to access in NAND Device n. + * + * If NAND Device 'n' should not be accessed, fill \a pDestPageNumbers[n] as + * 0xFFFFFFFF. + * If the Copy-back starts from Interleave column 'n', all the page numbers + * in the array should correspond to the same row, even though we don't + * access the same row pages for '0' to 'n-1' Devices. + * @param pNoOfPages The number of pages to copy-back. This count should include + * only valid page count. Consider that total NAND devices present is 4, + * Need to Copy-back 1 page from Device1 and 1 page from Device3. In this + * case, \a StartDeviceNum should be 1 and Number of pages should be 2. + * \a pSrcPageNumbers[0], \a pSrcPageNumbers[2], \a pDestPageNumbers[0] and + * \a pDestPageNumbers[2] should have 0xFFFFFFFF. \a pSrcPageNumbers[1], + * \a pSrcPageNumbers[3], \a pDestPageNumbers[1] and \a pDestPageNumbers[3] + * should have valid page numbers. + * The same pointer returns the number of pages copied-back successfully. + * @param IgnoreEccError NV_TRUE to ingnore ECC errors, NV_FALSE otherwise. + * + * @retval NvSuccess Operation completed successfully + * @retval NvError_NandOperationFailed Operation failed. + */ +NvError +NvDdkNandCopybackPages( + NvDdkNandHandle hNand, + NvU8 SrcStartDeviceNum, + NvU8 DstStartDeviceNum, + NvU32* pSrcPageNumbers, + NvU32* pDestPageNumbers, + NvU32 *pNoOfPages, + NvBool IgnoreEccError); + +/** + * Gets the NAND flash device information. + * + * @param hNand Handle to the NAND, which is returned by NvDdkNandOpen(). + * @param DeviceNumber NAND flash device number. + * @param pDeviceInfo Returns the device information. + * + * @retval NvSuccess Operation completed successfully. + * @retval NvError_NandOperationFailed NAND copy back operation failed. + */ + NvError + NvDdkNandGetDeviceInfo( + NvDdkNandHandle hNand, + NvU8 DeviceNumber, + NvDdkNandDeviceInfo* pDeviceInfo); + +/** + * Locks the specified NAND flash pages. + * + * @param hNand Handle to the NAND, which is returned by NvDdkNandOpen(). + * @param pFlashLockParams A pointer to the range of pages to be locked. + */ +void +NvDdkNandSetFlashLock( + NvDdkNandHandle hNand, + LockParams* pFlashLockParams); + +/** + * Returns the details of the locked apertures, like device number, starting + * page number, ending page number of the region locked. + * + * @param hNand Handle to the NAND, which is returned by NvDdkNandOpen(). + * @param pFlashLockParams A pointer to first array element of \a LockParams type + * with eight elements in the array. + * Check if \a pFlashLockParams[i].DeviceNumber == 0xFF, then that aperture is + * free to use for locking. + */ +void +NvDdkNandGetLockedRegions( + NvDdkNandHandle hNand, + LockParams* pFlashLockParams); +/** + * Releases all regions that were locked using NvDdkNandSetFlashLock API. + * + * @param hNand Handle to the NAND, which is returned by NvDdkNandOpen(). + */ +void NvDdkNandReleaseFlashLock(NvDdkNandHandle hNand); + +/** + * Gets the NAND driver capabilities. + * + * @param hNand Handle to the NAND, which is returned by NvDdkNandOpen(). + * @param pNandDriverCapabilities Returns the capabilities. + * + */ +void +NvDdkNandGetCapabilities( + NvDdkNandHandle hNand, + NvDdkNandDriverCapabilities* pNandDriverCapabilities); + +/** + * Gives the block specific information such as tag information, lock status, block good/bad. + * @param hNand Handle to the NAND, which is returned by NvDdkNandOpen(). + * @param DeviceNumber Device number in which the requested block exists. + * @param BlockNumber Requested physical block number. + * @param pBlockInfo Return the block information. + * @param SkippedBytesReadEnable NV_TRUE enables reading skipped bytes. + * + * @retval NvSuccess Success + */ +NvError +NvDdkNandGetBlockInfo( + NvDdkNandHandle hNand, + NvU32 DeviceNumber, + NvU32 BlockNumber, + NandBlockInfo* pBlockInfo, + NvBool SkippedBytesReadEnable); + +/** + * Part of static power management, call this API to put the NAND controller + * into suspend state. This API is a mechanism for client to augment OS + * power management policy. + * + * The h/w context of the NAND controller is saved. Clock is disabled and power + * is also disabled to the controller. + * + * @param hNand Handle to the NAND, which is returned by NvDdkNandOpen(). + * + * @retval NvSuccess Success + * @retval NvError_BadParameter Invalid input parameter value + */ +NvError NvDdkNandSuspend(NvDdkNandHandle hNand); + +/** + * Part of static power management, call this API to wake the NAND controller + * from suspend state. This API is a mechanism for client to augment OS power + * management policy. + * + * The h/w context of the NAND controller is restored. Clock is enabled and power + * is also enabled to the controller + * + * @param hNand Handle to the NAND, which is returned by NvDdkNandOpen(). + * + * @retval NvSuccess Success + * @retval NvError_BadParameter Invalid input parameter value + */ +NvError NvDdkNandResume(NvDdkNandHandle hNand); + +/** + * Part of local power management of the driver. Call this API to turn off the + * clocks required for NAND controller operation. + * + * @param hNand Handle to the NAND, which is returned by NvDdkNandOpen(). + * + * @retval NvSuccess Success + * @retval NvError_BadParameter Invalid input parameter value + */ +NvError NvDdkNandSuspendClocks(NvDdkNandHandle hNand); + +/** + * Part of local power management of the driver. Call this API to turn on the + * clocks required for NAND controller operation. + * + * @param hNand Handle to the NAND, which is returned by NvDdkNandOpen(). + * + * @retval NvSuccess Success + * @retval NvError_BadParameter Invalid input parameter value + */ +NvError NvDdkNandResumeClocks(NvDdkNandHandle hNand); + +/** + * API to read to the spare area. + */ +NvError +NvDdkNandReadSpare( + NvDdkNandHandle hNand, + NvU8 StartDeviceNum, + NvU32* pPageNumbers, + NvU8* const pSpareBuffer, + NvU8 OffsetInSpareAreaInBytes, + NvU8 NumSpareAreaBytes); + +/** + * API to write to the spare area. Use this API with caution, as there is a + * risk of overriding the factory bad block data. + */ +NvError +NvDdkNandWriteSpare( + NvDdkNandHandle hNand, + NvU8 StartDeviceNum, + NvU32* pPageNumbers, + NvU8* const pSpareBuffer, + NvU8 OffsetInSpareAreaInBytes, + NvU8 NumSpareAreaBytes); + +/* + * Functions shared between Ddk Nand, block driver and FTL code + */ +// Function to compare buffer contents +NvU32 NandUtilMemcmp(const void *pSrc, const void *pDst, NvU32 Size); + +// Simple function to get log2, assumed value power of 2, else return +// log2 for immediately smaller number +NvU8 NandUtilGetLog2(NvU32 Val); + +#ifdef __cplusplus +} +#endif + +/** @} */ +#endif // INCLUDED_NVDDK_NAND_H diff --git a/arch/arm/mach-tegra/nvddk/Makefile b/arch/arm/mach-tegra/nvddk/Makefile new file mode 100644 index 000000000000..7bc52709d605 --- /dev/null +++ b/arch/arm/mach-tegra/nvddk/Makefile @@ -0,0 +1,6 @@ +ccflags-y += -DNV_IS_AVP=0 +ccflags-y += -DNV_OAL=0 +ccflags-y += -DNV_USE_FUSE_CLOCK_ENABLE=0 +ccflags-y += -DNV_DEBUG=0 + +obj-$(CONFIG_MTD_NAND_TEGRA) += nvddk_nand.o diff --git a/arch/arm/mach-tegra/nvddk/nvddk_nand.c b/arch/arm/mach-tegra/nvddk/nvddk_nand.c new file mode 100644 index 000000000000..a1d372cad62e --- /dev/null +++ b/arch/arm/mach-tegra/nvddk/nvddk_nand.c @@ -0,0 +1,4948 @@ +/* + * Copyright (c) 2007-2009 NVIDIA Corporation. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of the NVIDIA Corporation nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + */ + +/** + * @file + * @brief <b>NVIDIA Driver Development Kit: + * NvDDK NAND APIs</b> + * + * @b Description: Declares Interface for NvDDK NAND module. + * + */ + +#include "nvddk_nand.h" +#include "nvodm_query_nand.h" +#include "ap20/arnandflash.h" +#include "nvrm_hardware_access.h" +#include "nvrm_power.h" +#include "nvrm_module.h" +#include "nvrm_gpio.h" +#include "nvrm_drf.h" +#include "nvassert.h" +#include "nvrm_memmgr.h" +#include "nvrm_interrupt.h" +#include "nvrm_pinmux.h" +#include "nvodm_query_pinmux.h" +#include "nvodm_query_nand.h" +#include "nvodm_query_gpio.h" +#include "nvodm_query_discovery.h" +#include "nvrm_pmu.h" + +#if NV_OAL + #define IS_CQ_ENABLED 0 +#else + #define IS_CQ_ENABLED 1 +#endif + + +// Enable following define for verifying write operations on to Nand +#define WRITE_VERIFY 0 +#define NAND_RANDOM_FAILURES 0 +#define NUMBER_OF_ITERATIONS_BEFORE_ERROR 100 +#define ENABLE_INTERNAL_COPYBACK 0 +#define NAND_MAX_BYTES_PER_PAGE 4096 + +// For internal Debug purpose and to display messages selectively. +#define DEBUG_NAND 0 +NvU8 DebugPrintEnable = 0; +#if DEBUG_NAND +#define NAND_TIME_STAMP 0 +#define NAND_DISP_INTS 0 +#define NAND_DISP_ERROR 1 +#define NAND_DISP_REG 1 +#define NAND_DISPLAY_ALL 0 +#define NAND_ASSRT_ERRORS 0 +#else +#define NAND_TIME_STAMP 0 +#define NAND_DISP_INTS 0 +#define NAND_DISP_ERROR 1 +#define NAND_DISP_REG 1 +#define NAND_DISPLAY_ALL 0 +#define NAND_ASSRT_ERRORS 0 +#endif +#if NAND_DISPLAY_ALL + #define PRINT_ALL(X) NvOsDebugPrintf X +#else + #define PRINT_ALL(X) +#endif +#if NAND_DISP_ERROR + #define PRINT_ERROR(X) NvOsDebugPrintf X +#else + #define PRINT_ERROR(X) +#endif +#if NAND_DISP_INTS + #define PRINT_INTS(X) NvOsDebugPrintf X +#else + #define PRINT_INTS(X) +#endif +#if NAND_DISP_REG + #define PRINT_REG(X) NvOsDebugPrintf X +#else + #define PRINT_REG(X) +#endif +#if NAND_ASSRT_ERRORS + #define NAND_ASSERT(e) \ + do \ + { \ + if (e != NvSuccess) \ + { \ + NV_ASSERT(NV_FALSE); \ + NvOsDebugPrintf("\r\n Nand Assert Err = 0x%x", e); \ + }\ + }while (0) +#else + #define NAND_ASSERT(e) +#endif + +#if NV_OAL + #define NAND_DDK_ENABLE_DMA_POLLING_MODE 1 +#else + #define NAND_DDK_ENABLE_DMA_POLLING_MODE 0 +#endif +#if NAND_DDK_ENABLE_DMA_POLLING_MODE + #define NAND_DDK_ENABLE_COMMAND_POLLING_MODE 1 +#else + #define NAND_DDK_ENABLE_COMMAND_POLLING_MODE 0 +#endif + +// Wait time out in mili seconds +#define NAND_COMMAND_TIMEOUT_IN_MS 1000 +/* + These constants are used to get the Bus Width, Page Size, Block Size and + the Redundant Area Size from ReadID +*/ +#define DDK_NAND_ID_DECODE_0_BUS_WIDTH_RANGE 30:30 +#define DDK_NAND_ID_DECODE_0_BLOCK_SIZE_RANGE 29:28 +#define DDK_NAND_ID_DECODE_0_REDUNDANT_AREA_SIZE_RANGE 26:26 +#define DDK_NAND_ID_DECODE_0_PAGE_SIZE_RANGE 25:24 + +#define DDK_42NM_NAND_ID_DECODE_0_BLOCK_SIZE_MSB_RANGE 31:31 +#define DDK_42NM_NAND_ID_DECODE_0_REDUNDANT_AREA_SIZE_RANGE 27:26 +#define DDK_42NM_NAND_ID_DECODE_0_REDUNDANT_AREA_SIZE_MSB_RANGE 30:30 +// Some of the golden constant values +enum GoldenValues +{ + // Timing register value that works with most of the Nand flashes. + // This value is used for identifying nand flash. + TIMING_VALUE = 0x3F0BD214, // 0x3F2BD214 can be used for Ap15. not for Ap10, + TIMING2_VALUE = 0xB, + // Physical Buffers need to be Word Aligned + NAND_BUFFER_ALIGNMENT = 32, + // Nand Flash operation success status. valid for most of the flashes + SUCCESS_STATUS = 0x40, + // Max round trip delay for Non EDO modes + MAX_ROUND_TRIP_DELAY = 13 +}; + +enum +{ + // maximum erase attempts before returning failure + DDK_NAND_MAX_ERASE_RETRY = 3 +}; + +typedef enum +{ + NandOperation_Reset = 1, + NandOperation_ReadId, + NandOperation_Read, + NandOperation_Write, + NandOperation_Erase, + NandOperation_GetStatus, + NandOperation_CopybackRead, + NandOperation_CopybackProgram, + NandOperation_ReadParamPage, + NandOperation_DataCyclesAlone, + NandOperation_Force32 = 0x7FFFFFFF +}NandOperation; + +// Structure to hold parameters required for Nand thread to perform +// Read/Write/Copy-back operations. +typedef struct NandParamsRec +{ + // Flash chip number on to which the requested operation is to take place. + NvU8 DeviceNumber; + // Destination device number for copyback. + NvU8 DstnDeviceNumber; + NvU32 StartPageNumber; + // The starting page number of the Nand flash for the requested opeartion. + // this will be considered as source page in case of copy bacck operations. + NvU32* pStartPageNumbers; + // The destination page number of the Nand flash for copy back opeartion. + // for Read/ Write operations this param is don't care. + NvU32* pDstnPageNumbers; + // Holds the column number. + NvU32 ColumnNumber; + // Number of spare area bytes to read/write. + NvU32 NumSpareAreaBytes; + // Client buffer for receiving or transmitting the page data. + NvU8* pDataBuffer; + // Client buffer for receiving or transmitting the spare data. + NvU8* pTagBuffer; + // Holds the number of pages to read/write. + NvU32 NumberOfPages; + // Returns the number of pages completed. + NvU32 NumberOfPagesCompleted; + // The type of nand operation requested - Read/Write/Copy back. + NandOperation OperationName; + // time out for the requested operation in milli seconds. + NvU32 WaitTimeoutInMilliSeconds; + // Semaphore Id that needs to signalled once the operation is complete. + NvOsSemaphoreHandle SemaphoreId; +}NandParams; + +// params to be passed for allocating physical buffer from SDRAM +typedef struct SdramBufferParamsRec +{ + // Virtual Buffer Pointer used to hold the pointer to the buffer + NvU8* pVirtualBuffer; + // Physical Buffer Pointer used to hold the pointer to the buffer + NvRmPhysAddr PhysBuffer; + // memory handle + NvRmMemHandle hMem; + // holds buffer size + NvU32 BufferSize; +}SdramBufferParams; + +// Defines the type of algorithm for error-correcting code (ECC). +typedef enum +{ + // Specifies Hamming ECC. + ECCAlgorithm_Hamming = 0, + // Specifies Reed-Solomon ECC. + ECCAlgorithm_ReedSolomon, + // Specifies BCH ECC. + ECCAlgorithm_BCH, + // Ecc disabled + ECCAlgorithm_None, + ECCAlgorithm_Force32 = 0x7FFFFFFF +}ECCAlgorithm; + +// structure for Nand handle. +typedef struct NvDdkNandRec +{ + // Holds a flag indicating whether Nand controller is open and initialized. + NvBool IsNandOpen; + // Nand Controller registers physical base address + NvRmPhysAddr pBaseAddress; + // Holds the virtual address for accessing registers. + NvU32 *pVirtualAddress; + // Holds the register map size. + NvU32 BankSize; + // RM device handle + NvRmDeviceHandle RmDevHandle; + // copy of Gpio handle + NvRmGpioHandle hGpio; + NvRmGpioPinHandle hWriteProtectPin; + // Variable used to hold information related ECC algorithm to be used: + // Hamming or Reed-solomon + ECCAlgorithm EccAlgorithm; + // Variable used to hold flash device information. + NvDdkNandDeviceInfo DevInfo; + // Variable used to hold the number of active devices on board. + NvU8 NumOfActiveDevices; + // variable to hold the RS-T value (number of correctable errors per sector + NvU8 TValue; + // Variable used to hold the number of Pages requested for current Nand operation + NvU32 NumOfPagesRequested; + // Number of Chips to be interleaved for the current read/ Write oepration. + NvU32 NumberOfChipsToBeInterleaved; + // Variable to hold the number of Pages successfully read/ written in + // current Nand operation + NvU32 NumOfPagesTransferred; + // Variable to hold the number of Tag (Spare) area Pages successfully + // read/ written in current Nand operation. + NvU32 NumOfTagPagesTransferred; + // Variable used to hold the information related to the current operation + // status (from thread). + NvError OperationStatus; + // Semaphore used for Synchronizing internal activities of to the ddk. + NvOsSemaphoreHandle CommandDoneSema; + // Semaphore to be used for DMA Interrupt signaling. + NvOsSemaphoreHandle DmaDoneSema; + // Semaphore to be used for Power Management signaling.purposes + NvOsSemaphoreHandle PowerMgmtSema; + // Nand configuration pin-map. + NvOdmNandPinMap PinMap; + // Variable to hold various Flash parameter values. + NvOdmNandFlashParams FlashParams; + // a flag to indicate the current nand flash operation usage of command + // queue. If True-use command Q mode else normal mode + NvBool IsCommandQueueOperation; + // Gives information about the Nand flash capability to support copy back + // operation. + NvBool IsCopybackSupported; + // a flag to indicate if the combined rdy/bsy mode is being used. + NvBool IsCombRbsyMode; + // A flag to check if command queue error has occured + NvBool IsCqError; + // PhysicalDeviceNumber[0] will give chipId / deviceNumber of the first + // physical nand chip avail on the board. + NvU8 PhysicalDeviceNumber[NDFLASH_CS_MAX]; + // pointer to nand driver capability structure + NvDdkNandDriverCapabilities NandCapability; + // Command queue buffer size + NvU32 CqBufferSize; + // Variable to hold the information of Cache write command support + NvBool IsCacheWriteSupproted; + // Ecc buffer size + NvU32 EccBufferSize; + // structure to hold parameters related to Command queue buffer in SDRAM + SdramBufferParams CqBuffer; + // structure to hold parameters related to Ecc buffer in SDRAM + SdramBufferParams EccBuffer; + // structure to hold parameters related to Physical data buffer in SDRAM + SdramBufferParams DataBuffer; + // structure to hold parameters related to Physical Tag buffer in SDRAM + SdramBufferParams TagBuffer; + // Number of lock apertures used for nand flash. + NvU8 NumberOfAperturesUsed; + // For each lock aperture, current Aperture Start, Aperture End, and Chip ID + // register values + NvU32 LockAperStart[NDFLASH_CS_MAX]; + NvU32 LockAperEnd[NDFLASH_CS_MAX]; + NvU32 LockAperChipId[NDFLASH_CS_MAX]; + // To store Rm power client Id + NvU32 RmPowerClientId; + // To store optimum timing register value. + NvU32 OptimumTiming; + NvU32 OptimumTiming2; + // Maximum number of pages that can bre read/written in one stretch through DMA. + NvU32 MaxNumOfPagesPerDMARequest; + // Interrupt handle + NvOsInterruptHandle InterruptHandle; + // Frequency set to Nand. + NvRmFreqKHz FreqInKhz; + // Indicates whether to signal command done sema. + volatile NvBool SignalCommandDoneSema; + // Holds the Ecc error page info. + volatile NvU32* pEccErrorData; + volatile NvU32 EccErrorCount; + NvU32 EccFailedPage; + NvU8 NandBusWidth; + NandParams Params; + NvBool IsNandClkEnabled; + /* flag to ensure suspend is not executed twice */ + NvBool IsNandSuspended; + // Flag to check if lock status is read from the device + NvBool IsLockStatusAvailable; + // To Hold the error threshold value. + NvU8 ErrThreshold; + NvBool IsBCHEccSupported; + // This flag is set if ONFI Nand is used on CS0. Based on this info other + // CS will be checked for ONFI initialization. + NvBool IsONFINandOnCs0; + // Peripheral DataBase + const NvOdmPeripheralConnectivity *pConnectivity; + // Mutex for thread safety + NvOsMutexHandle hMutex; + // Reference count to keep track of number of open calls made. + NvU32 RefCount; + // Profiling command issue count + NvU32 StartCommandCount; + // To hold the spare area size per each page of the flash + NvU16 SpareAreaSize; +}NvDdkNand; + +// This enum enumerates various bit positions for framing Nand Flash +// Controller Command Queue command word +typedef enum +{ + // presence of Config reg data in the command queue data field + CqCommand_NandConfig = 0, + // presence of DMA Config_A reg data in the command queue data field + CqCommand_NandDmaConfig_A = 1, + // presence of DMA Config_B reg data in the command queue data field + CqCommand_NandDmaConfig_B = 2, + // presence of Data Block Pointer reg data in the command queue data field + CqCommand_NandDataBlockPtr = 3, + // presence of Tag Pointer reg data in the command queue data field + CqCommand_NandTagPtr = 4, + // presence of ECC Pointer reg data in the command queue data field + CqCommand_NandEccPtr = 5, + // presence of DMA Master control reg data in the command queue data field + CqCommand_NandDmaMstCtrl = 6, + // presence of Addr Reg1 reg data in the command queue data field + CqCommand_NandAddrReg1 = 7, + // presence of Addr Reg2 reg data in the command queue data field + CqCommand_NandAddrReg2 = 8, + // presence of Command Reg1 reg data in the command queue data field + CqCommand_NandCmdReg1 = 9, + // presence of Command Reg2 reg data in the command queue data field + CqCommand_NandCmdReg2 = 10, + // presence of Hardware Status Command reg data in the command queue data field + CqCommand_NandHwStatusCmd = 11, + // presence of Hardware Status Mask reg data in the command queue data field + CqCommand_NandHwStatusMask = 12, + // presence of Command reg data in the command queue data field + CqCommand_NandCmd = 13, + // Packet ID of the command in the queue + CqCommand_PacketId = 24, + CqCommand_Force32 = 0x7FFFFFFF +}CqCommand; + +// This is stucture definition for Nand Flash Controller Command Queue packet +typedef struct NandCqPacket1Rec +{ + // Command queue command word, gives information about what registers + // to be filled with the following data. + NvU32 CqCommand; + // Data to be filled into Nand DMA control register. + NvU32 NandDmaMstCtrl; + // Data to be filled into Nand Command register2. + NvU32 NandCmdReg2; + // Data to be filled into Nand Command register. + NvU32 NandCmd; +}NandCqPacket1; + +typedef struct NandCqPacket2Rec +{ + // Command queue command word, gives information about what registers + // to be filled with the following data. + NvU32 CqCommand; + // Data to be filled into Nand Address register1. + NvU32 NandAddrReg1; + // Data to be filled into Nand Address register2. + NvU32 NandAddrReg2; + // Data to be filled into Nand Command register2. + NvU32 NandCmdReg2; + // Data to be filled into Nand Command register. + NvU32 NandCmd; +}NandCqPacket2; + +typedef struct NandCqPacket3Rec +{ + // Command queue command word, gives information about what registers + // to be filled with the following data. + NvU32 CqCommand; + // Data to be filled into Nand Command register. + NvU32 NandCmd; +}NandCqPacket3; + +// Defining constants to identify Ddk operations used to print error messages +typedef enum { + NAND_OP_READ, + NAND_OP_WRITE, + NAND_OP_ERASE, + NAND_OP_CPYBK, + NAND_OP_NUM, + NAND_OP_Force32 = 0x7FFFFFFF +} NAND_OP; + +/** Static variables */ +// Nand ddk structure pointer. +static NvDdkNand* s_pNandRec = NULL; + +#if WRITE_VERIFY +static NvU8 s_WriteVerifyBuffer[65536]; +#endif + +// static functions prototype.// +static NvError +MemAllocBuffer( + NvDdkNandHandle hNand, + SdramBufferParams *SdramParams, + NvU32 Alignment); +static void DestroyMemHandle(SdramBufferParams *SdramParams); +static void DumpRegData(NvDdkNandHandle hNand); +static void SetTimingRegVal(NvDdkNandHandle hNand, NvBool IsCalcRequired); +static NvU32 GetNumOfErrorVectorBytes(NvDdkNandHandle hNand); +static NvU8 GetNumOfParityBytesForMainArea(NvDdkNandHandle hNand); +static void FillPageSize(NvDdkNandHandle hNand, NvU32* ConfigReg); +static void ChipSelectEnable(NvU8 DeviceNumber, NvU32 *CommandReg); +static void StartCqOperation(NvDdkNandHandle hNand); +static void StartNandOperation(NvDdkNandHandle hNand); +static void SetCombRbsyAndEdoModes(NvDdkNandHandle hNand); +static void SetupInterrupt(NvDdkNandHandle hNand, NandOperation Op); +static void CleanInterruptRegisters(NvDdkNandHandle hNand); +static void +SetupAddressAndDeviceReg( + NvDdkNandHandle hNand, + NvU32 DevNum, + NvU32 StartPageNumber); +static void SetupRegisters(NvDdkNandHandle hNand, NandOperation Op); +static NvError NandRead(NvDdkNandHandle hNand, NvBool IgnoreEccError); +static void +SkipUnusedDevices(NvDdkNandHandle hNand, + NvU32* pPageNumbers, + NvU8* pStartDeviceNum, + NvU32* pOffset); +static NvError NandCopyback(NvDdkNandHandle hNand, NvBool IgnoreEccError); +#if ENABLE_INTERNAL_COPYBACK +static NvError NandInternalCopyback(NvDdkNandHandle hNand); +#endif +static NvError EnableNandClock(NvDdkNandHandle hNand); +static NvError NvDdkNandPrivSetPinMux(NvDdkNandHandle hNand); +static NvError InitNandController(NvDdkNandHandle hNand); +static void SetupDMA(NvDdkNandHandle hNand); +static void +SetCommandQueueOperationState( + NvDdkNandHandle hNand, + NvU32 NumberOfPages, + NandParams *p); +static NvU32 GetColumnNumber(NvDdkNandHandle hNand); +static NvError WaitForCqDone(NvDdkNandHandle hNand); +static void GetNumOfCsInterleaved(NvDdkNandHandle hNand, NvU32 *pPageNumbers); +static NvError WaitForDmaDone(NvDdkNandHandle hNand); +static NvError WaitForCommandDone(NvDdkNandHandle hNand); +static NvError NandCheckForEccError(NvDdkNandHandle hNand, NvU32* Offset); +static NvError NandWrite(NvDdkNandHandle hNand); +static NvError +NandReadID( + NvDdkNandHandle hNand, + NvU8 DevNumber, + NvU32* ReadID, + NvBool IsOnfiNand); +#if NAND_DDK_ENABLE_DMA_POLLING_MODE +static void NandWaitUS(NvU32 usec); +static NvError NandWaitDmaDone(NvDdkNandHandle hNand); +static NvError NandWaitCqDone(NvDdkNandHandle hNand); +#endif +static NvError NandWaitCommandDone(NvDdkNandHandle hNand); +static NvError +RegisterNandInterrupt( + NvRmDeviceHandle hDevice, + NvDdkNandHandle hNand); +static void ClearNandFifos(NvDdkNandHandle hNand); +static void NandIsr(void* args); +static NvError NandDisableWriteProtect(NvDdkNandHandle hNand); +static void NandLoadLockCfg(NvDdkNandHandle hNand); +static void NandRestoreLocks(NvDdkNandHandle hNand); +static void +NandPrivLockInterruptService( + NvDdkNandHandle hNand, + NvU32 InterruptStatusRegister); +static void SetupCqPkt(NvDdkNandHandle hNand); +static NvError GetOperationStatus(NvDdkNandHandle hNand, NvU8 DeviceNumber); +static NvU8 GetBitPosition(NvU32 Number); +static void NandPowerRailEnable(NvDdkNandHandle hNand, NvBool IsEnable); +static void NandWaitUS(NvU32 usec); +static NvError ResetNandFlash(NvDdkNandHandle hNand, const NvU8 DeviceNumber); + +// Macro definitions // +// Nand register read macro +#define Nand_REGR(hNand, reg) \ + NV_READ32(hNand->pVirtualAddress + ((NAND_##reg##_0) / 4)) +// Nand register write macro +#define Nand_REGW(hNand, reg, data) \ +do \ +{ \ + NV_WRITE32(hNand->pVirtualAddress + ((NAND_##reg##_0) / 4), (data)); \ +}while (0) + +// Nand register read macro with offset. +#define Nand_REGR_OFFSET(hNand, reg, OffsetInBytes) \ + NV_READ32(hNand->pVirtualAddress + (OffsetInBytes / 4) + \ + ((NAND_##reg##_0) / 4)) + +// Nand register write macro with offset. +#define Nand_REGW_OFFSET(hNand, reg, OffsetInBytes, data) \ +do \ +{ \ + NV_WRITE32(hNand->pVirtualAddress + (OffsetInBytes / 4) + \ + ((NAND_##reg##_0) / 4), (data)); \ +}while (0) + +// Macro to get the difference between two numbers +#define DIFF(T1, T2) \ + (((T1) > (T2)) ? ((T1) - (T2)) : ((T2) - (T1))) + +// Macro to get the bigger of the two +#define BIGGEROF(A, B) ((A > B) ? A : B) + +// Macro to get the biggest of the three numbers +#define BIGGESTOF(A, B, C) BIGGEROF(BIGGEROF(A, B), C) + +// static functions definition.// +static NvError +MemAllocBuffer( + NvDdkNandHandle hNand, + SdramBufferParams *SdramParams, + NvU32 Alignment) +{ + NvError e; + NvRmPhysAddr* PhyBuffer = &(SdramParams->PhysBuffer); + NvU8** VirBuffer = &(SdramParams->pVirtualBuffer); + NvU32 Size = SdramParams->BufferSize; + + // The first step to allocate a memory buffer is, allocating a handle for it. + NV_CHECK_ERROR(NvRmMemHandleCreate(hNand->RmDevHandle, + &(SdramParams->hMem), Size)); + // After specifying the properties of the memory buffer, + // it can be allocated. + NV_CHECK_ERROR_CLEANUP(NvRmMemAlloc(SdramParams->hMem, NULL, + 0, Alignment, NvOsMemAttribute_Uncached)); + // Before the memory buffer is used, it must be pinned. + *PhyBuffer = NvRmMemPin(SdramParams->hMem); + // For virtual address, the memory buffer is mapped into the process's + // address space. + NV_CHECK_ERROR_CLEANUP(NvRmMemMap(SdramParams->hMem, 0, Size, + NVOS_MEM_READ_WRITE, (void **)VirBuffer)); + NvOsMemset(*VirBuffer, 0, Size); + return e; +fail: + DestroyMemHandle(SdramParams); + return e; +} + +// This function deallocates physical buffer that was allocated in MemAllocBuffer. +static void DestroyMemHandle(SdramBufferParams *SdramParams) +{ + if (SdramParams->hMem) + { + // UnMap the handle + if (SdramParams->pVirtualBuffer) + NvRmMemUnmap(SdramParams->hMem, SdramParams->pVirtualBuffer, + SdramParams->BufferSize); + SdramParams->pVirtualBuffer = NULL; + // Unpin the memory allocation. + NvRmMemUnpin(SdramParams->hMem); + // Free the memory handle. + NvRmMemHandleFree(SdramParams->hMem); + SdramParams->hMem = NULL; + } +} + +// Function to compare byte by byte and print details if mismatched +NvU32 NandUtilMemcmp(const void *pSrc, const void *pDst, NvU32 Size) +{ + NvU32 i; + NvU32 MismatchCount = 0; + for (i = 0; i< Size; i++) + { + if ((*((NvU8 *)pSrc + i)) != (*((NvU8 *)pDst + i))) + { + // mismatch between compared byte sequences + if (!MismatchCount) + { + PRINT_ALL(("\n[index: Wr,Rd] ")); + } + PRINT_ALL((" [%d: 0x%x,0x%x] ", i, + (*((NvU8 *)pSrc + i)), (*((NvU8 *)pDst + i)))); + MismatchCount++; + } + } + if (MismatchCount) + { + PRINT_ALL(("\nMismatch: %d/%d ", MismatchCount, Size)); + } + return MismatchCount; +} + +// function to check power of 2 +static NvBool +UtilCheckPowerOf2(NvU32 Num) +{ + // A power of 2 satisfies condition (N & (N - 1)) == (2 * N - 1) + if ((Num & (Num - 1)) == 0) + return NV_TRUE; + else + return NV_FALSE; +} + +// Simple function to get log2, assumed value power of 2, else return +// returns log2 of immediately smaller number +NvU8 +NandUtilGetLog2(NvU32 Val) +{ + NvU8 Log2Val = 0; + NvU32 i; + // Value should be non-zero + NV_ASSERT(Val > 0); + if (UtilCheckPowerOf2(Val) == NV_FALSE) + { + NvOsDebugPrintf("\nCalling simple log2 with value which is " + "not power of 2 "); + // In case of values that are not power of 2 we return the + // integer part of the result of log2 + } + // Value is power of 2 + if (Val > 0) + { + // Assumed that Val is NvU32 + for (i = 0; i < 32; i++) + { + // divide by 2 + Val = MACRO_DIV_POW2_LOG2NUM(Val, 1); + if (Val == 0) + { + // Return 0 when Val is 1 + break; + } + Log2Val++; + } + } + return Log2Val; +} + +static void DumpRegData(NvDdkNandHandle hNand) +{ + PRINT_REG(("====== Register Dump Start =========\n")); + PRINT_REG((" Start command count=0x%x\n", hNand->StartCommandCount)); +#if NV_OAL + // bootloader version of print does not support %8.8x + PRINT_REG((" NAND_COMMAND = 0x%x\n", Nand_REGR(hNand, COMMAND))); + PRINT_REG((" NAND_STATUS = 0x%x\n", Nand_REGR(hNand, STATUS))); + PRINT_REG((" NAND_ISR = 0x%x\n", Nand_REGR(hNand, ISR))); + PRINT_REG((" NAND_IER = 0x%x\n", Nand_REGR(hNand, IER))); + PRINT_REG((" NAND_CONFIG = 0x%x\n", Nand_REGR(hNand, CONFIG))); + PRINT_REG((" NAND_TIMING = 0x%x\n", Nand_REGR(hNand, TIMING))); + PRINT_REG((" NAND_RESP = 0x%x\n", Nand_REGR(hNand, RESP))); + PRINT_REG((" NAND_TIMING2 = 0x%x\n", Nand_REGR(hNand, TIMING2))); + PRINT_REG((" NAND_CMD_REG1 = 0x%x\n", Nand_REGR(hNand, CMD_REG1))); + PRINT_REG((" NAND_CMD_REG2 = 0x%x\n", Nand_REGR(hNand, CMD_REG2))); + PRINT_REG((" NAND_ADDR_REG1 = 0x%x\n", Nand_REGR(hNand, ADDR_REG1))); + PRINT_REG((" NAND_ADDR_REG2 = 0x%x\n", Nand_REGR(hNand, ADDR_REG2))); + PRINT_REG((" NAND_DMA_MST_CTRL = 0x%x\n", Nand_REGR(hNand, DMA_MST_CTRL))); + PRINT_REG((" NAND_DMA_CFG.A = 0x%x\n", Nand_REGR(hNand, DMA_CFG_A))); + PRINT_REG((" NAND_DMA_CFG.B = 0x%x\n", Nand_REGR(hNand, DMA_CFG_B))); + PRINT_REG((" NAND_FIFO_CTRL = 0x%x\n", Nand_REGR(hNand, FIFO_CTRL))); + PRINT_REG((" NAND_DATA_BLOCK_PTR = 0x%x\n", Nand_REGR(hNand, DATA_BLOCK_PTR))); + PRINT_REG((" NAND_TAG_PTR = 0x%x\n", Nand_REGR(hNand, TAG_PTR))); + PRINT_REG((" NAND_ECC_PTR = 0x%x\n", Nand_REGR(hNand, ECC_PTR))); + PRINT_REG((" NAND_DEC_STATUS = 0x%x\n", Nand_REGR(hNand, DEC_STATUS))); + PRINT_REG((" NAND_HWSTATUS_CMD = 0x%x\n", Nand_REGR(hNand, HWSTATUS_CMD))); + PRINT_REG((" NAND_HWSTATUS_MASK = 0x%x\n", Nand_REGR(hNand, HWSTATUS_MASK))); + PRINT_REG((" NAND_LL_CONFIG = 0x%x\n", Nand_REGR(hNand, LL_CONFIG))); + PRINT_REG((" NAND_LL_PTR = 0x%x\n", Nand_REGR(hNand, LL_PTR))); + PRINT_REG((" NAND_LL_STATUS = 0x%x\n", Nand_REGR(hNand, LL_STATUS))); +#else + PRINT_REG((" NAND_COMMAND = 0x%8.8x\n", Nand_REGR(hNand, COMMAND))); + PRINT_REG((" NAND_STATUS = 0x%8.8x\n", Nand_REGR(hNand, STATUS))); + PRINT_REG((" NAND_ISR = 0x%8.8x\n", Nand_REGR(hNand, ISR))); + PRINT_REG((" NAND_IER = 0x%8.8x\n", Nand_REGR(hNand, IER))); + PRINT_REG((" NAND_CONFIG = 0x%8.8x\n", Nand_REGR(hNand, CONFIG))); + PRINT_REG((" NAND_TIMING = 0x%8.8x\n", Nand_REGR(hNand, TIMING))); + PRINT_REG((" NAND_RESP = 0x%8.8x\n", Nand_REGR(hNand, RESP))); + PRINT_REG((" NAND_TIMING2 = 0x%8.8x\n", Nand_REGR(hNand, TIMING2))); + PRINT_REG((" NAND_CMD_REG1 = 0x%8.8x\n", Nand_REGR(hNand, CMD_REG1))); + PRINT_REG((" NAND_CMD_REG2 = 0x%8.8x\n", Nand_REGR(hNand, CMD_REG2))); + PRINT_REG((" NAND_ADDR_REG1 = 0x%8.8x\n", Nand_REGR(hNand, ADDR_REG1))); + PRINT_REG((" NAND_ADDR_REG2 = 0x%8.8x\n", Nand_REGR(hNand, ADDR_REG2))); + PRINT_REG((" NAND_DMA_MST_CTRL = 0x%8.8x\n", Nand_REGR(hNand, DMA_MST_CTRL))); + PRINT_REG((" NAND_DMA_CFG.A = 0x%8.8x\n", Nand_REGR(hNand, DMA_CFG_A))); + PRINT_REG((" NAND_DMA_CFG.B = 0x%8.8x\n", Nand_REGR(hNand, DMA_CFG_B))); + PRINT_REG((" NAND_FIFO_CTRL = 0x%8.8x\n", Nand_REGR(hNand, FIFO_CTRL))); + PRINT_REG((" NAND_DATA_BLOCK_PTR = 0x%8.8x\n", Nand_REGR(hNand, DATA_BLOCK_PTR))); + PRINT_REG((" NAND_TAG_PTR = 0x%8.8x\n", Nand_REGR(hNand, TAG_PTR))); + PRINT_REG((" NAND_ECC_PTR = 0x%8.8x\n", Nand_REGR(hNand, ECC_PTR))); + PRINT_REG((" NAND_DEC_STATUS = 0x%8.8x\n", Nand_REGR(hNand, DEC_STATUS))); + PRINT_REG((" NAND_HWSTATUS_CMD = 0x%8.8x\n", Nand_REGR(hNand, HWSTATUS_CMD))); + PRINT_REG((" NAND_HWSTATUS_MASK = 0x%8.8x\n", Nand_REGR(hNand, HWSTATUS_MASK))); + PRINT_REG((" NAND_LL_CONFIG = 0x%8.8x\n", Nand_REGR(hNand, LL_CONFIG))); + PRINT_REG((" NAND_LL_PTR = 0x%8.8x\n", Nand_REGR(hNand, LL_PTR))); + PRINT_REG((" NAND_LL_STATUS = 0x%8.8x\n", Nand_REGR(hNand, LL_STATUS))); +#endif + PRINT_REG(("====== Register Dump End ===========\n")); +} + +static NvU32 CalcTcsVal(NvDdkNandHandle hNand, NvU32 Twp, NvU32 Twh) +{ + NvU32 TcsCntMax = 3; // TCS_CNT has 2 bits assigned in the TRM register spec. + NvBool IsSetupTimeSet; + NvOdmNandFlashParams* FP = &(hNand->FlashParams); + NvU16 MaxSetupTime = BIGGESTOF(FP->TCLS, FP->TALS, FP->TCS); + NvU16 MaxHoldTime = BIGGESTOF(FP->TCLH, FP->TALH, FP->TCH); + NvU32 TcsCnt = 0; + NvU32 Tcs = 0; + + for(TcsCnt = 0; TcsCnt <= TcsCntMax; TcsCnt ++) + { + IsSetupTimeSet = NV_FALSE; + + if((((TcsCnt + Twp + 2) * 1000000) / hNand->FreqInKhz) >=MaxSetupTime) + { + IsSetupTimeSet = NV_TRUE; + } + else + { + continue; + } + + if ((((TcsCnt + Twh + 3) * 1000000) / hNand->FreqInKhz) >=MaxHoldTime) + { + if (IsSetupTimeSet == NV_TRUE) + { + Tcs = TcsCnt; + break; + } + } + } + return Tcs; +} + +static void SetTimingRegVal(NvDdkNandHandle hNand, NvBool IsCalcRequired) +{ + NvU32 TimingRegVal = 0; + NvU32 Tcs = 0; + NvU32 Twp = 0; + NvU32 Twh = 0; + NvU32 MaxOfTrrTarTcr = 0; + NvU32 Trp = 0; + NvU32 Trp_resp = 0; + NvOdmNandFlashParams* FParams = &(hNand->FlashParams); + // This Macro Converts time in nano seconds to cycle count bitfield value. + // The 't' comes in nano seconds. + // Bit field Value '0' means '1' cycle. So, subtract '1'. + if (IsCalcRequired) + { + #define CNT(t) \ + (((((t) * hNand->FreqInKhz) + 1000000 - 1) / 1000000) - 1) + // calculating Max of TRR_TAR_TCR + MaxOfTrrTarTcr = BIGGESTOF(FParams->TCR, FParams->TAR, FParams->TRR); + // Calculate Trp and Trp_resp values + // Trp:: EDO mode: tRP timing from flash datasheet + // Trp:: Non-EDO mode: Max(tRP, tREA) timing + 13ns (round trip delay) + if (hNand->NandCapability.IsEdoModeSupported) + { + Trp = FParams->TRP; + Trp_resp = FParams->TREA; + } + else + { + Trp = BIGGEROF(FParams->TRP, FParams->TREA) + MAX_ROUND_TRIP_DELAY; + Trp_resp = Trp; + } + // Adjust Trp for TRC <= (TRP + TRH) + if (FParams->TRC > (Trp + FParams->TRH)) + { + Trp = FParams->TRC - FParams->TRH; + } + // Adjust Twp for TWC <= (TWP + TWH) + if (FParams->TWC > (FParams->TWP + FParams->TWH)) + { + FParams->TWP = FParams->TWC - FParams->TWH; + } + // Calculating Tcs + Twp = CNT(FParams->TWP); + Twh = CNT(FParams->TWH); + Tcs = CalcTcsVal(hNand, Twp, Twh); + + TimingRegVal = NV_DRF_NUM(NAND, TIMING, TRP_RESP_CNT, CNT(Trp_resp)) | + NV_DRF_NUM(NAND, TIMING, TWB_CNT, CNT(FParams->TWB)) | + NV_DRF_NUM(NAND, TIMING, TCR_TAR_TRR_CNT, + (CNT(MaxOfTrrTarTcr) - 2))| + NV_DRF_NUM(NAND, TIMING, TWHR_CNT, CNT(FParams->TWHR)) | + NV_DRF_NUM(NAND, TIMING, TCS_CNT, Tcs) | + NV_DRF_NUM(NAND, TIMING, TWH_CNT, Twh) | + NV_DRF_NUM(NAND, TIMING, TWP_CNT, Twp) | + NV_DRF_NUM(NAND, TIMING, TRH_CNT, CNT(FParams->TRH)) | + NV_DRF_NUM(NAND, TIMING, TRP_CNT, CNT(Trp)); + hNand->OptimumTiming = TimingRegVal; + hNand->OptimumTiming2 = NV_DRF_NUM(NAND, TIMING2, TADL_CNT, + (CNT(FParams->TADL) - 2)); + #undef CNT + } + // Set Nand timing reg values. + Nand_REGW(hNand, TIMING, hNand->OptimumTiming); + Nand_REGW(hNand, TIMING2, hNand->OptimumTiming2); +} + +static NvU32 GetNumOfErrorVectorBytes(NvDdkNandHandle hNand) +{ + /* + * Following are the arrays that contain the number of error vectors for + * various algorithms selected with different pages sizes (in KB) as Index. + */ + const NvU32 HammingErrorVectorBytes[] = {4, 8, 16, 0, 32}; + const NvU32 Rs4ErrorVectorBytes[] = {32, 64, 128, 0, 256}; + const NvU32 Rs6ErrorVectorBytes[] = {48, 96, 192, 0, 384}; + const NvU32 Rs8ErrorVectorBytes[] = {64, 128, 256, 0, 512}; + + NvU32 ErrorVectorIndex = 0; + NvU32 NumOfErrorVectorBytes = 0; + NvU32 MaxNumberOfCorrectableErrors = 0; + + ErrorVectorIndex = hNand->DevInfo.PageSize / 1024; + if ((hNand->EccAlgorithm == ECCAlgorithm_BCH) || + (hNand->EccAlgorithm == ECCAlgorithm_None)) + { + // for BCH Ecc algorithm vector allocation space not required + return 0; + } + else if (hNand->EccAlgorithm == ECCAlgorithm_Hamming) + { + return HammingErrorVectorBytes[ErrorVectorIndex]; + } + else if (hNand->EccAlgorithm == ECCAlgorithm_ReedSolomon) + { + if (hNand->TValue == 0) + { + MaxNumberOfCorrectableErrors = 4; + NumOfErrorVectorBytes = Rs4ErrorVectorBytes[ErrorVectorIndex]; + } + else if (hNand->TValue == 1) + { + MaxNumberOfCorrectableErrors = 6; + NumOfErrorVectorBytes = Rs6ErrorVectorBytes[ErrorVectorIndex]; + } + else if (hNand->TValue == 2) + { + MaxNumberOfCorrectableErrors = 8; + NumOfErrorVectorBytes = Rs8ErrorVectorBytes[ErrorVectorIndex]; + } + } + // Set error threshold to (MaxCorrectableErrors - 1) per every 512 + // bytes so that to know if a page is developing uncorrectable + // number of errors for the selected T-value. + hNand->ErrThreshold = MaxNumberOfCorrectableErrors - 1; + + if (NumOfErrorVectorBytes) + return NumOfErrorVectorBytes; + else + { + // If we reached here means either page size or ECC algorithm selected are + // not supported. + NV_ASSERT(NV_FALSE); + return 512; + } +} + +static NvU8 GetNumOfParityBytesForMainArea(NvDdkNandHandle hNand) +{ + const NvU8 HammingParityBytes[] = {0, + NDFLASH_PARITY_SZ_HAMMING_1024, + NDFLASH_PARITY_SZ_HAMMING_2048, + 0, + NDFLASH_PARITY_SZ_HAMMING_4096}; + const NvU8 Rs4ParityBytes[] = {0, + NDFLASH_PARITY_SZ_RS_T4_1024, + NDFLASH_PARITY_SZ_RS_T4_2048, + 0, + NDFLASH_PARITY_SZ_RS_T4_4096}; + const NvU8 Rs6ParityBytes[] = {0, + NDFLASH_PARITY_SZ_RS_T6_1024, + NDFLASH_PARITY_SZ_RS_T6_2048, + 0, + NDFLASH_PARITY_SZ_RS_T6_4096}; + const NvU8 Rs8ParityBytes[] = {0, + NDFLASH_PARITY_SZ_RS_T8_1024, + NDFLASH_PARITY_SZ_RS_T8_2048, + 0, + NDFLASH_PARITY_SZ_RS_T8_4096}; + const NvU8 Bch4ParityBytes[] = {NDFLASH_PARITY_SZ_BCH_T4_512, + 2 * NDFLASH_PARITY_SZ_BCH_T4_512, + 4 * NDFLASH_PARITY_SZ_BCH_T4_512, + 0, + 8 * NDFLASH_PARITY_SZ_BCH_T4_512}; + const NvU8 Bch8ParityBytes[] = {NDFLASH_PARITY_SZ_BCH_T8_512, + 2 * NDFLASH_PARITY_SZ_BCH_T8_512, + 4 * NDFLASH_PARITY_SZ_BCH_T8_512, + 0, + 8 * NDFLASH_PARITY_SZ_BCH_T8_512}; + const NvU8 Bch14ParityBytes[] = {NDFLASH_PARITY_SZ_BCH_T14_512, + 2 * NDFLASH_PARITY_SZ_BCH_T14_512, + 4 * NDFLASH_PARITY_SZ_BCH_T14_512, + 0, + 8 * NDFLASH_PARITY_SZ_BCH_T14_512}; + const NvU8 Bch16ParityBytes[] = {NDFLASH_PARITY_SZ_BCH_T16_512, + 2 * NDFLASH_PARITY_SZ_BCH_T16_512, + 4 * NDFLASH_PARITY_SZ_BCH_T16_512, + 0, + 8 * NDFLASH_PARITY_SZ_BCH_T16_512}; + NvU32 ParityIndex; + + NV_ASSERT(hNand->DevInfo.PageSize); + + if (hNand->EccAlgorithm == ECCAlgorithm_None) + return 0; + if (hNand->NandCapability.IsEccSupported) + { + ParityIndex = hNand->DevInfo.PageSize / 1024; + if (hNand->EccAlgorithm == ECCAlgorithm_BCH) + { + if (hNand->TValue == 0) + return Bch4ParityBytes[ParityIndex]; + else if (hNand->TValue == 1) + return Bch8ParityBytes[ParityIndex]; + else if (hNand->TValue == 2) + return Bch14ParityBytes[ParityIndex]; + else if (hNand->TValue == 3) + return Bch16ParityBytes[ParityIndex]; + } + else if (hNand->EccAlgorithm == ECCAlgorithm_Hamming) + { + return HammingParityBytes[ParityIndex]; + } + else if (hNand->EccAlgorithm == ECCAlgorithm_ReedSolomon) + { + if (hNand->TValue == 0) + return Rs4ParityBytes[ParityIndex]; + else if (hNand->TValue == 1) + return Rs6ParityBytes[ParityIndex]; + else if (hNand->TValue == 2) + return Rs8ParityBytes[ParityIndex]; + } + } + // If we reached here means either page size or ECC algorithm selected are + // not supported. + NV_ASSERT(NV_FALSE); + return 0; +} + +static void FillPageSize(NvDdkNandHandle hNand, NvU32* ConfigReg) +{ + const NvU8 PageSizeSelectArray[] = {0, 0, 1, 0, 2, 0, 0, 0, 3, + 0, 0, 0, 0, 0, 0, 0, 4}; + // Get the index by dividing by 256. + NvU8 Index = hNand->DevInfo.PageSize >> 8; + NV_ASSERT((hNand->DevInfo.PageSize > 0) && + (hNand->DevInfo.PageSize <= 4096)); + + *ConfigReg |= NV_DRF_NUM(NAND, CONFIG, PAGE_SIZE_SEL, + PageSizeSelectArray[Index]); +} + +static void ChipSelectEnable(NvU8 DeviceNumber, NvU32 *CommandReg) +{ + NvU32 CommandRegisterValue = *CommandReg; + NV_ASSERT(DeviceNumber < NDFLASH_CS_MAX); + // To clear Chip select field value. + CommandRegisterValue &= (~(0xFF << NAND_COMMAND_0_CE0_SHIFT)); + // To fill required chip select value + CommandRegisterValue |= (1 << (NAND_COMMAND_0_CE0_SHIFT + DeviceNumber)); + *CommandReg = CommandRegisterValue; +} + +static void SetCombRbsyAndEdoModes(NvDdkNandHandle hNand) +{ + NvU32 RegVal = 0; + RegVal = Nand_REGR(hNand, CONFIG); + if (hNand->IsCombRbsyMode) + RegVal |= NV_DRF_DEF(NAND, CONFIG, COM_BSY, ENABLE); + if (hNand->NandCapability.IsEdoModeSupported) + RegVal |= NV_DRF_NUM(NAND, CONFIG, EDO_MODE, 1); + Nand_REGW(hNand, CONFIG, RegVal); +} + +static void StartCqOperation(NvDdkNandHandle hNand) +{ + NvU32 RegVal = 0; + SetCombRbsyAndEdoModes(hNand); + SetupCqPkt(hNand); + // Start Command queue operation. + RegVal = Nand_REGR(hNand, LL_CONFIG); + RegVal |= NV_DRF_NUM(NAND, LL_CONFIG, LL_START, 1); + Nand_REGW(hNand, LL_CONFIG, RegVal); +} + +static void StartNandOperation(NvDdkNandHandle hNand) +{ + NvU32 RegVal = 0; + // increment command issue count + hNand->StartCommandCount++; + SetCombRbsyAndEdoModes(hNand); + // Signal nand controller start operation. + RegVal = Nand_REGR(hNand, COMMAND); + if (RegVal & NV_DRF_DEF(NAND, COMMAND, GO, ENABLE)) + { + DumpRegData(hNand); + NV_ASSERT(NV_FALSE); + } + RegVal |= NV_DRF_DEF(NAND, COMMAND, GO, ENABLE); + Nand_REGW(hNand, COMMAND, RegVal); +} + +// Set ISR & IER registers to 0. +static void CleanInterruptRegisters(NvDdkNandHandle hNand) +{ + NvU32 RegVal = 0; + + RegVal = Nand_REGR(hNand, ISR); + Nand_REGW(hNand, ISR, RegVal); + Nand_REGW(hNand, IER, 0); +} + +#if NAND_DDK_ENABLE_DMA_POLLING_MODE +static void SetupInterrupt(NvDdkNandHandle hNand, NandOperation Op) +{ +// For Polling nothing to be done +} +#else +static void SetupInterrupt(NvDdkNandHandle hNand, NandOperation Op) +{ + NvU32 RegVal = 0; + NvU32 IerReg = 0; + + CleanInterruptRegisters(hNand); + // Enalbe Global interrupt enable bit. + IerReg = NV_DRF_NUM(NAND, IER, GIE, 1) | + NV_DRF_NUM(NAND, IER, IE_UND, 1) | + NV_DRF_NUM(NAND, IER, IE_OVR, 1); + if (hNand->EccAlgorithm == ECCAlgorithm_ReedSolomon) + IerReg |= NV_DRF_NUM(NAND, IER, ERR_TRIG_VAL, hNand->ErrThreshold); + + if (hNand->IsCommandQueueOperation) + { + IerReg |= NV_DRF_NUM(NAND, IER, IE_LL_DONE, 1) | + NV_DRF_NUM(NAND, IER, IE_LL_ERR, 1) | + NV_DRF_NUM(NAND, IER, IE_ECC_ERR, 1); + } + else + { + if (Op == NandOperation_Read) + IerReg |= NV_DRF_NUM(NAND, IER, IE_ECC_ERR, 1); + IerReg |= NV_DRF_NUM(NAND, IER, IE_CMD_DONE, 1); + } + if (hNand->NumberOfAperturesUsed) + RegVal |= NV_DRF_NUM(NAND, LOCK_CONTROL, IE_LOCK_ERR, 1); + Nand_REGW(hNand, IER, IerReg); +} +#endif + +static NvError EnableNandPower(NvDdkNandHandle hNand) +{ + NvError e = NvSuccess; + /* Enable power for Nand module */ + NV_CHECK_ERROR(NvRmPowerVoltageControl(hNand->RmDevHandle, + NvRmModuleID_Nand, hNand->RmPowerClientId, NvRmVoltsUnspecified, + NvRmVoltsUnspecified, NULL, 0, NULL)); + NandPowerRailEnable(hNand, NV_TRUE); + return e; +} + +static NvError EnableNandClock(NvDdkNandHandle hNand) +{ + NvError e; + // Add any more frequencies required here. + const NvRmFreqKHz PrefFreqList[] = {130000, 108000, 80000, 72000, 48000, + 24000, 12000, 8300, NvRmFreqUnspecified}; + NvU32 ListCount = NV_ARRAY_SIZE(PrefFreqList); + NvRmFreqKHz CurrentFreq = 0; + + // Enable clock to Nand controller + NV_CHECK_ERROR(NvRmPowerModuleClockControl(hNand->RmDevHandle, + NvRmModuleID_Nand, hNand->RmPowerClientId, NV_TRUE)); + + // Request for clk + NV_CHECK_ERROR(NvRmPowerModuleClockConfig(hNand->RmDevHandle, + NvRmModuleID_Nand, hNand->RmPowerClientId, PrefFreqList[ListCount - 2], + PrefFreqList[0], PrefFreqList, ListCount, &CurrentFreq, 0)); + hNand->FreqInKhz = CurrentFreq; + return e; +} + +static NvError NvDdkNandPrivSetPinMux(NvDdkNandHandle hNand) +{ + NvError e = NvError_BadValue; + NvU32 *pPinMuxConfigTable = NULL; + NvU32 Count = 0; + NvRmModuleNandInterfaceCaps InterfaceCaps; + + NV_ASSERT(hNand); + NvOdmQueryPinMux(NvOdmIoModule_Nand, (const NvU32 **)&pPinMuxConfigTable, + &Count); + NV_ASSERT(pPinMuxConfigTable); + + if (Count != 0) + { + NV_ASSERT_SUCCESS(NvRmGetModuleInterfaceCapabilities( + hNand->RmDevHandle, + NVRM_MODULE_ID(NvRmModuleID_Nand,0), + sizeof(NvRmModuleNandInterfaceCaps), &InterfaceCaps)); + hNand->IsCombRbsyMode = InterfaceCaps.IsCombRbsyMode; + hNand->NandBusWidth = InterfaceCaps.NandInterfaceWidth; + + e= NvRmSetModuleTristate(hNand->RmDevHandle, + NVRM_MODULE_ID(NvRmModuleID_Nand,0), + NV_FALSE); + } + return e; +} + +static NvError InitNandController(NvDdkNandHandle hNand) +{ + NvError e; + + e = NvDdkNandPrivSetPinMux(hNand); + if ((e != NvSuccess) && (e != NvError_NotSupported)) + { + return e; + } + // Disable write protect. + e = NandDisableWriteProtect(hNand); + // Addresses for write protect disable are finalised.in case of AP15. + if ((e != NvSuccess) && (e != NvError_NotSupported)) + { + return e; + } + return e; +} + +static void SetupDMA(NvDdkNandHandle hNand) +{ + NandParams* p = &hNand->Params; + NvU32 NumOfBytesData = 0; + NvU32 ConfigReg = 0; + NvU32 DmaMasterCtlReg = 0; + NvU32 DmaConfigAReg = 0; + NvU32 DmaConfigBReg = 0; + NvU32 DataBlockPtrReg = 0; + NvU32 TagBlockPtrReg = 0; + NvU32 TagBytes; + NvU32 BchConfigReg = 0; + + DmaMasterCtlReg = NV_DRF_DEF(NAND, DMA_MST_CTRL, BURST_SIZE, BURST_8WORDS) | + NV_DRF_NUM(NAND, DMA_MST_CTRL, DMA_PERF_EN, 1); + if (p->OperationName == NandOperation_Write) + DmaMasterCtlReg |= NV_DRF_NUM(NAND, DMA_MST_CTRL, DIR, 1); + else + DmaMasterCtlReg |= NV_DRF_NUM(NAND, DMA_MST_CTRL, REUSE_BUFFER, 1); + // Setup Configuration register + + if (hNand->EccAlgorithm == ECCAlgorithm_BCH) + { + NumOfBytesData = (hNand->DevInfo.PageSize) * p->NumberOfPages; + // setting DMA data transfer size + DmaConfigAReg |= NV_DRF_NUM(NAND, DMA_CFG_A, DMA_BLOCK_SIZE_A, + (NumOfBytesData - 1)); + // Setting DMA data buffer ptr. + DataBlockPtrReg = (NvU32)hNand->DataBuffer.PhysBuffer; + // To enable Main Page Data transfer by DMA. + DmaMasterCtlReg |= NV_DRF_NUM(NAND, DMA_MST_CTRL, DMA_EN_A, 1); + + // Enable skip bit + if (hNand->FlashParams.SkippedSpareBytes != + NvOdmNandSkipSpareBytes_0) + { + ConfigReg |= NV_DRF_NUM(NAND, CONFIG, SKIP_SPARE, 1) | + NV_DRF_NUM(NAND, CONFIG, SKIP_SPARE_SEL, + (hNand->FlashParams.SkippedSpareBytes - 1)); + } + + TagBytes = hNand->DevInfo.TagSize - 1; + ConfigReg |= NV_DRF_NUM(NAND, CONFIG, TAG_BYTE_SIZE, TagBytes); + if (p->OperationName == NandOperation_Read) + { + TagBytes = ((p->NumberOfPages * (hNand->DevInfo.TagSize + + (hNand->FlashParams.SkippedSpareBytes << 2))) - 1); + } + else + TagBytes = ((p->NumberOfPages * hNand->DevInfo.TagSize) - 1); + DmaConfigBReg |= NV_DRF_NUM(NAND, DMA_CFG_B, DMA_BLOCK_SIZE_B, + TagBytes); + // Set TAG pointer. + TagBlockPtrReg = (NvU32)hNand->TagBuffer.PhysBuffer; + // To enable Spare Data transfer by DMA. + DmaMasterCtlReg |= NV_DRF_NUM(NAND, DMA_MST_CTRL, DMA_EN_B, 1); + } + else // RS or Hamming + { + if (p->pDataBuffer) + { + NumOfBytesData = (hNand->DevInfo.PageSize) * p->NumberOfPages; + // setting DMA data transfer size + DmaConfigAReg |= NV_DRF_NUM(NAND, DMA_CFG_A, DMA_BLOCK_SIZE_A, + (NumOfBytesData - 1)); + // Setting DMA data buffer ptr. + DataBlockPtrReg = (NvU32)hNand->DataBuffer.PhysBuffer; + // To enable Main Page Data transfer by DMA. + DmaMasterCtlReg |= NV_DRF_NUM(NAND, DMA_MST_CTRL, DMA_EN_A, 1); + + // Enable skip bit + if (hNand->FlashParams.SkippedSpareBytes != + NvOdmNandSkipSpareBytes_0) + { + ConfigReg |= NV_DRF_NUM(NAND, CONFIG, SKIP_SPARE, 1) | + NV_DRF_NUM(NAND, CONFIG, SKIP_SPARE_SEL, + (hNand->FlashParams.SkippedSpareBytes - 1)); + } + } + + if (p->pTagBuffer) + { + if (hNand->NandCapability.IsEccSupported) + TagBytes = hNand->DevInfo.TagSize + + NDFLASH_PARITY_SZ_HAMMING_SPARE - 1; + else + TagBytes = hNand->DevInfo.TagSize - 1; + if (p->NumSpareAreaBytes) + // We are trying to read/write spare area. + TagBytes = p->NumSpareAreaBytes - 1; + ConfigReg |= NV_DRF_NUM(NAND, CONFIG, TAG_BYTE_SIZE, TagBytes); + + if (p->OperationName == NandOperation_Read) + { + if (hNand->NandCapability.IsEccSupported) + { + TagBytes = ((p->NumberOfPages * (hNand->DevInfo.TagSize + + NDFLASH_PARITY_SZ_HAMMING_SPARE)) - 1); + } + else + TagBytes = ((p->NumberOfPages * hNand->DevInfo.TagSize) - 1); + + // Add Skip Spare bytes.when page data also needs to be read. + if (p->pDataBuffer) + { + TagBytes += ((hNand->FlashParams.SkippedSpareBytes << 2) * + p->NumberOfPages); + } + } + else + { + TagBytes = (p->NumberOfPages * hNand->DevInfo.TagSize) - 1; + } + if (p->NumSpareAreaBytes) + // We are trying to read/write spare area. + TagBytes = p->NumSpareAreaBytes - 1; + + DmaConfigBReg |= NV_DRF_NUM(NAND, DMA_CFG_B, DMA_BLOCK_SIZE_B, + TagBytes); + // Set TAG pointer. + TagBlockPtrReg = (NvU32)hNand->TagBuffer.PhysBuffer; + // To enable Spare Data transfer by DMA. + DmaMasterCtlReg |= NV_DRF_NUM(NAND, DMA_MST_CTRL, DMA_EN_B, 1); + } + } + // Set config reg params here. + if ((hNand->NandBusWidth == 16) && (hNand->DevInfo.BusWidth == 16)) + ConfigReg |= NV_DRF_DEF(NAND, CONFIG, BUS_WIDTH, BUS_WIDTH_16); + else + ConfigReg |= NV_DRF_DEF(NAND, CONFIG, BUS_WIDTH, BUS_WIDTH_8); + + if (hNand->NandCapability.IsEccSupported == NV_TRUE) + { + if (hNand->EccAlgorithm != ECCAlgorithm_BCH) + { + if (p->OperationName == NandOperation_Read) + ConfigReg |= NV_DRF_NUM(NAND, CONFIG, HW_ERR_CORRECTION, 1); + ConfigReg |= NV_DRF_NUM(NAND, CONFIG, TVALUE, hNand->TValue); + if (hNand->TValue == 0) + ConfigReg |= NV_DRF_DEF(NAND, CONFIG, TVALUE, TVAL4); + else if (hNand->TValue == 1) + ConfigReg |= NV_DRF_DEF(NAND, CONFIG, TVALUE, TVAL6); + if (hNand->TValue == 2) + ConfigReg |= NV_DRF_DEF(NAND, CONFIG, TVALUE, TVAL8); + + if (p->pDataBuffer) + { + ConfigReg |= NV_DRF_NUM(NAND, CONFIG, HW_ECC, 1); + } + if (p->pTagBuffer) + { + if (p->NumSpareAreaBytes == 0) + ConfigReg |= NV_DRF_NUM(NAND, CONFIG, ECC_EN_TAG, 1); + } + // Enable reed_solomon algorithm by default + ConfigReg |= NV_DRF_NUM(NAND, CONFIG, ECC_SEL, hNand->EccAlgorithm); + } + ConfigReg |= NV_DRF_NUM(NAND, CONFIG, ECC_SEL, hNand->EccAlgorithm); + } + + FillPageSize(hNand, &ConfigReg); + ConfigReg |= NV_DRF_NUM(NAND, CONFIG, PIPELINE_EN, 1); + // Configure DMA MST Cntrl register. + DmaMasterCtlReg |= NV_DRF_NUM(NAND, DMA_MST_CTRL, IS_DMA_DONE, 1) | + NV_DRF_NUM(NAND, DMA_MST_CTRL, IE_DMA_DONE, 1); + if (!hNand->IsCommandQueueOperation) + DmaMasterCtlReg |= NV_DRF_NUM(NAND, DMA_MST_CTRL, DMA_GO, 1); + // Finally, Write all required registers. + // Set ECC buffer pointer. + Nand_REGW(hNand, ECC_PTR, (NvU32)hNand->EccBuffer.PhysBuffer); + Nand_REGW(hNand, DATA_BLOCK_PTR, DataBlockPtrReg); + Nand_REGW(hNand, TAG_PTR, TagBlockPtrReg); + Nand_REGW(hNand, DMA_CFG_A, DmaConfigAReg); + Nand_REGW(hNand, DMA_CFG_B, DmaConfigBReg); + Nand_REGW(hNand, BCH_CONFIG, BchConfigReg); + Nand_REGW(hNand, CONFIG, ConfigReg); + Nand_REGW(hNand, DMA_MST_CTRL, DmaMasterCtlReg); +} + +static void SetupAddressAndDeviceReg( + NvDdkNandHandle hNand, + NvU32 DevNum, + NvU32 StartPageNumber) +{ + NandParams *p = &hNand->Params; + NvU32 CommandReg = 0; + + // Setup Address Registers. + if (p->OperationName != NandOperation_Erase) + { + Nand_REGW(hNand, ADDR_REG1, (p->ColumnNumber | + (StartPageNumber << NAND_ADDR_REG1_0_ADDR_BYTE2_SHIFT))); + Nand_REGW(hNand, ADDR_REG2, + (StartPageNumber >> NAND_ADDR_REG1_0_ADDR_BYTE2_SHIFT)); + } + CommandReg = Nand_REGR(hNand, COMMAND); + ChipSelectEnable(DevNum, &CommandReg); + Nand_REGW(hNand, COMMAND, CommandReg); +} + +static void +SetupRegisters( + NvDdkNandHandle hNand, + NandOperation Op) +{ + NvU32 CommandReg = 0; + NvU32 StatusMaskReg = 0; + NvU32 CommandReg1 = 0; + NvU32 CommandReg2 = 0; + NvU32 AddressReg1 = 0; + NvU32 AddressReg2 = 0; + NvU32 ConfigReg = 0; + NvU32 StatusCommandReg = NvOdmNandCommandList_Status; + NandParams *p = &hNand->Params; + + StatusMaskReg = NV_DRF_NUM(NAND, HWSTATUS_MASK, RDSTATUS_MASK, 1)| + NV_DRF_NUM(NAND, HWSTATUS_MASK, RDSTATUS_EXP_VAL, 0)| + NV_DRF_NUM(NAND, HWSTATUS_MASK, RBSY_MASK, + hNand->FlashParams.OperationSuccessStatus)| + NV_DRF_NUM(NAND, HWSTATUS_MASK, RBSY_EXP_VAL, + hNand->FlashParams.OperationSuccessStatus); + + if (Op == NandOperation_Read) + { + CommandReg1 = NvOdmNandCommandList_Read; + CommandReg2 = NvOdmNandCommandList_Read_Start; + // Setup required bits. + CommandReg |= NV_DRF_NUM(NAND, COMMAND, ALE, 1)| + NV_DRF_NUM(NAND, COMMAND, CLE, 1)| + NV_DRF_NUM(NAND, COMMAND, RX, 1)| + NV_DRF_NUM(NAND, COMMAND, SEC_CMD, 1)| + NV_DRF_DEF(NAND, COMMAND, ALE_BYTE_SIZE, ALE_BYTES5)| + NV_DRF_NUM(NAND, COMMAND, RBSY_CHK, 1); + if (hNand->EccAlgorithm == ECCAlgorithm_BCH) + { + CommandReg |= NV_DRF_NUM(NAND, COMMAND, B_VALID, 1); + CommandReg |= NV_DRF_NUM(NAND, COMMAND, A_VALID, 1)| + NV_DRF_DEF(NAND, COMMAND, TRANS_SIZE, BYTES_PAGE_SIZE_SEL); + } + else + { + if (p->pTagBuffer) + { + CommandReg |= NV_DRF_NUM(NAND, COMMAND, B_VALID, 1); + } + if (p->pDataBuffer) + { + CommandReg |= NV_DRF_NUM(NAND, COMMAND, A_VALID, 1)| + NV_DRF_DEF(NAND, COMMAND, TRANS_SIZE, BYTES_PAGE_SIZE_SEL); + } + } + } + else if (Op == NandOperation_ReadParamPage) + { + CommandReg1 = NvOdmNandCommandList_ONFIReadId; + // Setup required bits. + CommandReg |= NV_DRF_NUM(NAND, COMMAND, ALE, 1)| + NV_DRF_NUM(NAND, COMMAND, CLE, 1)| + NV_DRF_DEF(NAND, COMMAND, ALE_BYTE_SIZE, ALE_BYTES1); + } + else if(Op == NandOperation_DataCyclesAlone) + { + CommandReg = NV_DRF_NUM(NAND, COMMAND, A_VALID, 1)| + NV_DRF_NUM(NAND, COMMAND, RX, 1)| + NV_DRF_NUM(NAND, COMMAND, RBSY_CHK, 1)| + NV_DRF_DEF(NAND, COMMAND, TRANS_SIZE, BYTES_PAGE_SIZE_SEL); + } + else if (Op == NandOperation_Write) + { + CommandReg1 = NvOdmNandCommandList_Page_Program; + CommandReg2 = NvOdmNandCommandList_Page_Program_Start; + // Setup required bits + CommandReg |= NV_DRF_NUM(NAND, COMMAND, ALE, 1)| + NV_DRF_NUM(NAND, COMMAND, CLE, 1)| + NV_DRF_NUM(NAND, COMMAND, TX, 1)| + NV_DRF_NUM(NAND, COMMAND, SEC_CMD, 1)| + NV_DRF_NUM(NAND, COMMAND, AFT_DAT, 1)| + NV_DRF_DEF(NAND, COMMAND, ALE_BYTE_SIZE, ALE_BYTES5)| + NV_DRF_NUM(NAND, COMMAND, RBSY_CHK, 1); + if (hNand->EccAlgorithm == ECCAlgorithm_BCH) + { + CommandReg |= NV_DRF_NUM(NAND, COMMAND, B_VALID, 1); + CommandReg |= NV_DRF_NUM(NAND, COMMAND, A_VALID, 1)| + NV_DRF_DEF(NAND, COMMAND, TRANS_SIZE, BYTES_PAGE_SIZE_SEL); + } + else + { + if (p->pTagBuffer) + { + CommandReg |= NV_DRF_NUM(NAND, COMMAND, B_VALID, 1); + } + if (p->pDataBuffer) + { + CommandReg |= NV_DRF_NUM(NAND, COMMAND, A_VALID, 1)| + NV_DRF_DEF(NAND, COMMAND, TRANS_SIZE, BYTES_PAGE_SIZE_SEL); + } + } + } + else if (Op == NandOperation_Erase) + { + CommandReg1 = NvOdmNandCommandList_Block_Erase; + CommandReg2 = NvOdmNandCommandList_Block_Erase_Start; + // Setup required bits. + CommandReg |= NV_DRF_NUM(NAND, COMMAND, ALE, 1) | + NV_DRF_NUM(NAND, COMMAND, CLE, 1) | + NV_DRF_NUM(NAND, COMMAND, SEC_CMD, 1) | + // Erase needs only 3 address cycles.to access the block. + NV_DRF_DEF(NAND, COMMAND, ALE_BYTE_SIZE, ALE_BYTES3) | + // Wait for chip to be ready. + NV_DRF_NUM(NAND, COMMAND, RBSY_CHK, 1); + // Setup Address Registers. + AddressReg1 = p->StartPageNumber; + } + else if (Op == NandOperation_GetStatus) + { + CommandReg1 = NvOdmNandCommandList_Status; + // Setup required bits. + CommandReg |= NV_DRF_NUM(NAND, COMMAND, CLE, 1)| + NV_DRF_NUM(NAND, COMMAND, RX, 1)| + NV_DRF_NUM(NAND, COMMAND, PIO, 1)| + // Wait for chip to be ready + NV_DRF_NUM(NAND, COMMAND, RBSY_CHK, 1); + } + else if (Op == NandOperation_Reset) + { + CommandReg1 = NvOdmNandCommandList_Reset; + // Setup required bits. + CommandReg |= NV_DRF_NUM(NAND, COMMAND, CLE, 1); + } + else if (Op == NandOperation_ReadId) + { + CommandReg1 = NvOdmNandCommandList_Read_Id; + // Setup required bits. + CommandReg |= NV_DRF_NUM(NAND, COMMAND, ALE, 1)| + NV_DRF_NUM(NAND, COMMAND, CLE, 1)| + NV_DRF_NUM(NAND, COMMAND, RX, 1)| + NV_DRF_NUM(NAND, COMMAND, PIO, 1)| + // Only 4 bytes are read as part of read ID + NV_DRF_DEF(NAND, COMMAND, TRANS_SIZE, BYTES4); + } + else if (Op == NandOperation_CopybackRead) + { + CommandReg1 = NvOdmNandCommandList_Read_Cpy_Bck; + CommandReg2 = NvOdmNandCommandList_Read_Cpy_Bck_Start; + // Setup required bits. + CommandReg |= NV_DRF_NUM(NAND, COMMAND, ALE, 1)| + NV_DRF_NUM(NAND, COMMAND, CLE, 1)| + NV_DRF_NUM(NAND, COMMAND, SEC_CMD, 1)| + NV_DRF_DEF(NAND, COMMAND, ALE_BYTE_SIZE, ALE_BYTES5)| + NV_DRF_NUM(NAND, COMMAND, RBSY_CHK, 1); + FillPageSize(hNand, &ConfigReg); + } + else if (Op == NandOperation_CopybackProgram) + { + CommandReg1 = NvOdmNandCommandList_Copy_Back; + CommandReg2 = NvOdmNandCommandList_Page_Program_Start; + // Setup required bits + CommandReg |= NV_DRF_NUM(NAND, COMMAND, ALE, 1)| + NV_DRF_NUM(NAND, COMMAND, CLE, 1)| + NV_DRF_NUM(NAND, COMMAND, SEC_CMD, 1)| + NV_DRF_DEF(NAND, COMMAND, ALE_BYTE_SIZE, ALE_BYTES5)| + NV_DRF_NUM(NAND, COMMAND, RBSY_CHK, 1); + FillPageSize(hNand, &ConfigReg); + } + + if ((Op != NandOperation_Read) && (Op != NandOperation_Write) && + (Op != NandOperation_GetStatus)) + { + Nand_REGW(hNand, CONFIG, ConfigReg); + } + Nand_REGW(hNand, ADDR_REG1, AddressReg1); + Nand_REGW(hNand, ADDR_REG2, AddressReg2); + Nand_REGW(hNand, CMD_REG1, CommandReg1); + Nand_REGW(hNand, CMD_REG2, CommandReg2); + Nand_REGW(hNand, HWSTATUS_CMD, StatusCommandReg); + Nand_REGW(hNand, HWSTATUS_MASK, StatusMaskReg); + Nand_REGW(hNand, COMMAND, CommandReg); +} + +static void +SetCommandQueueOperationState( + NvDdkNandHandle hNand, + NvU32 NumberOfPages, + NandParams *p) +{ + hNand->IsCommandQueueOperation = NV_FALSE; + if (p) + { + // For reading Tag info alone, we don't do cq mode. + if (hNand->NandCapability.IsCommandQueueModeSupported && + (p->pTagBuffer == NULL) && (p->NumberOfPages > 1)) + hNand->IsCommandQueueOperation = NV_TRUE; + } +} + +static NvU32 GetColumnNumber(NvDdkNandHandle hNand) +{ + NvU32 ColumnNumber = 0; + NvU32 ParityBytes = 0; + NandParams *p = &hNand->Params; + if (hNand->EccAlgorithm != ECCAlgorithm_BCH) + { + ParityBytes = GetNumOfParityBytesForMainArea(hNand); + if ((!p->pDataBuffer) && p->pTagBuffer) + { + // Column Number = Page Size + Parity bytes (in case RS/ Hamming are + // selected).+ Skipped Bytes; + ColumnNumber = hNand->DevInfo.PageSize + ParityBytes + + (hNand->FlashParams.SkippedSpareBytes << 2); + } + // If Flash is of 16 bit bus width, divide column Number by 2. + if (hNand->DevInfo.BusWidth == 16) + ColumnNumber = ColumnNumber >> 1; + } + return ColumnNumber; +} + +static void GetNumOfCsInterleaved(NvDdkNandHandle hNand, NvU32 *pPageNumbers) +{ + NvU32 i = 0; + hNand->NumberOfChipsToBeInterleaved = 0; + for (i = 0; i < NDFLASH_CS_MAX; i++) + { + if (pPageNumbers[i] != 0xFFFFFFFF) + { + hNand->NumberOfChipsToBeInterleaved++; + } + } + NV_ASSERT(hNand->NumberOfChipsToBeInterleaved <= hNand->NumOfActiveDevices); +} + +static NvError WaitForCqDone(NvDdkNandHandle hNand) +{ + NvError Error; +#if !NAND_DDK_ENABLE_DMA_POLLING_MODE + NandParams *p = &hNand->Params; + NvU32 CqConfig; + NvU32 CqGo; + NvU32 CqMaxWaitTime = p->WaitTimeoutInMilliSeconds * + hNand->MaxNumOfPagesPerDMARequest; +#endif +#if NAND_DDK_ENABLE_COMMAND_POLLING_MODE + Error = NandWaitCqDone(hNand); +#else + Error = NvOsSemaphoreWaitTimeout(hNand->CommandDoneSema, CqMaxWaitTime); + if (Error == NvError_Timeout) + { + CqConfig = Nand_REGR(hNand, LL_CONFIG); + CqGo = NV_DRF_VAL(NAND, LL_CONFIG, LL_START, CqConfig); + if (CqGo == 0) + Error = NvSuccess; + } +#endif + NAND_ASSERT(Error); + if (Error != NvSuccess) + { + DumpRegData(hNand); + return Error; + } + if (hNand->IsCqError) + { + Error = NvError_NandCommandQueueError; + hNand->IsCqError = NV_FALSE; + DumpRegData(hNand); + NV_ASSERT("Command Queue Error in Nand HW"); + } + return Error; +} + +static NvError WaitForDmaDone(NvDdkNandHandle hNand) +{ + NvError e = NvSuccess; +#if !NAND_DDK_ENABLE_DMA_POLLING_MODE + NandParams *p = &hNand->Params; + NvU32 DmaMasterControl; + NvU32 DmaGo; +#endif + if (!hNand->IsCommandQueueOperation) + { + #if NAND_DDK_ENABLE_DMA_POLLING_MODE + e = NandWaitDmaDone(hNand); + #else + e = NvOsSemaphoreWaitTimeout(hNand->DmaDoneSema, + p->WaitTimeoutInMilliSeconds); + if (e == NvError_Timeout) + { + DmaMasterControl = Nand_REGR(hNand, DMA_MST_CTRL); + DmaGo = NV_DRF_VAL(NAND, DMA_MST_CTRL, DMA_GO, DmaMasterControl); + if (DmaGo == 0) + e = NvSuccess; + } + #endif + NAND_ASSERT(e); + if (e != NvSuccess) + { + DumpRegData(hNand); + } + } + return e; +} + +static NvError WaitForCommandDone(NvDdkNandHandle hNand) +{ + NvError e = NvSuccess; + #if !NAND_DDK_ENABLE_COMMAND_POLLING_MODE + NandParams *p = &hNand->Params; + NvU32 CommandReg; + NvU32 CommandGo; + #endif + + if (!hNand->IsCommandQueueOperation) + { + #if NAND_DDK_ENABLE_COMMAND_POLLING_MODE + e = NandWaitCommandDone(hNand); + #else + e = NvOsSemaphoreWaitTimeout(hNand->CommandDoneSema, + p->WaitTimeoutInMilliSeconds); + if (e == NvError_Timeout) + { + CommandReg = Nand_REGR(hNand, COMMAND); + CommandGo = NV_DRF_VAL(NAND, COMMAND, GO, CommandReg); + if (CommandGo == 0) + e = NvSuccess; + } + #endif + NAND_ASSERT(e); + if (e != NvSuccess) + { + DumpRegData(hNand); + } + } + return e; +} + +static void +SkipUnusedDevices(NvDdkNandHandle hNand, + NvU32* pPageNumbers, + NvU8* pStartDeviceNum, + NvU32* pOffset) +{ + NvU8 StartDeviceNum = *pStartDeviceNum; + NvU8 Count = 0; + while (pPageNumbers[StartDeviceNum] == 0xFFFFFFFF) + { + StartDeviceNum++; + if (StartDeviceNum >= NDFLASH_CS_MAX) + { + StartDeviceNum = 0; + if (pOffset) + *pOffset = *pOffset + 1; + } + Count++; + // If follwing ASSERT hits, then none of the devices are filled with + // valid page numbers. + if (Count >= NDFLASH_CS_MAX) + NV_ASSERT(NV_FALSE); + } + *pStartDeviceNum = StartDeviceNum; +} + +// command queue read operation +static NvError CommandQueueRead(NvDdkNandHandle hNand, NvU32* pPageNumOffset) +{ + NandParams *p = &hNand->Params; + NvError e = NvSuccess; + NvU8 DeviceNumber = 0; + NvU32 PageNumber = 0; + + SkipUnusedDevices(hNand, p->pStartPageNumbers, + &(p->DeviceNumber), pPageNumOffset); + DeviceNumber = hNand->PhysicalDeviceNumber[p->DeviceNumber]; + PageNumber = p->pStartPageNumbers[p->DeviceNumber]; + #if NAND_DISPLAY_ALL + if (DebugPrintEnable) + { + PRINT_ALL(("\nRd DevNum = %d, PageNum = %d", + DeviceNumber, (PageNumber + (*pPageNumOffset)))); + } + #endif + // Setup all registers required for main area read here. + SetupAddressAndDeviceReg(hNand, DeviceNumber, + (PageNumber + (*pPageNumOffset))); + // Set Command queue buffer and start the data transfers + StartCqOperation(hNand); + + e = WaitForCqDone(hNand); + if (e != NvSuccess) + { + return e; + } + (*pPageNumOffset) += + (p->NumberOfPages / hNand->NumberOfChipsToBeInterleaved); + p->DeviceNumber += + (p->NumberOfPages % hNand->NumberOfChipsToBeInterleaved); + do + { + p->DeviceNumber++; + if (p->DeviceNumber >= NDFLASH_CS_MAX) + { + p->DeviceNumber = 0; + } + } + while(p->pStartPageNumbers[p->DeviceNumber] == 0xFFFFFFFF); + p->NumberOfPagesCompleted += p->NumberOfPages; + + // Wait till DMA done. This is only for non-command queue mode. + // For Command queue mode, this function just returns back. + NV_CHECK_ERROR_CLEANUP(WaitForDmaDone(hNand)); + // Shift the data buffer pointer by p->NumberOfPages. + if ((p->pDataBuffer != NULL) && + (p->pDataBuffer !=hNand->DataBuffer.pVirtualBuffer)) + { + NvOsMemcpy(p->pDataBuffer, hNand->DataBuffer.pVirtualBuffer, + (hNand->DevInfo.PageSize) * (p->NumberOfPages)); + p->pDataBuffer += (hNand->DevInfo.PageSize) * + (p->NumberOfPages); + } + + return NvSuccess; +fail: + return e; +} + +// Normal non-command queue read operation +static NvError NonCQRead(NvDdkNandHandle hNand, NvU32* pPageNumOffset) +{ + NandParams *p = &hNand->Params; + NvError e = NvSuccess; + NvU32 i = 0; + NvU32 j = 0; + NvU8 DeviceNumber = 0; + NvU8 NumberOfPages = 0; + NvU32 PageNumber = 0; + NvU8 *pTagBuf = NULL; + NvU8* pBuf = hNand->DataBuffer.pVirtualBuffer; + #if NAND_DDK_ENABLE_COMMAND_POLLING_MODE + NvU32 IsrReg = 0; + NvU32 IsEccError =0; + #endif + + for (i = 0; i < p->NumberOfPages; i += NumberOfPages) + { + NumberOfPages = 0; + for (j = 0; j < hNand->NumberOfChipsToBeInterleaved; j++) + { + SkipUnusedDevices(hNand, p->pStartPageNumbers, + &(p->DeviceNumber), pPageNumOffset); + DeviceNumber = hNand->PhysicalDeviceNumber[p->DeviceNumber]; + PageNumber = p->pStartPageNumbers[p->DeviceNumber]; + #if NAND_DISPLAY_ALL + if (DebugPrintEnable) + { + PRINT_ALL(("\nRd DevNum = %d, PageNum = %d", + DeviceNumber, (PageNumber + (*pPageNumOffset)))); + } + #endif + // Setup all registers required for main area read here. + SetupAddressAndDeviceReg(hNand, DeviceNumber, + (PageNumber + (*pPageNumOffset))); + // Start Nand operation. + StartNandOperation(hNand); + // Copy previous page data from local buffer to OS buffer + if ((i > 0) && (p->pDataBuffer != NULL) && + (p->pDataBuffer !=hNand->DataBuffer.pVirtualBuffer)) + { + NvOsMemcpy(p->pDataBuffer, pBuf, hNand->DevInfo.PageSize); + p->pDataBuffer += (hNand->DevInfo.PageSize); + pBuf += (hNand->DevInfo.PageSize); + } + // Wait till command done. + e = WaitForCommandDone(hNand); + if (e != NvSuccess) + { + return e; + } + #if NAND_DDK_ENABLE_COMMAND_POLLING_MODE + IsrReg = Nand_REGR(hNand, ISR); + IsEccError = NV_DRF_VAL(NAND, ISR, IS_ECC_ERR, IsrReg); + if (IsEccError) + { + hNand->pEccErrorData[hNand->EccErrorCount] = + Nand_REGR(hNand, DEC_STATUS); + hNand->EccErrorCount++; + IsrReg = NV_DRF_NUM(NAND, ISR, IS_ECC_ERR, 1); + Nand_REGW(hNand, ISR, IsrReg); + } + #endif + p->NumberOfPagesCompleted++; + p->DeviceNumber++; + if (p->DeviceNumber >= NDFLASH_CS_MAX) + { + p->DeviceNumber = 0; + (*pPageNumOffset)++; + } + NumberOfPages++; + if ((i + NumberOfPages) == p->NumberOfPages) + break; + } + } + + // Wait till DMA done. This is only for non-command queue mode. + // For Command queue mode, this function just returns back. + NV_CHECK_ERROR_CLEANUP(WaitForDmaDone(hNand)); + // Shift the data buffer pointer by p->NumberOfPages. + if ((p->pDataBuffer != NULL) && + (p->pDataBuffer !=hNand->DataBuffer.pVirtualBuffer)) + { + NvU32 PageCount; + if (hNand->NumberOfChipsToBeInterleaved > p->NumberOfPages) + { + NvOsDebugPrintf("\nNandRead Error: Number of Pages=%d < " + "interleave count=%d ", p->NumberOfPages, + hNand->NumberOfChipsToBeInterleaved); + } + PageCount = (p->NumberOfPages < + hNand->NumberOfChipsToBeInterleaved)? p->NumberOfPages : + hNand->NumberOfChipsToBeInterleaved; + NvOsMemcpy(p->pDataBuffer, pBuf, + hNand->DevInfo.PageSize * PageCount); + p->pDataBuffer += (hNand->DevInfo.PageSize * PageCount); + } + if (p->pTagBuffer) + { + pTagBuf = hNand->TagBuffer.pVirtualBuffer; + for (i = 0; i < p->NumberOfPages; i++) + { + if (p->pDataBuffer != NULL) + pTagBuf += (hNand->FlashParams.SkippedSpareBytes << 2); + // user the NumSpareBytes if specified, else use the TagSize + if (p->NumSpareAreaBytes) + { + NvOsMemcpy(p->pTagBuffer, pTagBuf, p->NumSpareAreaBytes); + p->pTagBuffer += (p->NumSpareAreaBytes); + pTagBuf += (p->NumSpareAreaBytes); + } + else + { + NvOsMemcpy(p->pTagBuffer, pTagBuf, hNand->DevInfo.TagSize); + p->pTagBuffer += (hNand->DevInfo.TagSize); + pTagBuf += (hNand->DevInfo.TagSize); + } + } + } + return NvSuccess; +fail: + return e; +} + +static NvError NandRead(NvDdkNandHandle hNand, NvBool IgnoreEccError) +{ + NandParams *p = &hNand->Params; + NvU32 NumOfPagesRemaining = 0; + NvU32 PageNumberOffset = 0; + NvError e = NvSuccess; + NvU32 EccErrorPageOffset = 0; + NvU32 i = 0; + #if NAND_TIME_STAMP + NvU64 Time; + #endif + + NumOfPagesRemaining = p->NumberOfPages; + // Calculate number of CS interleaved in the current transaction + GetNumOfCsInterleaved(hNand, p->pStartPageNumbers); + + #if NAND_DISPLAY_ALL + if (DebugPrintEnable) + { + PRINT_ALL(("\nRd DevNum = %d, PageNum = %d, No. pages = %d", + p->DeviceNumber, p->pStartPageNumbers[p->DeviceNumber], + p->NumberOfPages)); + } + #endif + SetupRegisters(hNand, NandOperation_Read); + #if NAND_TIME_STAMP + Time = NvOsGetTimeUS(); + #endif + while (NumOfPagesRemaining) + { + // Calculate number of pages to be read in one DMA set up. + p->NumberOfPages = + (NumOfPagesRemaining > hNand->MaxNumOfPagesPerDMARequest) ? + hNand->MaxNumOfPagesPerDMARequest : NumOfPagesRemaining; + NumOfPagesRemaining -= p->NumberOfPages; + // In command queue mode If ECC error occurs, then command queue may + // return LL_ERROR. Hence to avoid this, in cases when IgnoreEccError is + // NV_TRUE, then use Non-command queue mode only for read operations. + if (IgnoreEccError) + hNand->IsCommandQueueOperation = NV_FALSE; + else + { + #if IS_CQ_ENABLED + SetCommandQueueOperationState(hNand, p->NumberOfPages, p); + #else + hNand->IsCommandQueueOperation = NV_FALSE; + #endif + } + SetupInterrupt(hNand, NandOperation_Read); + hNand->EccErrorCount = 0; + // Setup DMA upto maximum data size that can be transferrable. + SetupDMA(hNand); + if (hNand->IsCommandQueueOperation) + e = CommandQueueRead(hNand, &PageNumberOffset); + else + e = NonCQRead(hNand, &PageNumberOffset); + if (!IgnoreEccError) + NV_CHECK_ERROR_CLEANUP( + NandCheckForEccError(hNand, &EccErrorPageOffset)); + } + #if NAND_TIME_STAMP + Time = NvOsGetTimeUS() - Time; + if (DebugPrintEnable) + { + PRINT_ALL(("\r\ntms Read time = %dus, pc = %d", Time, p->NumberOfPages)); + } + #endif +fail: + if (e != NvSuccess) + { + for (i = 0; i < 8; i++) + { + if (p->pStartPageNumbers[i] != 0xFFFFFFFF) + NvOsDebugPrintf("\n Chip: %d, Page = %d\n", i, p->pStartPageNumbers[i]); + } + } + // Don't assert for ECC failure + if (e != NvError_NandReadEccFailed) + { + NAND_ASSERT(e); + } + else + DumpRegData(hNand); + if (e == NvError_Timeout) + { + DumpRegData(hNand); + NvRmModuleReset(hNand->RmDevHandle, NvRmModuleID_Nand); + SetTimingRegVal(hNand, NV_FALSE); + // Restore the NAND lock cfg that was stored during previous Suspend, + // as locks should have got released due to reset operation. + NandRestoreLocks(hNand); + } + else if (e == NvError_NandReadEccFailed) + { + p->NumberOfPagesCompleted = + ((p->NumberOfPagesCompleted / hNand->MaxNumOfPagesPerDMARequest) * + hNand->MaxNumOfPagesPerDMARequest) + EccErrorPageOffset; + } + if (hNand->IsCommandQueueOperation) + { + if (e == NvError_NandCommandQueueError) + p->NumberOfPagesCompleted = hNand->NumOfPagesTransferred; + hNand->IsCommandQueueOperation = NV_FALSE; + } + hNand->OperationStatus = e; + return e; +} + +static NvError NandCheckForEccError(NvDdkNandHandle hNand, NvU32* ErrorPage) +{ + NandParams *p = &hNand->Params; + NvU32 DecStatusReg; + NvU32 BufferStart; + NvU32 i; + NvU32 j; + NvBool IsDefaultData = NV_FALSE; + for (i = 0; i < hNand->EccErrorCount; i++) + { + IsDefaultData = NV_FALSE; + // Check Nand decode status register to check decode failures. + DecStatusReg = hNand->pEccErrorData[i]; + *ErrorPage = NV_DRF_VAL(NAND, DEC_STATUS, ERR_PAGE_NUMBER, DecStatusReg); + if (NV_DRF_VAL(NAND, DEC_STATUS, A_ECC_FAIL, DecStatusReg)) + { + // Don't raise Ecc error if all data is 0xFF. + if (p->pDataBuffer) + { + BufferStart = ((*ErrorPage) * hNand->DevInfo.PageSize); + for (j = 0; j < hNand->DevInfo.PageSize; j++) + { + if (hNand->DataBuffer.pVirtualBuffer[j + BufferStart] != 0xFF) + { + DumpRegData(hNand); + PRINT_ERROR(("\r\n Ecc.Err pgoffset: %d, status: 0x%x", *ErrorPage, DecStatusReg)); + return NvError_NandReadEccFailed; + } + } + // We reached here because Flash has default data i.e. 0xFF + IsDefaultData = NV_TRUE; + } + } + if (NV_DRF_VAL(NAND, DEC_STATUS, B_ECC_FAIL, DecStatusReg)) + { + if (p->pTagBuffer) + { + BufferStart = ((*ErrorPage) * hNand->DevInfo.TagSize); + for (j = 0; j < hNand->DevInfo.TagSize; j++) + { + if (hNand->TagBuffer.pVirtualBuffer[j + BufferStart] != 0xFF) + { + DumpRegData(hNand); + PRINT_ERROR(("\r\n Ecc.Err in Tag pgoffset: %d, status: 0x%x", *ErrorPage, DecStatusReg)); + return NvError_NandReadEccFailed; + } + } + // We reached here because Flash has default data i.e. 0xFF + IsDefaultData = NV_TRUE; + } + } + // If we have ECC error with no decode failure observed and also Flash + // contains Non-0xFF data means, the error threshold has reached. + if (!IsDefaultData) + return NvError_NandErrorThresholdReached; + } + return NvSuccess; +} + +static NvError NonCQWrite(NvDdkNandHandle hNand, NvU32 MaxPageNumberOffset, NvU32* pPageNumberOffset) +{ + NvU32 i = 0; + NvU32 j = 0; + NandParams *p = &hNand->Params; + NvError e = NvSuccess; + #if NAND_TIME_STAMP + NvU64 Time; + #endif + NvU32 NumberOfPages = 0; + NvU8 StartDeviceNumber = 0; + NvU8 DeviceNumber = 0; + NvU32 PageNumber = 0; + + for (i = 0; i < p->NumberOfPages; i += NumberOfPages) + { + NumberOfPages = 0; + StartDeviceNumber = p->DeviceNumber; + for (j = 0; j < hNand->NumberOfChipsToBeInterleaved; j++) + { + SkipUnusedDevices(hNand, p->pStartPageNumbers, + &(p->DeviceNumber), pPageNumberOffset); + + DeviceNumber = hNand->PhysicalDeviceNumber[p->DeviceNumber]; + if (i) + { + // Check status of previous operation here + e = GetOperationStatus(hNand, DeviceNumber); + if (e != NvError_Success) + return e; + } + + SetupRegisters(hNand, NandOperation_Write); + SetupInterrupt(hNand, NandOperation_Write); + if (((*pPageNumberOffset) < (MaxPageNumberOffset - 1)) && + hNand->IsCacheWriteSupproted) + Nand_REGW(hNand, CMD_REG2, NvOdmNandCommandList_Cache_Program_Start); + else + Nand_REGW(hNand, CMD_REG2, NvOdmNandCommandList_Page_Program_Start); + + PageNumber = p->pStartPageNumbers[p->DeviceNumber]; + #if NAND_DISPLAY_ALL + if (DebugPrintEnable) + { + PRINT_ALL(("\nWr DevNum = %d, PageNum = %d", + DeviceNumber, (PageNumber + (*pPageNumberOffset)))); + } + #endif + // Setup all registers required for main area read here. + SetupAddressAndDeviceReg(hNand, DeviceNumber, + (PageNumber + (*pPageNumberOffset))); + // Start Nand operation. + StartNandOperation(hNand); + + // Wait till command done. + e = WaitForCommandDone(hNand); + if (e != NvError_Success) + return e; + p->DeviceNumber++; + if (p->DeviceNumber >= NDFLASH_CS_MAX) + { + p->DeviceNumber = 0; + (*pPageNumberOffset)++; + } + NumberOfPages++; + p->NumberOfPagesCompleted++; + if ((i + NumberOfPages) == p->NumberOfPages) + break; + } + } + p->DeviceNumber = StartDeviceNumber; + for (j = 0; j < hNand->NumberOfChipsToBeInterleaved; j++) + { + SkipUnusedDevices(hNand, p->pStartPageNumbers, + &(p->DeviceNumber), NULL); + DeviceNumber = hNand->PhysicalDeviceNumber[p->DeviceNumber]; + // Check status of previous operation here + e = GetOperationStatus(hNand, DeviceNumber); + if (e != NvError_Success) + return NvError_NandProgramFailed; + p->DeviceNumber++; + if (p->DeviceNumber == hNand->NumberOfChipsToBeInterleaved) + { + p->DeviceNumber = 0; + } + } + (*pPageNumberOffset)++; + return e; +} + +static NvError CommandQueueWrite(NvDdkNandHandle hNand, NvU32 MaxPageNumberOffset, NvU32* pPageNumberOffset) +{ + NandParams *p = &hNand->Params; + NvError e = NvSuccess; + #if NAND_TIME_STAMP + NvU64 Time; + #endif + NvU8 DeviceNumber = 0; + NvU32 PageNumber = 0; + + SkipUnusedDevices(hNand, p->pStartPageNumbers, + &(p->DeviceNumber), pPageNumberOffset); + + DeviceNumber = hNand->PhysicalDeviceNumber[p->DeviceNumber]; + SetupRegisters(hNand, NandOperation_Write); + SetupInterrupt(hNand, NandOperation_Write); + if (((*pPageNumberOffset) < (MaxPageNumberOffset - 1)) && + hNand->IsCacheWriteSupproted) + Nand_REGW(hNand, CMD_REG2, NvOdmNandCommandList_Cache_Program_Start); + else + Nand_REGW(hNand, CMD_REG2, NvOdmNandCommandList_Page_Program_Start); + + PageNumber = p->pStartPageNumbers[p->DeviceNumber]; + #if NAND_DISPLAY_ALL + if (DebugPrintEnable) + { + PRINT_ALL(("\nWr DevNum = %d, PageNum = %d", + DeviceNumber, (PageNumber + (*pPageNumberOffset)))); + } + #endif + // Setup all registers required for main area read here. + SetupAddressAndDeviceReg(hNand, DeviceNumber, + (PageNumber + (*pPageNumberOffset))); + // Set Command queue buffer and start the data transfers + StartCqOperation(hNand); + + e = WaitForCqDone(hNand); + if (e != NvSuccess) + return e; + (*pPageNumberOffset) += + (p->NumberOfPages / hNand->NumberOfChipsToBeInterleaved); + p->DeviceNumber += (p->NumberOfPages % hNand->NumberOfChipsToBeInterleaved); + do + { + p->DeviceNumber++; + if (p->DeviceNumber >= NDFLASH_CS_MAX) + { + p->DeviceNumber = 0; + } + } + while(p->pStartPageNumbers[p->DeviceNumber] == 0xFFFFFFFF); + p->NumberOfPagesCompleted += p->NumberOfPages; + + return e; +} + +static NvError NandWrite(NvDdkNandHandle hNand) +{ + NvU32 NumOfPagesRemaining = 0; + NvU32 PageNumberOffset = 0; + NvError e = NvSuccess; + NvU32 i = 0; + NandParams *p = &hNand->Params; + NvU32 MaxPageNumberOffset = 0; + #if NAND_TIME_STAMP + NvU64 Time; + #endif + + NumOfPagesRemaining = p->NumberOfPages; + #if NAND_DISPLAY_ALL + if (DebugPrintEnable) + { + PRINT_ALL(("\nWr DevNum = %d, PageNum = %d, No. pages = %d", + p->DeviceNumber, p->pStartPageNumbers[p->DeviceNumber], + p->NumberOfPages)); + } + #endif + // Calculate number of CS interleaved in the current transaction + GetNumOfCsInterleaved(hNand, p->pStartPageNumbers); + + #if NAND_TIME_STAMP + Time = NvOsGetTimeUS(); + #endif + while (NumOfPagesRemaining) + { + // Calculate number of pages to be written in one DMA set up. + p->NumberOfPages = + (NumOfPagesRemaining > hNand->MaxNumOfPagesPerDMARequest) ? + hNand->MaxNumOfPagesPerDMARequest : NumOfPagesRemaining; + NumOfPagesRemaining -= p->NumberOfPages; + // Shift the data buffer pointer by p->NumberOfPages . + if ((p->pDataBuffer != NULL) && (p->pDataBuffer !=hNand->DataBuffer.pVirtualBuffer)) + { + NvOsMemcpy(hNand->DataBuffer.pVirtualBuffer, + p->pDataBuffer, + (hNand->DevInfo.PageSize) * (p->NumberOfPages)); + } + if (p->pTagBuffer) + { + NvOsMemcpy( hNand->TagBuffer.pVirtualBuffer, + p->pTagBuffer, + p->NumSpareAreaBytes ? p->NumSpareAreaBytes : + ((hNand->DevInfo.TagSize) * (p->NumberOfPages)) ); + } + #if IS_CQ_ENABLED + SetCommandQueueOperationState(hNand, NumOfPagesRemaining, p); + #else + hNand->IsCommandQueueOperation = NV_FALSE; + #endif + // Setup DMA upto maximum data size that can be transferrable. + SetupDMA(hNand); + MaxPageNumberOffset += (p->NumberOfPages / hNand->NumberOfChipsToBeInterleaved); + + if (hNand->IsCommandQueueOperation) + e = CommandQueueWrite(hNand, MaxPageNumberOffset, &PageNumberOffset); + else + e = NonCQWrite(hNand, MaxPageNumberOffset, &PageNumberOffset); + if (p->pDataBuffer) + { + // Shift the data buffer pointer by p->NumberOfPages . + p->pDataBuffer += (hNand->DevInfo.PageSize) * + (p->NumberOfPages); + } + if (p->pTagBuffer) + { + p->pTagBuffer += (hNand->DevInfo.TagSize) * + (p->NumberOfPages); + } + + // Wait till DMA done. This is only for non-command queue mode. + // For Command queue mode, this function just returns back. + NV_CHECK_ERROR_CLEANUP(WaitForDmaDone(hNand)); + } + #if NAND_TIME_STAMP + Time = NvOsGetTimeUS() - Time; + if (DebugPrintEnable) + { + PRINT_ALL(("\r\ntms Write time = %dus, pc = %d", Time, p->NumberOfPages)); + } + #endif +fail: + NAND_ASSERT(e); + if (e != NvSuccess) + { + for (i = 0;i < 8; i++) + { + if (p->pStartPageNumbers[i] != 0xFFFFFFFF) + NvOsDebugPrintf("\n Chip: %d, Page = %d\n", i, p->pStartPageNumbers[i]); + } + } + if (e == NvError_Timeout) + { + DumpRegData(hNand); + NvRmModuleReset(hNand->RmDevHandle, NvRmModuleID_Nand); + SetTimingRegVal(hNand, NV_FALSE); + // Restore the NAND lock cfg that was stored during previous Suspend, + // as locks should have got released due to reset operation. + NandRestoreLocks(hNand); + } + if (hNand->IsCommandQueueOperation) + { + if (e == NvError_NandCommandQueueError) + p->NumberOfPagesCompleted = hNand->NumOfPagesTransferred; + hNand->IsCommandQueueOperation = NV_FALSE; + } + hNand->OperationStatus = e; + return e; +} + +///////////////// TO SUPPORT ONFI NANDS /////////////////////// + +#define ONFI_INITIAL_PAGE_SIZE 2048 // FixMe: Does it need to be set to the Max Page size? +#define ONFI_SPEC2_INITIAL_TR_TIME 200 // 200 microseconds as per section 4.2.1 of ONFI spec2 +#define READ_ID_ADDR_FOR_ONFI_NAND 0x20 +#define ONFI_ID_SIZE_IN_BYTES 4 + +static NvError ReadONFIParamPage(NvDdkNandHandle hNand, NvU8 DeviceNumber, NvRmPhysAddr pDataBuffer) +{ + NvError e = NvSuccess; + NvU32 DmaMasterControl = 0; + SetupRegisters(hNand, NandOperation_ReadParamPage); + SetupInterrupt(hNand, NandOperation_Read); + + hNand->Params.ColumnNumber = 0; + SetupAddressAndDeviceReg(hNand, DeviceNumber, 0); + // Start Nand operation. + StartNandOperation(hNand); + NV_CHECK_ERROR_CLEANUP(WaitForCommandDone(hNand)); + + // Wait for initial tR time here as per ONFI spec. + NandWaitUS(ONFI_SPEC2_INITIAL_TR_TIME); + + //issue data cycles + SetupRegisters(hNand, NandOperation_DataCyclesAlone); + SetupAddressAndDeviceReg(hNand, DeviceNumber, 0); + Nand_REGW(hNand, DATA_BLOCK_PTR, (NvU32)pDataBuffer); + Nand_REGW(hNand, DMA_CFG_A, (ONFI_INITIAL_PAGE_SIZE - 1)); + Nand_REGW(hNand, CONFIG, 0x30000); + + // Set the DMA burst size to 8 words. + // Enable DMA performance. + // Enable DMA for main area. + // Finally, Enable the DMA + DmaMasterControl = NV_DRF_DEF(NAND, DMA_MST_CTRL, BURST_SIZE, BURST_8WORDS)| + NV_DRF_DEF(NAND, DMA_MST_CTRL, DMA_PERF_EN, ENABLE) | + NV_DRF_DEF(NAND, DMA_MST_CTRL, DMA_EN_A, DEFAULT_MASK) | + NV_DRF_NUM(NAND, DMA_MST_CTRL, IS_DMA_DONE, 1) | + NV_DRF_NUM(NAND, DMA_MST_CTRL, IE_DMA_DONE, 1) | + NV_DRF_DEF(NAND, DMA_MST_CTRL, DMA_GO, ENABLE); + + Nand_REGW(hNand, DMA_MST_CTRL, DmaMasterControl); + + // Start Nand operation. + StartNandOperation(hNand); + NV_CHECK_ERROR_CLEANUP(WaitForCommandDone(hNand)); + NV_CHECK_ERROR_CLEANUP(WaitForDmaDone(hNand)); +fail: + return e; +} + +static NvError InitONFINands(NvDdkNandHandle hNand, const NvU8 DeviceNumber) +{ + NvU8 ReadID[ONFI_ID_SIZE_IN_BYTES] ; + NvError e = NvSuccess; + SdramBufferParams BufParams; + NvU32 CompareResult = 0; + NvU8 OnfiSignature[ONFI_ID_SIZE_IN_BYTES] = {0x4F, 0x4E, 0x46, 0x49}; // ASCII values of O, N, F, I + + BufParams.BufferSize = ONFI_INITIAL_PAGE_SIZE; + NV_CHECK_ERROR_CLEANUP(MemAllocBuffer(hNand, &BufParams, NAND_BUFFER_ALIGNMENT)); + hNand->Params.WaitTimeoutInMilliSeconds = NAND_COMMAND_TIMEOUT_IN_MS; + ResetNandFlash(hNand, DeviceNumber); + // Check for the ONFI signature + NV_CHECK_ERROR_CLEANUP(NandReadID(hNand, DeviceNumber, (NvU32 *)ReadID, NV_TRUE)); + CompareResult = NandUtilMemcmp(ReadID, OnfiSignature, ONFI_ID_SIZE_IN_BYTES); + if ((DeviceNumber == 0) && CompareResult) + hNand->IsONFINandOnCs0 = NV_FALSE; + // Read Params Page + NV_CHECK_ERROR_CLEANUP(ReadONFIParamPage(hNand, DeviceNumber, BufParams.PhysBuffer)); + CompareResult = NandUtilMemcmp(BufParams.pVirtualBuffer, OnfiSignature, ONFI_ID_SIZE_IN_BYTES); + if ((DeviceNumber == 0) && CompareResult) + hNand->IsONFINandOnCs0 = NV_FALSE; +fail: + DestroyMemHandle(&BufParams); + return e; +} + +///////////////// TO SUPPORT ONFI NANDS /////////////////////// + +static NvError NandReadID( + NvDdkNandHandle hNand, + NvU8 DeviceNumber, + NvU32* ReadID, + NvBool IsOnfiNand) +{ + NvError Error = NvSuccess; + + SetupRegisters(hNand, NandOperation_ReadId); + + if (IsOnfiNand) + hNand->Params.ColumnNumber = READ_ID_ADDR_FOR_ONFI_NAND; + else + hNand->Params.ColumnNumber = 0; + SetupAddressAndDeviceReg(hNand, DeviceNumber, 0); + CleanInterruptRegisters(hNand); + // Start Nand operation. + StartNandOperation(hNand); + Error = NandWaitCommandDone(hNand); + *ReadID = Nand_REGR(hNand, RESP); + return Error; +} + +static void NandWaitUS(NvU32 usec) +{ + NvU64 t0; + NvU64 t1; + + t0 = NvOsGetTimeUS(); + t1 = t0; + // Use the difference for the comparison to be wraparound safe + while (DIFF(t1, t0) < usec) + { + t1 = NvOsGetTimeUS(); + } +} + +#if NAND_DDK_ENABLE_DMA_POLLING_MODE +static NvError NandWaitDmaDone(NvDdkNandHandle hNand) +{ + NvU32 DmaMasterControl; + NvU32 DmaGo; + NvU32 StatusReg; + NvU32 IsIdle; + NvU32 IsrReg; + NvU32 IsDmaDone; + NvU32 TimeOutCounter = 10000000; + // Wait for DMA done with timeout check. + while (TimeOutCounter) + { + // Check whether the TX is completed. + DmaMasterControl = Nand_REGR(hNand, DMA_MST_CTRL); + DmaGo = NV_DRF_VAL(NAND, DMA_MST_CTRL, DMA_GO, DmaMasterControl); + // Check the status register. + StatusReg = Nand_REGR(hNand, STATUS); + IsIdle = NV_DRF_VAL(NAND, STATUS, ISEMPTY, StatusReg); + IsDmaDone = NV_DRF_VAL(NAND, DMA_MST_CTRL, IS_DMA_DONE, DmaMasterControl); + if ((DmaGo == 0) && IsIdle && IsDmaDone) + { + IsrReg = Nand_REGR(hNand, ISR); + // Clear the status. + Nand_REGW(hNand, ISR, IsrReg); + Nand_REGW(hNand, DMA_MST_CTRL, DmaMasterControl); + break; + } + NvOsWaitUS(1); + TimeOutCounter--; + } + if (!TimeOutCounter) + { + DmaGo = NV_DRF_VAL(NAND, DMA_MST_CTRL, DMA_GO, DmaMasterControl); + if (DmaGo != 0) + { + NAND_ASSERT(NvError_Timeout); + return NvError_Timeout; + } + } + return NvSuccess; +} + +static NvError NandWaitCqDone(NvDdkNandHandle hNand) +{ + NvU32 CommandReg; + NvU32 CommandGo; + NvU32 TimeOutCounter = 1000 * NAND_COMMAND_TIMEOUT_IN_MS; + NvU32 IsrReg; + NvU32 IsCommandDone; + // Wait for Command to be sent out with time out. + while (TimeOutCounter) + { + CommandReg = Nand_REGR(hNand, COMMAND); + CommandGo = NV_DRF_VAL(NAND, LL_CONFIG, LL_START, CommandReg); + // CommandGo = 1 indicates that command send cycle is not yet complete. + // CommandGo = 0 indicates that command is sent. + IsrReg = Nand_REGR(hNand, ISR); + IsCommandDone = NV_DRF_VAL(NAND, ISR, IS_LL_DONE, IsrReg); + if ((CommandGo == 0) && IsCommandDone) + { + IsCommandDone = NV_DRF_NUM(NAND, ISR, IS_LL_DONE, 1); + Nand_REGW(hNand, ISR, IsCommandDone); + break; + } + NvOsWaitUS(1); + TimeOutCounter--; + } + if (!TimeOutCounter) + { + NAND_ASSERT(NvError_Timeout); + return NvError_Timeout; + } + return NvSuccess; +} + +#endif + +static NvError NandWaitCommandDone(NvDdkNandHandle hNand) +{ + NvU32 CommandReg; + NvU32 CommandGo; + NvU32 TimeOutCounter = 1000 * NAND_COMMAND_TIMEOUT_IN_MS; + NvU32 IsrReg; + NvU32 IsCommandDone; + // Wait for Command to be sent out with time out. + while (TimeOutCounter) + { + CommandReg = Nand_REGR(hNand, COMMAND); + CommandGo = NV_DRF_VAL(NAND, COMMAND, GO, CommandReg); + // CommandGo = 1 indicates that command send cycle is not yet complete. + // CommandGo = 0 indicates that command is sent. + IsrReg = Nand_REGR(hNand, ISR); + IsCommandDone = NV_DRF_VAL(NAND, ISR, IS_CMD_DONE, IsrReg); + if ((CommandGo == 0) && IsCommandDone) + { + IsCommandDone = NV_DRF_NUM(NAND, ISR, IS_CMD_DONE, 1); + Nand_REGW(hNand, ISR, IsCommandDone); + break; + } + NvOsWaitUS(1); + TimeOutCounter--; + } + if (!TimeOutCounter) + { + CommandGo = NV_DRF_VAL(NAND, COMMAND, GO, CommandReg); + if (CommandGo != 0) + { + NAND_ASSERT(NvError_Timeout); + return NvError_Timeout; + } + } + return NvSuccess; +} + +static NvError +RegisterNandInterrupt( + NvRmDeviceHandle hDevice, + NvDdkNandHandle hNand) +{ + NvU32 IrqList; + NvOsInterruptHandler IntHandlers; + if (hNand->InterruptHandle) + { + return NvSuccess; + } + IrqList = NvRmGetIrqForLogicalInterrupt(hDevice, NvRmModuleID_Nand, 0); + IntHandlers = NandIsr; + return NvRmInterruptRegister(hDevice, 1, &IrqList, &IntHandlers, + hNand, &hNand->InterruptHandle, NV_TRUE); +} + +static void ClearNandFifos(NvDdkNandHandle hNand) +{ + NvU32 FifoControlRegister = 0; + FifoControlRegister = NV_DRF_NUM(NAND, FIFO_CTRL, LL_BUF_CLR, 1)| + NV_DRF_NUM(NAND, FIFO_CTRL, FIFO_A_CLR, 1)| + NV_DRF_NUM(NAND, FIFO_CTRL, FIFO_B_CLR, 1)| + NV_DRF_NUM(NAND, FIFO_CTRL, FIFO_C_CLR, 1); + Nand_REGW(hNand, FIFO_CTRL, FifoControlRegister); +} + +static void NandIsr(void* args) +{ + NvU32 InterruptStatusReg = 0; + NvU32 InterruptEnableReg = 0; + NvU32 Interrupts2Clear = 0; + NvU32 EccErr2Clear = 0; + NvU32 DmaStatusReg = 0; + NvU32 DecodeStatusReg = 0; + NvU32 SignalCommandDoneSema = 0; + NvU32 SignalDmaDoneSema = 0; + NvDdkNandHandle hNand = args; + + InterruptStatusReg = Nand_REGR(hNand, ISR); + InterruptEnableReg = Nand_REGR(hNand, IER); + DmaStatusReg = Nand_REGR(hNand, DMA_MST_CTRL); + + // If the interrupt is enabled, then only clear that particular interrupt. + if (NV_DRF_VAL(NAND, ISR, IS_LL_ERR, InterruptStatusReg) && + NV_DRF_VAL(NAND, IER, IE_LL_ERR, InterruptEnableReg)) + { + // Clear LL_ERR field of ISR. + Interrupts2Clear |= NV_DRF_NUM(NAND, ISR, IS_LL_ERR, 1); + ClearNandFifos(hNand); + DecodeStatusReg = Nand_REGR(hNand, DEC_STATUS); + hNand->NumOfPagesTransferred = NV_DRF_VAL(NAND, DEC_STATUS, + ERR_PAGE_NUMBER, DecodeStatusReg); + hNand->IsCqError = NV_TRUE; + PRINT_INTS(("\r\n NINT- IS_LL_ERR")); + SignalCommandDoneSema++; + } + if (NV_DRF_VAL(NAND, ISR, IS_LL_DONE, InterruptStatusReg) && + NV_DRF_VAL(NAND, IER, IE_LL_DONE, InterruptEnableReg)) + { + // Clear LL_DONE field of ISR. + Interrupts2Clear |= NV_DRF_NUM(NAND, ISR, IS_LL_DONE, 1); + // Signal the Command done sema. + PRINT_INTS(("\r\n NINT- IS_LL_DONE")); + if (!hNand->IsCqError) + SignalCommandDoneSema++; + } + if (NV_DRF_VAL(NAND, ISR, IS_UND, InterruptStatusReg) && + NV_DRF_VAL(NAND, IER, IE_UND, InterruptEnableReg)) + { + NV_ASSERT(NV_FALSE); + // Clear UND field of ISR. + Interrupts2Clear |= NV_DRF_NUM(NAND, ISR, IS_UND, 1); + PRINT_INTS(("\r\n NINT- IS_UND")); + } + if (NV_DRF_VAL(NAND, ISR, IS_OVR, InterruptStatusReg) && + NV_DRF_VAL(NAND, IER, IE_OVR, InterruptEnableReg)) + { + NV_ASSERT(NV_FALSE); + // Clear OVR field of ISR. + Interrupts2Clear |= NV_DRF_NUM(NAND, ISR, IS_OVR, 1); + PRINT_INTS(("\r\n NINT- IS_OVR")); + } + if (NV_DRF_VAL(NAND, ISR, IS_ECC_ERR, InterruptStatusReg) && + NV_DRF_VAL(NAND, IER, IE_ECC_ERR, InterruptEnableReg)) + { + // Clear ECC_ERR field of ISR. + hNand->pEccErrorData[hNand->EccErrorCount] = Nand_REGR(hNand, DEC_STATUS); + hNand->EccErrorCount++; + NV_ASSERT(hNand->EccErrorCount <= hNand->MaxNumOfPagesPerDMARequest); + NV_ASSERT(hNand->Params.OperationName == NandOperation_Read); + EccErr2Clear |= NV_DRF_NUM(NAND, ISR, IS_ECC_ERR, 1); + Nand_REGW(hNand, ISR, EccErr2Clear); + PRINT_INTS(("\r\n NINT- IS_ECC_ERR")); + } + if (NV_DRF_VAL(NAND, ISR, IS_CMD_DONE, InterruptStatusReg) && + NV_DRF_VAL(NAND, IER, IE_CMD_DONE, InterruptEnableReg)) + { + // Clear CMD_DONE field of ISR. + Interrupts2Clear |= NV_DRF_NUM(NAND, ISR, IS_CMD_DONE, 1); + // Signal the Command done sema. + PRINT_INTS(("\r\n NINT- IS_CMD_DONE")); + SignalCommandDoneSema++; + } + if (NV_DRF_VAL(NAND, DMA_MST_CTRL, IS_DMA_DONE, DmaStatusReg) && + NV_DRF_VAL(NAND, DMA_MST_CTRL, IE_DMA_DONE, DmaStatusReg)) + { + // Clear DMA_DONE field of DMA_MST_CNTL reg. + Nand_REGW(hNand, DMA_MST_CTRL, DmaStatusReg); + // Signal the Dma done sema. + PRINT_INTS(("\r\n NINT- IS_DMA_DONE")); + SignalDmaDoneSema++; + } + // Write registers at the end. + if (Interrupts2Clear & InterruptStatusReg) + { + Nand_REGW(hNand, ISR, Interrupts2Clear); + InterruptStatusReg = Nand_REGR(hNand, ISR); + PRINT_INTS(("\r\n NINT- Isr 0x%x 0x%x ", Interrupts2Clear, + InterruptStatusReg)); + } + + InterruptStatusReg = Nand_REGR(hNand, LOCK_STATUS); + if (NV_DRF_VAL(NAND, LOCK_STATUS, IS_LOCK_ERR, InterruptStatusReg)) + { + PRINT_INTS(("\r\n NINT- IS_LOCK_ERR")); + NandPrivLockInterruptService(hNand, InterruptStatusReg); + } + + NV_ASSERT(SignalCommandDoneSema <= 1); + NV_ASSERT(SignalDmaDoneSema <= 1); + while (SignalCommandDoneSema--) + NvOsSemaphoreSignal(hNand->CommandDoneSema); + while (SignalDmaDoneSema--) + NvOsSemaphoreSignal(hNand->DmaDoneSema); + NvRmInterruptDone(hNand->InterruptHandle); +} + +static NvError NandDisableWriteProtect(NvDdkNandHandle hNand) +{ + NvError ErrStatus = NvError_Success; + NvRmGpioPinState PinState; + const NvOdmGpioPinInfo *pPinInfoTable = NULL; + NvU32 PinCount = 1; + + ErrStatus = NvRmGpioOpen(hNand->RmDevHandle, &hNand->hGpio); + if (ErrStatus != NvSuccess) + return ErrStatus; + + pPinInfoTable = NvOdmQueryGpioPinMap(NvOdmGpioPinGroup_NandFlash, 0, &PinCount); + if (!pPinInfoTable) // write protect gpio is optional. + return NvSuccess; + + ErrStatus = NvRmGpioAcquirePinHandle(hNand->hGpio, pPinInfoTable->Port, + pPinInfoTable->Pin, &hNand->hWriteProtectPin); + if (ErrStatus != NvSuccess) + return ErrStatus; + + NvRmGpioConfigPins(hNand->hGpio, &hNand->hWriteProtectPin, 1, NvRmGpioPinMode_Output); + PinState = NvRmGpioPinState_High; + NvRmGpioWritePins(hNand->hGpio, &hNand->hWriteProtectPin, &PinState, 1); + + return ErrStatus; +} + +static void NandLoadLockCfg(NvDdkNandHandle hNand) +{ + NvU32 i; + NvU32 LockApertureMask; + NvU32 LockCtrlReg; + NvU32 LockRegOffset; + + LockCtrlReg = Nand_REGR(hNand, LOCK_CONTROL); + LockApertureMask = 1; + hNand->NumberOfAperturesUsed = 0; + for (i = 0; i < NDFLASH_CS_MAX; i++) + { + if(LockCtrlReg & LockApertureMask) + { + // Lock aperture enabled...read the aperture cfg + LockRegOffset = (NAND_LOCK_APER_CHIPID1_0 - NAND_LOCK_APER_CHIPID0_0) * i; + hNand->LockAperStart[i] = Nand_REGR_OFFSET(hNand, LOCK_APER_START0, LockRegOffset); + hNand->LockAperEnd[i] = Nand_REGR_OFFSET(hNand, LOCK_APER_END0, LockRegOffset); + hNand->LockAperChipId[i] = Nand_REGR_OFFSET(hNand, LOCK_APER_CHIPID0, LockRegOffset); + hNand->NumberOfAperturesUsed++; + } + LockApertureMask <<= 1; + } + + return; +} + +static void NandRestoreLocks(NvDdkNandHandle hNand) +{ + NvU32 i; + NvU32 LockCtrlReg; + NvU32 LockRegOffset; + LockCtrlReg = 0; + + // Restore the lock aperture definitions + if(hNand->NumberOfAperturesUsed) + { + for (i = 0; i < hNand->NumberOfAperturesUsed; i++) + { + LockRegOffset = (NAND_LOCK_APER_CHIPID1_0 - NAND_LOCK_APER_CHIPID0_0) * i; + Nand_REGW_OFFSET(hNand, LOCK_APER_START0, LockRegOffset, hNand->LockAperStart[i]); + Nand_REGW_OFFSET(hNand, LOCK_APER_END0, LockRegOffset, hNand->LockAperEnd[i]); + Nand_REGW_OFFSET(hNand, LOCK_APER_CHIPID0, LockRegOffset, hNand->LockAperChipId[i]); + LockCtrlReg |= (1 << i); + } + // re-enable the apertures + Nand_REGW(hNand, LOCK_CONTROL, LockCtrlReg); + } + return; +} + +static void +NandPrivLockInterruptService( + NvDdkNandHandle hNand, + NvU32 InterruptStatusRegister) +{ + NvU32 LockStatusRegister = 0; + + InterruptStatusRegister |= NV_DRF_NUM(NAND, LOCK_STATUS, IS_LOCK_ERR, 1); + Nand_REGW(hNand, LOCK_STATUS, InterruptStatusRegister); + LockStatusRegister = Nand_REGR(hNand, LOCK_STATUS); + Nand_REGW(hNand, LOCK_STATUS, LockStatusRegister); + ClearNandFifos(hNand); +} + +static void SetupCqPkt(NvDdkNandHandle hNand) +{ + NandParams* p = &hNand->Params; + NvU32 RegVal; + NvU32 Offset = 0; + NvU32 PageNumber = 0; + NvU32 NumOfPages = p->NumberOfPages; + NvU32 CqLength = 0; + NandCqPacket1 *pCqPkt1; + NandCqPacket2 *pCqPkt2; + NandCqPacket3 *pCqPkt3; + NvU32 Command2 = 0; + NvU32 PageNumberOffset = p->NumberOfPagesCompleted / hNand->NumberOfChipsToBeInterleaved; + NvU8 DeviceNumber = 0; + NvU32 MaxPageNumberOffset = 0; + NvU8 i = 0; + + while (NumOfPages) + { + MaxPageNumberOffset = p->NumberOfPages / hNand->NumberOfChipsToBeInterleaved; + if (p->OperationName == NandOperation_Write) + { + if ((PageNumberOffset < (MaxPageNumberOffset - 1)) && + hNand->IsCacheWriteSupproted) + Command2 = NvOdmNandCommandList_Cache_Program_Start; + else + Command2 = NvOdmNandCommandList_Page_Program_Start; + } + else + { + Command2 = Nand_REGR(hNand, CMD_REG2); + } + + // Fill dma control reg + address reg's + command reg's. + if (Offset == 0) + { + pCqPkt1 = (NandCqPacket1*)(hNand->CqBuffer.pVirtualBuffer); + // DMA Master Control register. + RegVal = Nand_REGR(hNand, DMA_MST_CTRL); + if (p->OperationName != NandOperation_Erase) + RegVal |= NV_DRF_NUM(NAND, DMA_MST_CTRL, DMA_GO, 1); + pCqPkt1->NandDmaMstCtrl = RegVal; + pCqPkt1->CqCommand = (1 << CqCommand_NandDmaMstCtrl); + // Command value register2. + pCqPkt1->NandCmdReg2 = Command2; + pCqPkt1->CqCommand |= (1 << CqCommand_NandCmdReg2); + // Command register. + RegVal = Nand_REGR(hNand, COMMAND); + DeviceNumber = hNand->PhysicalDeviceNumber[p->DeviceNumber]; + ChipSelectEnable(DeviceNumber, &RegVal); + RegVal |= NV_DRF_DEF(NAND, COMMAND, GO, ENABLE); + pCqPkt1->NandCmd = RegVal; + pCqPkt1->CqCommand |= (1 << CqCommand_NandCmd); + // Packet Id + pCqPkt1->CqCommand |= (Offset << CqCommand_PacketId); + CqLength += sizeof(NandCqPacket1); + } + // Fill address reg's + command reg's. + else + { + do + { + if (p->DeviceNumber < (NDFLASH_CS_MAX - 1)) + { + p->DeviceNumber++; + } + else + { + p->DeviceNumber = 0; + PageNumberOffset++; + } + } + while(p->pStartPageNumbers[p->DeviceNumber] == 0xFFFFFFFF); + DeviceNumber = hNand->PhysicalDeviceNumber[p->DeviceNumber]; + pCqPkt2 = (NandCqPacket2*)(hNand->CqBuffer.pVirtualBuffer + + CqLength); + // Address register1. + PageNumber = p->pStartPageNumbers[p->DeviceNumber]; + RegVal = p->ColumnNumber | + ((PageNumber + PageNumberOffset) << NAND_ADDR_REG1_0_ADDR_BYTE2_SHIFT); + pCqPkt2->NandAddrReg1 = RegVal; + pCqPkt2->CqCommand = (1 << CqCommand_NandAddrReg1); + // Address register2. + RegVal = ((PageNumber + PageNumberOffset) >> NAND_ADDR_REG1_0_ADDR_BYTE2_SHIFT); + pCqPkt2->NandAddrReg2 = RegVal; + pCqPkt2->CqCommand |= (1 << CqCommand_NandAddrReg2); + // Command value register2. + pCqPkt2->NandCmdReg2 = Command2; + pCqPkt2->CqCommand |= (1 << CqCommand_NandCmdReg2); + // Command register. + RegVal = Nand_REGR(hNand, COMMAND); + ChipSelectEnable(DeviceNumber, &RegVal); + RegVal |= NV_DRF_DEF(NAND, COMMAND, GO, ENABLE); + if (p->OperationName != NandOperation_Read) + RegVal |= NV_DRF_NUM(NAND, COMMAND, RD_STATUS_CHK, 1); + pCqPkt2->NandCmd = RegVal; + pCqPkt2->CqCommand |= (1 << CqCommand_NandCmd); + // Packet Id + pCqPkt2->CqCommand |= (Offset << CqCommand_PacketId); + CqLength += sizeof(NandCqPacket2); + } + Offset++; + NumOfPages--; + } + // Fill commad reg for issuing status read for last write page operation. + if (p->OperationName != NandOperation_Read) + { + for (i = 0; i < hNand->NumberOfChipsToBeInterleaved; i++) + { + pCqPkt3 = (NandCqPacket3*)(hNand->CqBuffer.pVirtualBuffer + CqLength); + // Command register. + RegVal = NV_DRF_DEF(NAND, COMMAND, GO, ENABLE) | + NV_DRF_NUM(NAND, COMMAND, RD_STATUS_CHK, 1) | + NV_DRF_NUM(NAND, COMMAND, RBSY_CHK, 1); + do + { + p->DeviceNumber++; + if (p->DeviceNumber >= NDFLASH_CS_MAX) + { + p->DeviceNumber = 0; + } + } + while(p->pStartPageNumbers[p->DeviceNumber] == 0xFFFFFFFF); + DeviceNumber = hNand->PhysicalDeviceNumber[p->DeviceNumber]; + ChipSelectEnable(DeviceNumber, &RegVal); + pCqPkt3->NandCmd = RegVal; + pCqPkt3->CqCommand = (1 << CqCommand_NandCmd); + // Packed Id + pCqPkt3->CqCommand |= (Offset << CqCommand_PacketId); + CqLength += sizeof(NandCqPacket3); + Offset++; + } + } + CqLength = (CqLength / sizeof(NvU32)); + RegVal = NV_DRF_NUM(NAND, LL_CONFIG, LL_LENGTH, CqLength) | + NV_DRF_DEF(NAND, LL_CONFIG, BURST_SIZE, BURST_8WORDS) | + NV_DRF_NUM(NAND, LL_CONFIG, WORD_CNT_STATUS_EN, 1); + Nand_REGW(hNand, LL_CONFIG, RegVal); + // Set LL_pointer register + Nand_REGW(hNand, LL_PTR, hNand->CqBuffer.PhysBuffer); +} + +static NvError GetOperationStatus(NvDdkNandHandle hNand, NvU8 DeviceNumber) +{ + NvError e = NvSuccess; + NvU32 Response = 0; + + SetCommandQueueOperationState(hNand, 0, NULL); + SetupRegisters(hNand, NandOperation_GetStatus); + SetupAddressAndDeviceReg(hNand, DeviceNumber, 0); + CleanInterruptRegisters(hNand); + + // Start Nand operation. + StartNandOperation(hNand); + NV_CHECK_ERROR_CLEANUP(NandWaitCommandDone(hNand)); + Response = Nand_REGR(hNand, RESP); + + if (((Response & hNand->FlashParams.OperationSuccessStatus) != + hNand->FlashParams.OperationSuccessStatus) || + (Response & 1)) + { + // Either chip is not ready or operation failed. + PRINT_ALL(("\r\n Status failed, Response = %x", Response)); + NV_CHECK_ERROR_CLEANUP(NvError_NandOperationFailed); + } +fail: + return e; +} + +static void NandPowerRailEnable(NvDdkNandHandle hNand, NvBool IsEnable) +{ + NvU32 i; + NvRmPmuVddRailCapabilities RailCaps; + NvU32 SettlingTime; + + // As per Bug 525355 + if (hNand->pConnectivity == NULL) + return; + for (i = 0; i < (hNand->pConnectivity->NumAddress); i++) + { + // Search for the vdd rail entry + if (hNand->pConnectivity->AddressList[i].Interface == NvOdmIoModule_Vdd) + { + NvRmPmuGetCapabilities(hNand->RmDevHandle, + hNand->pConnectivity->AddressList[i].Address, &RailCaps); + if (IsEnable) + { + NvRmPmuSetVoltage(hNand->RmDevHandle, + hNand->pConnectivity->AddressList[i].Address, + RailCaps.requestMilliVolts, &SettlingTime); + } + else + { + NvRmPmuSetVoltage(hNand->RmDevHandle, + hNand->pConnectivity->AddressList[i].Address, + ODM_VOLTAGE_OFF, &SettlingTime); + } + if (SettlingTime) + NvOsWaitUS(SettlingTime); + } + } +} + +// Following function includes all register operations required for resetting a Nand +// flash referred by Device number. +static NvError ResetNandFlash(NvDdkNandHandle hNand, const NvU8 DeviceNumber) +{ + NvError Error = NvSuccess; + NvU32 RegVal = 0; + + SetupRegisters(hNand, NandOperation_Reset); + hNand->Params.ColumnNumber = 0; + SetupAddressAndDeviceReg(hNand, DeviceNumber, 0); + CleanInterruptRegisters(hNand); + + // Start Nand operation. + StartNandOperation(hNand); + Error = WaitForCommandDone(hNand); + if (Error != NvSuccess) + { + return Error; + } + // Check if GO did not become '0' yet. if so, send error. + RegVal = Nand_REGR(hNand, COMMAND); + RegVal = NV_DRF_VAL(NAND, COMMAND, GO, RegVal); + if (RegVal) + { + return NvError_NandOperationFailed; + } + Error = GetOperationStatus(hNand, DeviceNumber); + return Error; +} + +// Nand DDK APIs. +NvError NvDdkNandOpen(NvRmDeviceHandle hRmDevice, NvDdkNandHandle *phNand) +{ + NvU32 DeviceNumber = 0; + NvError e = NvError_Success; + NvU32 Count = 0; + NvDdkNandDeviceInfo DevInfo; + NvU32 BchConfigReg = 0; + // code for using NvOdmPeripheralEnumerate + const NvOdmPeripheralConnectivity *pConnectivity = NULL; + NvU64 NandGuid = 0; + NvU32 NumGuid = 0; + NvOsMutexHandle hMutex; + NvOdmPeripheralSearch SearchAttrs[] = + { + NvOdmPeripheralSearch_IoModule, + }; + NvU32 SearchVals[] = + { + NvOdmIoModule_Nand, + }; + + NV_ASSERT(phNand); + NV_ASSERT(hRmDevice); + + if (s_pNandRec) + { + NvOsMutexLock(s_pNandRec->hMutex); + *phNand = s_pNandRec; + s_pNandRec->RefCount++; + NvOsMutexUnlock(s_pNandRec->hMutex); + return NvSuccess; + } + e = NvOsMutexCreate(&hMutex); + if (e) + { + return e; + } + NvOsMutexLock(hMutex); + + NumGuid = NvOdmPeripheralEnumerate(SearchAttrs, SearchVals, + NV_ARRAY_SIZE(SearchAttrs), &NandGuid, 1); + if (NumGuid) + { + pConnectivity = NvOdmPeripheralGetGuid(NandGuid); + if (!pConnectivity) + { + e = NvError_ModuleNotPresent; + goto fail; + } + } + + // Allocate memory for handle. + s_pNandRec = NvOsAlloc(sizeof(NvDdkNand)); + if (s_pNandRec == NULL) + { + e = NvError_InsufficientMemory; + goto fail; + } + NvOsMemset(s_pNandRec, 0, sizeof(NvDdkNand)); + s_pNandRec->RmDevHandle = hRmDevice; + s_pNandRec->FlashParams.OperationSuccessStatus = SUCCESS_STATUS; + s_pNandRec->IsNandOpen = NV_TRUE; + s_pNandRec->pConnectivity = pConnectivity; + s_pNandRec->hMutex = hMutex; + // Get the base address of the Nand registers + NvRmModuleGetBaseAddress(hRmDevice, + NVRM_MODULE_ID(NvRmModuleID_Nand, 0), + &(s_pNandRec->pBaseAddress), &(s_pNandRec->BankSize)); + NV_CHECK_ERROR_CLEANUP(NvRmPhysicalMemMap(s_pNandRec->pBaseAddress, + s_pNandRec->BankSize, NVOS_MEM_READ_WRITE, NvOsMemAttribute_Uncached, + (void **)&(s_pNandRec->pVirtualAddress))); + NvDdkNandGetCapabilities(s_pNandRec, &(s_pNandRec->NandCapability)); + NV_CHECK_ERROR_CLEANUP(NvOsSemaphoreCreate(&s_pNandRec->DmaDoneSema, 0)); + NV_CHECK_ERROR_CLEANUP(NvOsSemaphoreCreate(&s_pNandRec->CommandDoneSema, 0)); + // Event semaphore to register with the rm_power module + NV_CHECK_ERROR_CLEANUP(NvOsSemaphoreCreate(&s_pNandRec->PowerMgmtSema, 0)); + // Register with the rm_power manager + s_pNandRec->RmPowerClientId = NVRM_POWER_CLIENT_TAG('N','A','N','D'); + NV_CHECK_ERROR_CLEANUP(NvRmPowerRegister(s_pNandRec->RmDevHandle, + s_pNandRec->PowerMgmtSema, &(s_pNandRec->RmPowerClientId))); + // Read the NAND lock cfg before resetting the NAND controller (NAND controller + // reset unlocks all flash). + s_pNandRec->IsLockStatusAvailable = NV_FALSE; + NvDdkNandResume(s_pNandRec); + s_pNandRec->IsLockStatusAvailable = NV_TRUE; + // As part of Suspend, Lock status is read from the controller. + NvDdkNandSuspend(s_pNandRec); + NvRmModuleReset(s_pNandRec->RmDevHandle, NvRmModuleID_Nand); + NV_CHECK_ERROR_CLEANUP(InitNandController(s_pNandRec)); + // Enable interrupt + NV_CHECK_ERROR_CLEANUP(RegisterNandInterrupt(hRmDevice, s_pNandRec)); + // Set Nand timing reg to a known Timing Value before identifying the flash. + s_pNandRec->OptimumTiming = TIMING_VALUE; + s_pNandRec->OptimumTiming2 = TIMING2_VALUE; + NvDdkNandResume(s_pNandRec); + // Disabling ONFI support by default, as it is increasing fastboot time. + // For enabling ONFI support "s_pNandRec->IsONFINandOnCs0" should be set to NV_TRUE + s_pNandRec->IsONFINandOnCs0 = NV_FALSE; + // To identify how many flashes are present on the board. + for (DeviceNumber = 0; DeviceNumber < + s_pNandRec->NandCapability.NumberOfDevicesSupported; DeviceNumber++) + { + s_pNandRec->PhysicalDeviceNumber[DeviceNumber] = 0xFF; + if (s_pNandRec->IsONFINandOnCs0) + { + e = InitONFINands(s_pNandRec, DeviceNumber); + if (e == NvSuccess) + { + PRINT_ALL(("\n\r ONFI Nand is connected to CS# %d", DeviceNumber)); + } + } + e = NvDdkNandGetDeviceInfo(s_pNandRec, DeviceNumber, &DevInfo); + if (e == NvError_Success) + { + // As Nand driver expects same flash part to be connected at + // all the chip selects, storing flash details in Nand handle once + if (!Count) + { + NvOsMemcpy(&(s_pNandRec->DevInfo), &DevInfo, + sizeof(NvDdkNandDeviceInfo)); + } + s_pNandRec->PhysicalDeviceNumber[Count] = DeviceNumber; + Count++; + } + } + // Return error either if the none of the flashes connected to the + // controller are identified or the flash is not supported. Add flash + // details to the ODM query table, if the flash used is not supported. + if (!Count) + NV_CHECK_ERROR_CLEANUP(NvError_NandFlashNotSupported); + s_pNandRec->NumOfActiveDevices = Count; + NvRmModuleReset(s_pNandRec->RmDevHandle, NvRmModuleID_Nand); + s_pNandRec->IsCacheWriteSupproted = s_pNandRec->FlashParams.IsCacheWriteSupported; + SetTimingRegVal(s_pNandRec, NV_TRUE); + // We must restore the lock state after resets + NandRestoreLocks(s_pNandRec); + s_pNandRec->MaxNumOfPagesPerDMARequest = + (s_pNandRec->NandCapability.MaxDataTransferSize) / + (s_pNandRec->DevInfo.PageSize); + s_pNandRec->pEccErrorData = NvOsAlloc(sizeof(NvU32) * + s_pNandRec->MaxNumOfPagesPerDMARequest); + if (s_pNandRec->pEccErrorData == NULL) + NV_CHECK_ERROR_CLEANUP(NvError_InsufficientMemory); + // Do Command queue related initialization. + if (s_pNandRec->NandCapability.IsCommandQueueModeSupported) + { + // As 4 bytes per each command queue word + s_pNandRec->CqBuffer.BufferSize = NDFLASH_CMDQ_MAX_PKT_LENGTH * 8 * + s_pNandRec->MaxNumOfPagesPerDMARequest; + // Need a 4-byte aligned memory buffer + NV_CHECK_ERROR_CLEANUP(MemAllocBuffer(s_pNandRec, &(s_pNandRec->CqBuffer), + NAND_BUFFER_ALIGNMENT)); + } + // Allocate memory required for storing error vectors. + if (s_pNandRec->NandCapability.IsEccSupported) + { + if (s_pNandRec->EccAlgorithm == ECCAlgorithm_BCH) + { + if (s_pNandRec->TValue == 0) + BchConfigReg |= NV_DRF_DEF(NAND, BCH_CONFIG, BCH_TVALUE, BCH_TVAL4); + else if (s_pNandRec->TValue == 1) + BchConfigReg |= NV_DRF_DEF(NAND, BCH_CONFIG, BCH_TVALUE, BCH_TVAL8); + else if (s_pNandRec->TValue == 2) + BchConfigReg |= NV_DRF_DEF(NAND, BCH_CONFIG, BCH_TVALUE, BCH_TVAL14); + else if (s_pNandRec->TValue == 3) + BchConfigReg |= NV_DRF_DEF(NAND, BCH_CONFIG, BCH_TVALUE, BCH_TVAL16); + else + NV_ASSERT(NV_FALSE); + // Enable BCH algorithm + BchConfigReg |= NV_DRF_DEF(NAND, BCH_CONFIG, BCH_ECC, ENABLE); + Nand_REGW(s_pNandRec, BCH_CONFIG, BchConfigReg); + } + else + { + s_pNandRec->EccBuffer.BufferSize = GetNumOfErrorVectorBytes(s_pNandRec); + // Need a 4-byte aligned memory buffer + NV_CHECK_ERROR_CLEANUP(MemAllocBuffer(s_pNandRec, &(s_pNandRec->EccBuffer), + NAND_BUFFER_ALIGNMENT)); + } + } + s_pNandRec->TValue = 0; + s_pNandRec->RmDevHandle = hRmDevice; + // Allocate physical buffer for Main data transfer + s_pNandRec->DataBuffer.BufferSize = + s_pNandRec->NandCapability.MaxDataTransferSize; + NV_CHECK_ERROR_CLEANUP(MemAllocBuffer(s_pNandRec, &(s_pNandRec->DataBuffer), + NAND_BUFFER_ALIGNMENT)); + // Allocate physical buffer for Tag data transfer + s_pNandRec->TagBuffer.BufferSize = s_pNandRec->DevInfo.NumSpareAreaBytes * + s_pNandRec->MaxNumOfPagesPerDMARequest; + NV_CHECK_ERROR_CLEANUP(MemAllocBuffer(s_pNandRec, &(s_pNandRec->TagBuffer), + NAND_BUFFER_ALIGNMENT)); + s_pNandRec->Params.WaitTimeoutInMilliSeconds = NAND_COMMAND_TIMEOUT_IN_MS; + s_pNandRec->RefCount++; + *phNand = s_pNandRec; + NvOsMutexUnlock(hMutex); + return NvSuccess; +fail: + // Disable interrupts. + PRINT_ALL(("\nNand ddk open err:0x%x\n", e)); + if (s_pNandRec) + { + NvRmInterruptUnregister(s_pNandRec->RmDevHandle, + s_pNandRec->InterruptHandle); + s_pNandRec->InterruptHandle = NULL; + NvOsSemaphoreDestroy(s_pNandRec->DmaDoneSema); + NvOsSemaphoreDestroy(s_pNandRec->CommandDoneSema); + DestroyMemHandle(&(s_pNandRec->EccBuffer)); + DestroyMemHandle(&(s_pNandRec->CqBuffer)); + DestroyMemHandle(&(s_pNandRec->DataBuffer)); + DestroyMemHandle(&(s_pNandRec->TagBuffer)); + NvRmPhysicalMemUnmap((void *)s_pNandRec->pVirtualAddress, + s_pNandRec->BankSize); + if (s_pNandRec->PowerMgmtSema) + { + NvRmPowerUnRegister(s_pNandRec->RmDevHandle, + s_pNandRec->RmPowerClientId); + NvOsSemaphoreDestroy(s_pNandRec->PowerMgmtSema); + } + NvOsFree((void*)s_pNandRec->pEccErrorData); + NvOsFree(s_pNandRec); + *phNand = NULL; + } + NvOsMutexUnlock(hMutex); + NvOsMutexDestroy(hMutex); + return e; +} + +void NvDdkNandClose(NvDdkNandHandle hNand) +{ + if ((hNand == NULL) || (!hNand->IsNandOpen)) + return; + + NvOsMutexLock(hNand->hMutex); + NV_ASSERT(hNand->RefCount); + hNand->RefCount--; + if (hNand->RefCount) + { + NvOsMutexUnlock(hNand->hMutex); + return; + } + + // Disable interrupts + NvRmInterruptUnregister(hNand->RmDevHandle, hNand->InterruptHandle); + hNand->InterruptHandle = NULL; + // Destroy all memory handles. + DestroyMemHandle(&(hNand->EccBuffer)); + DestroyMemHandle(&(hNand->CqBuffer)); + DestroyMemHandle(&(hNand->DataBuffer)); + DestroyMemHandle(&(hNand->TagBuffer)); + // Delete all semaphores. + NvOsSemaphoreDestroy(hNand->DmaDoneSema); + NvOsSemaphoreDestroy(hNand->CommandDoneSema); + if (hNand->RmPowerClientId) + { + // Unregister with RM Power + NvRmPowerUnRegister(hNand->RmDevHandle, hNand->RmPowerClientId); + } + NvOsSemaphoreDestroy(hNand->PowerMgmtSema); + // Call RM Unmap here + NvRmPhysicalMemUnmap((void *)(hNand->pVirtualAddress), hNand->BankSize); + NvOsMutexUnlock(hNand->hMutex); + NvOsMutexDestroy(hNand->hMutex); + if (hNand->hGpio) + { + if (hNand->hWriteProtectPin) + { + NvRmGpioReleasePinHandles(hNand->hGpio, + &hNand->hWriteProtectPin, 1); + } + NvRmGpioClose(hNand->hGpio); + } + NvOsFree(hNand); + s_pNandRec = NULL; +} + +NvError +NvDdkNandReadSpare( + NvDdkNandHandle hNand, + NvU8 StartDeviceNum, + NvU32* pPageNumbers, + NvU8* const pSpareBuffer, + NvU8 OffsetInSpareAreaInBytes, + NvU8 NumSpareAreaBytes) +{ + NvError e; + NV_ASSERT(hNand); + NV_ASSERT(pSpareBuffer != NULL); + + NvOsMutexLock(hNand->hMutex); + if (!hNand->IsNandOpen) + { + e = NvError_NandNotOpened; + goto fail; + } + hNand->Params.DeviceNumber = StartDeviceNum; + hNand->Params.pStartPageNumbers = pPageNumbers; + hNand->Params.pDstnPageNumbers = NULL; + hNand->Params.NumberOfPagesCompleted = 0; + hNand->Params.pDataBuffer = NULL; + hNand->Params.pTagBuffer = pSpareBuffer; + hNand->Params.NumberOfPages = 1; + hNand->Params.NumSpareAreaBytes = NumSpareAreaBytes; + + if (hNand->EccAlgorithm != NvOdmNandECCAlgorithm_BCH) + { + if (hNand->DevInfo.BusWidth == 16) + hNand->Params.ColumnNumber = + (hNand->DevInfo.PageSize + OffsetInSpareAreaInBytes) >> 1; + else + hNand->Params.ColumnNumber = + hNand->DevInfo.PageSize + OffsetInSpareAreaInBytes; + } + else + hNand->Params.ColumnNumber = 0; + + hNand->Params.OperationName = NandOperation_Read; + #if NAND_DISPLAY_ALL + if (DebugPrintEnable) + { + PRINT_ALL(("\nDDK_SpareRead:dev = %d, page_num = %d", + StartDeviceNum, pPageNumbers[StartDeviceNum])); + } + #endif + e = NandRead(hNand, NV_TRUE); +fail: + NvOsMutexUnlock(hNand->hMutex); + return e; + } + +NvError +NvDdkNandWriteSpare( + NvDdkNandHandle hNand, + NvU8 StartDeviceNum, + NvU32* pPageNumbers, + NvU8* const pSpareBuffer, + NvU8 OffsetInSpareAreaInBytes, + NvU8 NumSpareAreaBytes) +{ + NvError e; + NV_ASSERT(hNand); + NV_ASSERT(pSpareBuffer != NULL); + NvOsMutexLock(hNand->hMutex); + if (!hNand->IsNandOpen) + { + e = NvError_NandNotOpened; + goto fail; + } + + /* Don't allow writes to spare area containing factory bad block info */ + if (OffsetInSpareAreaInBytes == 0) + { + e = NvError_BadParameter; + goto fail; + } + + hNand->Params.DeviceNumber = StartDeviceNum; + hNand->Params.pStartPageNumbers = pPageNumbers; + hNand->Params.pDstnPageNumbers = NULL; + hNand->Params.NumberOfPagesCompleted = 0; + hNand->Params.pDataBuffer = NULL; + hNand->Params.pTagBuffer = pSpareBuffer; + hNand->Params.NumberOfPages = 1; + hNand->Params.NumSpareAreaBytes = NumSpareAreaBytes; + + if (hNand->EccAlgorithm != NvOdmNandECCAlgorithm_BCH) + { + if (hNand->DevInfo.BusWidth == 16) + hNand->Params.ColumnNumber = + (hNand->DevInfo.PageSize + OffsetInSpareAreaInBytes) >> 1; + else + hNand->Params.ColumnNumber = + hNand->DevInfo.PageSize + OffsetInSpareAreaInBytes; + } + else + hNand->Params.ColumnNumber = 0; + + hNand->Params.OperationName = NandOperation_Write; + #if NAND_DISPLAY_ALL + if (DebugPrintEnable) + { + PRINT_ALL(("\nDDK_SpareWrite:dev = %d, page_num = %d", + StartDeviceNum, pPageNumbers[StartDeviceNum])); + } + #endif + e = NandWrite(hNand); +fail: + NvOsMutexUnlock(hNand->hMutex); + return e; +} + +NvError +NvDdkNandGetBlockInfo( + NvDdkNandHandle hNand, + NvU32 DeviceNumber, + NvU32 BlockNumber, + NandBlockInfo* pBlockInfo, + NvBool SkippedBytesReadEnable) +{ + NvU32 PageNumbers[NDFLASH_CS_MAX]; + NvU32 Numpages = 1; + NvU32 devCount; + NvU32 i = 0; + NvError Status; + NV_ASSERT(pBlockInfo->pTagBuffer != NULL); + + NvOsMutexLock(hNand->hMutex); + + NV_ASSERT(pBlockInfo->pTagBuffer != NULL); + for(devCount = 0;devCount < NDFLASH_CS_MAX;devCount++) + PageNumbers[devCount] = 0xFFFFFFFF; + PageNumbers[DeviceNumber] = BlockNumber * hNand->DevInfo.PagesPerBlock; + + // To read Factory Bad Block information + if (hNand->DevInfo.NandType == NvOdmNandFlashType_Mlc) + PageNumbers[DeviceNumber] += (hNand->DevInfo.PagesPerBlock - 1); + Status = NvDdkNandReadSpare(hNand, DeviceNumber, PageNumbers, pBlockInfo->pTagBuffer, 0, 4); + if (Status != NvSuccess) + return Status; + if (pBlockInfo->pTagBuffer[0] == 0xFF) + pBlockInfo->IsFactoryGoodBlock = NV_TRUE; + else + pBlockInfo->IsFactoryGoodBlock = NV_FALSE; + + // To check if the block is locked + pBlockInfo->IsBlockLocked = NV_FALSE; + while (i < NDFLASH_CS_MAX) + { + if ((DeviceNumber == hNand->LockAperChipId[i]) && + (BlockNumber > hNand->LockAperStart[i]) && + (BlockNumber < hNand->LockAperEnd[i])) + { + pBlockInfo->IsBlockLocked = NV_TRUE; + break; + } + i++; + } + + if (pBlockInfo->IsFactoryGoodBlock == NV_TRUE) + { + // To read Tag data + PageNumbers[DeviceNumber] = BlockNumber * hNand->DevInfo.PagesPerBlock; + if (SkippedBytesReadEnable) + { + // When skipped bytes are requested complete spare area returned + Status = NvDdkNandReadSpare(hNand, DeviceNumber, PageNumbers, + pBlockInfo->pTagBuffer, 0, hNand->DevInfo.NumSpareAreaBytes); + } + else + { + Status = NvDdkNandRead(hNand, DeviceNumber, PageNumbers, NULL, + pBlockInfo->pTagBuffer,&Numpages,NV_TRUE); + } + if (Status != NvSuccess) + return Status; + } + NvOsMutexUnlock(hNand->hMutex); + return NvSuccess; +} + +static void +PrintBadBlockIfError( + NvDdkNandHandle hNand, + NvU32* pPageNumbers, + NvError Err, + NAND_OP OpType) +{ + NvU32 i; + NvU32 Log2PagesPerBlock; + NvU32 BlkNum; + if (Err != NvSuccess) + { + switch(OpType) + { + case NAND_OP_READ: + NvOsDebugPrintf("\n Failed Ddk Rd. Bad block "); + break; + case NAND_OP_WRITE: + NvOsDebugPrintf("\n Failed Ddk Wr. Bad block"); + break; + case NAND_OP_ERASE: + NvOsDebugPrintf("\n Failed Ddk Erase. Bad block"); + break; + case NAND_OP_CPYBK: + NvOsDebugPrintf("\n Failed Ddk Cpybk. Bad block"); + break; + default: + NvOsDebugPrintf("\n Failed Ddk unknown Operation. Bad block"); + break; + } + NvOsDebugPrintf(" Error code=0x%x ", Err); + Log2PagesPerBlock = NandUtilGetLog2(hNand->DevInfo.PagesPerBlock); + for (i = 0; i < hNand->DevInfo.NumberOfDevices; i++) + { + if (((NvS32)pPageNumbers[i]) == -1) + continue; + BlkNum = pPageNumbers[i] >> Log2PagesPerBlock; + NvOsDebugPrintf(" at chip=%d,block=%d ", i, BlkNum); + } + } +} + +NvU32 DDK_Time =0; + +NvError +NvDdkNandRead( + NvDdkNandHandle hNand, + NvU8 StartDeviceNum, + NvU32* pPageNumbers, + NvU8* const pDataBuffer, + NvU8* const pTagBuffer, + NvU32 *pNoOfPages, + NvBool IgnoreEccError) +{ + NvError e; + NvU8 i; + + #if NAND_RANDOM_FAILURES + static NvU32 FakeErrCnt = 0; + #endif + NV_ASSERT(hNand); + NV_ASSERT(StartDeviceNum < hNand->DevInfo.NumberOfDevices); + NV_ASSERT((pDataBuffer != NULL) || (pTagBuffer != NULL)); + NvOsMutexLock(hNand->hMutex); + + if (DebugPrintEnable) + { + NvOsDebugPrintf("\nDDK_Rd:dev = %d, %s + %s," + " number_of_pages = %d", StartDeviceNum, + (pDataBuffer ? "MAIN":"-"), + (pTagBuffer ? "TAG":"-"), *pNoOfPages); + for (i = 0;i < 8; i++) + { + if (pPageNumbers[i] != 0xFFFFFFFF) + NvOsDebugPrintf("\n Chip: %d, Page = %d, blk = %d\n", + i, pPageNumbers[i], (pPageNumbers[i]/hNand->DevInfo.PagesPerBlock)); + } + } + if (!hNand->IsNandOpen) + { + e = NvError_NandNotOpened; + goto fail; + } + + hNand->Params.pDataBuffer = (NvU8 *)pDataBuffer; + if ((hNand->EccAlgorithm == NvOdmNandECCAlgorithm_BCH) && + (pDataBuffer == NULL) && (pTagBuffer != NULL)) + { + hNand->Params.pDataBuffer = hNand->DataBuffer.pVirtualBuffer; + } + hNand->Params.DeviceNumber = StartDeviceNum; + hNand->Params.pStartPageNumbers = pPageNumbers; + hNand->Params.pDstnPageNumbers = NULL; + hNand->Params.NumberOfPagesCompleted = 0; + hNand->Params.pTagBuffer = pTagBuffer; + hNand->Params.NumberOfPages = *pNoOfPages; + hNand->Params.ColumnNumber = GetColumnNumber(hNand); + hNand->Params.NumSpareAreaBytes = 0; + hNand->Params.OperationName = NandOperation_Read; + #if NAND_DISPLAY_ALL + if (DebugPrintEnable) + { + PRINT_ALL(("\nDDK_Read:dev = %d, page_num = %d, %s + %s," + "number_of_pages = %d", StartDeviceNum, + pPageNumbers[StartDeviceNum], (pDataBuffer ? "MAIN":"-"), + (pTagBuffer ? "TAG":"-"), hNand->Params.NumberOfPages)); + } + #endif + #if NAND_RANDOM_FAILURES + if (DebugPrintEnable) + NvOsDebugPrintf("\r\n Read FakeErrCnt %d", FakeErrCnt); + FakeErrCnt++; + if (!(FakeErrCnt % NUMBER_OF_ITERATIONS_BEFORE_ERROR) && DebugPrintEnable) + { + if(!IgnoreEccError) + { + NvOsDebugPrintf("\n\n\n\n $$$$$$ Returning Read Failure for FAKE BAD BLOCK test"); + for (i = 0;i < 8; i++) + { + if (pPageNumbers[i] != 0xFFFFFFFF) + NvOsDebugPrintf("\n FAKE BB Chip: %d, Page = %d, blk = %d\n", + i, pPageNumbers[i], (pPageNumbers[i]/hNand->DevInfo.PagesPerBlock)); + } + } + } + #endif + e = NandRead(hNand, IgnoreEccError); + *pNoOfPages = hNand->Params.NumberOfPagesCompleted; + // Print Bad block for failure + PrintBadBlockIfError(hNand, pPageNumbers, e, NAND_OP_READ); + #if NAND_RANDOM_FAILURES + if (!(FakeErrCnt % NUMBER_OF_ITERATIONS_BEFORE_ERROR) && DebugPrintEnable) + { + if(!IgnoreEccError) + return NvError_NandReadEccFailed; + } + #endif +fail: + NvOsMutexUnlock(hNand->hMutex); + return e; +} + +NvError +NvDdkNandWrite( + NvDdkNandHandle hNand, + NvU8 StartDeviceNum, + NvU32* pPageNumbers, + const NvU8* pDataBuffer, + const NvU8* pTagBuffer, + NvU32 *pNoOfPages) +{ + NvError e; + static NvU8 flag = 0, i; + NvU32 NumOfPages = 0; + #if NAND_RANDOM_FAILURES + static NvU32 FakeErrCnt = 0; + NvBool RetFail = NV_FALSE; + #endif +#if WRITE_VERIFY + NvU8 * pTempDataBuffer = NULL; + NvU8 * pRefDataBuffer = NULL; + NvU8 * pTempTagBuffer = NULL; + NvU8 * pRefTagBuffer = NULL; + NvU32 TotPageSize = 0; + NvU32 TotTagSize = 0; + NvU32 ErrCnt = 0; + NvError RdError; +#endif + +#if WRITE_VERIFY + if(!DDK_Time) DDK_Time = NvOsGetTimeMS(); + if ((!DebugPrintEnable) && ((NvOsGetTimeMS() - DDK_Time) > 120000)) + { + DebugPrintEnable = 1; + DDK_Time = 0xDEADC0DE; + } +#endif + + NV_ASSERT(pNoOfPages); + NV_ASSERT(hNand); + NV_ASSERT(StartDeviceNum < hNand->DevInfo.NumberOfDevices); + NV_ASSERT((pDataBuffer != NULL) || (pTagBuffer != NULL)); + + NvOsMutexLock(hNand->hMutex); + NumOfPages = *pNoOfPages; + if (!hNand->IsNandOpen) + { + e = NvError_NandNotOpened; + goto fail; + } + if (DebugPrintEnable) + { + NvOsDebugPrintf("\nDDK_Write:device = %d, %s + %s," + " number_of_pages = %d", StartDeviceNum, + (pDataBuffer ? "MAIN":"-"), + (pTagBuffer ? "TAG":"-"), NumOfPages); + for (i = 0;i < 8; i++) + { + if (pPageNumbers[i] != 0xFFFFFFFF) + NvOsDebugPrintf("\n Chip: %d, Page = %d\n", i, pPageNumbers[i]); + } + } + #if WRITE_VERIFY + TotPageSize = NumOfPages * hNand->DevInfo.PageSize; + if (pDataBuffer) + { + pTempDataBuffer = NvOsAlloc(TotPageSize); + NV_ASSERT(pTempDataBuffer); + pRefDataBuffer = NvOsAlloc(TotPageSize); + NV_ASSERT(pRefDataBuffer); + NvOsMemset(pRefDataBuffer, 0xFF, TotPageSize); + } + + TotTagSize = NumOfPages * hNand->DevInfo.TagSize; + if (pTagBuffer) + { + pTempTagBuffer = NvOsAlloc(TotTagSize); + NV_ASSERT(pTempTagBuffer); + pRefTagBuffer = NvOsAlloc(TotTagSize); + NV_ASSERT(pRefTagBuffer); + NvOsMemset(pRefTagBuffer, 0xFF, TotTagSize); + } +#if WRITE_VERIFY + if (DDK_Time == 0xDEADC0DE) + DebugPrintEnable = 0; +#endif + RdError = NvDdkNandRead(hNand, StartDeviceNum, pPageNumbers, + pTempDataBuffer, pTempTagBuffer, &NumOfPages, NV_TRUE); +#if WRITE_VERIFY + if (DDK_Time == 0xDEADC0DE) + DebugPrintEnable = 1; +#endif + + if (RdError != NvSuccess) + { + NvOsDebugPrintf("rd in wr fail. errcode: %d", RdError); + } + if (pTempDataBuffer != NULL) + { + i = 0; + while (TotPageSize--) + { + if (*(pTempDataBuffer + i) != *(pRefDataBuffer + i)) + { + ErrCnt++; + i++; + } + } + if (ErrCnt) + { + NvOsDebugPrintf("\nWrong Write, Numof Pages: %d, Cnt: %d", *pNoOfPages, ErrCnt); + + for (i = 0;i < 8; i++) + { + if (pPageNumbers[i] != 0xFFFFFFFF) + NvOsDebugPrintf("\n Chip: %d, Page = %d, blk = %d\n", + i, pPageNumbers[i], (pPageNumbers[i]/hNand->DevInfo.PagesPerBlock)); + } + } + } + if (pTempTagBuffer != NULL) + { + ErrCnt = 0; + i = 0; + while (TotTagSize--) + { + if (*(pTempTagBuffer + i) != *(pRefTagBuffer + i)) + { + ErrCnt++; + i++; + } + } + if (ErrCnt) + { + NvOsDebugPrintf("\nWrong Tag, Numof Pages: %d, Cnt : %d", *pNoOfPages, ErrCnt); + } + } + + #endif + NumOfPages = *pNoOfPages; + + hNand->Params.pDataBuffer = (NvU8 *)pDataBuffer; + if ((hNand->EccAlgorithm == NvOdmNandECCAlgorithm_BCH) && + (pDataBuffer == NULL) && (pTagBuffer != NULL)) + { + hNand->Params.pDataBuffer = hNand->DataBuffer.pVirtualBuffer; + } + + if ((hNand->EccAlgorithm == NvOdmNandECCAlgorithm_BCH) && + (pDataBuffer == NULL) && (pTagBuffer != NULL)) + NV_ASSERT(NV_FALSE); + + hNand->Params.DeviceNumber = StartDeviceNum; + hNand->Params.pStartPageNumbers = pPageNumbers; + hNand->Params.pDstnPageNumbers = NULL; + hNand->Params.NumberOfPagesCompleted = 0; + hNand->Params.pTagBuffer = (NvU8 *)pTagBuffer; + hNand->Params.NumberOfPages = *pNoOfPages; + hNand->Params.ColumnNumber = GetColumnNumber(hNand); + hNand->Params.NumSpareAreaBytes = 0; + hNand->Params.OperationName = NandOperation_Write; + if (flag) + { + for (i = 0;i < 8; i++) + { + if (pPageNumbers[i] != 0xFFFFFFFF) + NvOsDebugPrintf("In DDK write %d: PhysBlkNum = %d PageOffset = %d, Page = %d\n", + i, pPageNumbers[i] / hNand->DevInfo.PagesPerBlock, + pPageNumbers[i] % hNand->DevInfo.PagesPerBlock, + pPageNumbers[i]); + } + } + #if NAND_RANDOM_FAILURES + if (DebugPrintEnable) + NvOsDebugPrintf("\r\n Write FakeErrCnt %d", FakeErrCnt); + FakeErrCnt++; + if (!(FakeErrCnt % NUMBER_OF_ITERATIONS_BEFORE_ERROR) && DebugPrintEnable) + if (hNand->Params.NumberOfPages > 1) + { + hNand->Params.NumberOfPages -= 1; + NvOsDebugPrintf("\n\n\n\n $$$$$$ Returning Write Failure for FAKE BAD BLOCK test"); + for (i = 0;i < 8; i++) + { + if (pPageNumbers[i] != 0xFFFFFFFF) + NvOsDebugPrintf("\n FAKE BB Chip: %d, Page = %d, blk = %d\n", + i, pPageNumbers[i], (pPageNumbers[i]/hNand->DevInfo.PagesPerBlock)); + } + RetFail = NV_TRUE; + } + + #endif + e = NandWrite(hNand); + *pNoOfPages = hNand->Params.NumberOfPagesCompleted; + if (flag) + { + NvOsDebugPrintf("In DDK write: PagesReq = %d, pages trans = %d\n", + hNand->Params.NumberOfPages, *pNoOfPages); + } +#if WRITE_VERIFY + NumOfPages = *pNoOfPages; + if (DDK_Time == 0xDEADC0DE) + DebugPrintEnable = 0; + RdError = NvDdkNandRead(hNand, StartDeviceNum, pPageNumbers, + pTempDataBuffer, pTempTagBuffer, &NumOfPages, NV_TRUE); + if (DDK_Time == 0xDEADC0DE) + DebugPrintEnable = 1; + TotPageSize = NumOfPages * hNand->DevInfo.PageSize; + TotTagSize = NumOfPages * hNand->DevInfo.TagSize; + + if (RdError != NvSuccess) + { + NvOsDebugPrintf("rd after wr fail. errcode: %d", RdError); + } + if (pTempDataBuffer != NULL) + { + i = 0; + while (TotPageSize--) + { + if (*(pTempDataBuffer + i) != *(pDataBuffer + i)) + { + ErrCnt++; + i++; + } + } + if (ErrCnt) + { + NvOsDebugPrintf("\nrd after wr Wrong Write, Numof Pages: %d, Cnt: %d", + *pNoOfPages, ErrCnt); + + for (i = 0;i < 8; i++) + { + if (pPageNumbers[i] != 0xFFFFFFFF) + NvOsDebugPrintf("\n rd after wr Chip: %d, Page = %d\n", i, pPageNumbers[i]); + } + } + } + if (pTempTagBuffer != NULL) + { + ErrCnt = 0; + i = 0; + while (TotTagSize--) + { + if (*(pTempTagBuffer + i) != *(pTagBuffer + i)) + { + ErrCnt++; + i++; + } + } + if (ErrCnt) + { + NvOsDebugPrintf("\nrd after wr Wrong Tag, Numof Pages: %d, Cnt : %d", + *pNoOfPages, ErrCnt); + } + } + + if (pTempDataBuffer) + { + NvOsFree(pTempDataBuffer); + pTempDataBuffer = NULL; + } + if (pTempTagBuffer) + { + NvOsFree(pTempTagBuffer); + pTempTagBuffer = NULL; + } + if (pRefDataBuffer) + { + NvOsFree(pRefDataBuffer); + pRefDataBuffer = NULL; + } + if (pRefTagBuffer) + { + NvOsFree(pRefTagBuffer); + pRefTagBuffer = NULL; + } +#endif + #if NAND_RANDOM_FAILURES + if (RetFail && DebugPrintEnable) + return NvError_NandWriteFailed; + #endif +fail: + NvOsMutexUnlock(hNand->hMutex); + return e; +} + +NvError +NvDdkNandErase( + NvDdkNandHandle hNand, + NvU8 StartDeviceNum, + NvU32* pPageNumbers, + NvU32* pNumberOfBlocks) +{ + NvError e = NvError_Success; + NvU32 i; + NvU32 DeviceNumber; + NvU32 NumberOfBlocks; + NvU32 NumberOfBlocksToBeErased; + NvU32 InterleaveBlockNumber; + NvU32 FirstDeviceNum; + NvU32 RetryCount; + #if NAND_RANDOM_FAILURES + static NvU32 FakeErrCnt = 0; + FakeErrCnt++; + + if (!(FakeErrCnt % NUMBER_OF_ITERATIONS_BEFORE_ERROR)) + { + if (DebugPrintEnable) + { + NvOsDebugPrintf("\n\n\n\n $$$$$$ Returning Erase Failure for FAKE BAD BLOCK test"); + for (i = 0;i < 8; i++) + { + if (pPageNumbers[i] != 0xFFFFFFFF) + NvOsDebugPrintf("\n FAKE BB Chip: %d, Page = %d, blk = %d\n", + i, pPageNumbers[i], (pPageNumbers[i]/hNand->DevInfo.PagesPerBlock)); + } + } + return NvError_NandEraseFailed; + } + #endif + + NV_ASSERT(hNand); + NV_ASSERT(StartDeviceNum < hNand->DevInfo.NumberOfDevices); + NvOsMutexLock(hNand->hMutex); + if (!hNand->IsNandOpen) + { + e = NvError_NandNotOpened; + goto fail; + } + + if (DebugPrintEnable) + { + NvOsDebugPrintf("\nDDK_Ers:dev = %d," + " number of blks = %d", StartDeviceNum, + *pNumberOfBlocks); + for (i = 0;i < 8; i++) + { + if (pPageNumbers[i] != 0xFFFFFFFF) + NvOsDebugPrintf("\n Chip: %d, Page = %d, blk = %d\n", + i, pPageNumbers[i], (pPageNumbers[i]/hNand->DevInfo.PagesPerBlock)); + } + } + + for (RetryCount = 0; RetryCount < DDK_NAND_MAX_ERASE_RETRY; RetryCount++) + { + InterleaveBlockNumber = 0; + NumberOfBlocks = *pNumberOfBlocks; + + // Calculate number of CS interleaved in the current transaction + GetNumOfCsInterleaved(hNand, pPageNumbers); + + hNand->Params.NumberOfPagesCompleted = 0; + hNand->Params.OperationName = NandOperation_Erase; + SetCommandQueueOperationState(hNand, 0, NULL); + do + { + NumberOfBlocksToBeErased = + (NumberOfBlocks > hNand->NumberOfChipsToBeInterleaved) ? + hNand->NumberOfChipsToBeInterleaved : NumberOfBlocks; + FirstDeviceNum = StartDeviceNum; + // Issue erase command for all blocks present in interleave way + for (i = 0; i < NumberOfBlocksToBeErased; i++) + { + hNand->Params.StartPageNumber = pPageNumbers[StartDeviceNum] + + (InterleaveBlockNumber * hNand->DevInfo.PagesPerBlock); + DeviceNumber = hNand->PhysicalDeviceNumber[StartDeviceNum]; + + if (hNand->Params.NumberOfPagesCompleted > + hNand->NumberOfChipsToBeInterleaved) + { + e = GetOperationStatus(hNand, DeviceNumber); + if (e != NvError_Success) + NV_CHECK_ERROR_CLEANUP(NvError_NandEraseFailed); + } + // Set up registers. + SetupRegisters(hNand, NandOperation_Erase); + SetupAddressAndDeviceReg(hNand, DeviceNumber, 0); + // Set interrupts. + SetupInterrupt(hNand, NandOperation_Erase); + #if NAND_DISPLAY_ALL + if (DebugPrintEnable) + { + PRINT_ALL(("\nErs DevNum = %d, PageNum = %d", + DeviceNumber, hNand->Params.StartPageNumber)); + } + #endif + // Start Nand operation. + StartNandOperation(hNand); + e = WaitForCommandDone(hNand); + // Error can be returned only in last attempt + if (RetryCount == (DDK_NAND_MAX_ERASE_RETRY - 1)) + NV_CHECK_ERROR_CLEANUP(e); + else + { + // Retry in case of error till maximum attempts + if (e != NvError_Success) + goto LblNextTry; + } + do + { + StartDeviceNum++; + if (StartDeviceNum >= NDFLASH_CS_MAX) + { + StartDeviceNum = 0; + InterleaveBlockNumber++; + } + } + while (pPageNumbers[StartDeviceNum] == 0xFFFFFFFF); + hNand->Params.NumberOfPagesCompleted++; + } + NumberOfBlocks -= NumberOfBlocksToBeErased; + }while (NumberOfBlocks); + // Check status of erase command for all blocks present in interleave way + StartDeviceNum = FirstDeviceNum; + for (i = 0; i < hNand->NumberOfChipsToBeInterleaved; i++) + { + DeviceNumber = hNand->PhysicalDeviceNumber[StartDeviceNum]; + e = GetOperationStatus(hNand, DeviceNumber); + if (e != NvSuccess) + NV_CHECK_ERROR_CLEANUP(NvError_NandEraseFailed); + do + { + StartDeviceNum++; + if (StartDeviceNum >= NDFLASH_CS_MAX) + { + StartDeviceNum = 0; + } + } + while (pPageNumbers[StartDeviceNum] == 0xFFFFFFFF); + } +LblNextTry: + if (e == NvError_Success) + { + // Return if success + break; + } + } + +fail: + if (e == NvError_Timeout) + { + NAND_ASSERT(NvError_Timeout); + DumpRegData(hNand); + NvRmModuleReset(hNand->RmDevHandle, NvRmModuleID_Nand); + SetTimingRegVal(hNand, NV_FALSE); + // Restore the NAND lock cfg that was stored during previous Suspend, + // as locks should have got released due to above reset operation. + NandRestoreLocks(hNand); + } + // Return the number of blocks erased + *pNumberOfBlocks = hNand->Params.NumberOfPagesCompleted; + hNand->OperationStatus = e; + // Print Bad block for failure + PrintBadBlockIfError(hNand, pPageNumbers, e, NAND_OP_ERASE); + NvOsMutexUnlock(hNand->hMutex); + return e; +} + +static NvError NandCopyback(NvDdkNandHandle hNand, NvBool IgnoreEccError) +{ + NvError Error = NvSuccess; + NandParams *p = &hNand->Params; + NvU32* pSourcePageNumbers = p->pStartPageNumbers; + NvU32* pDstnPageNumbers = p->pDstnPageNumbers; + NvU32 NoOfPages; + NvU32 i; + NvU32 NoOfFullPg2Copyback = p->NumberOfPages; + NvU8 DeviceNum = p->DeviceNumber; + NvU8 DstDeviceNum = p->DstnDeviceNumber; + NvU32 SrcPgNums[MAX_NAND_SUPPORTED]; + NvU32 DstPgNums[MAX_NAND_SUPPORTED] ; + NvU32 NumOfPagesTransferred = 0; + #if ENABLE_INTERNAL_COPYBACK + NvU32 SrcBlock[MAX_NAND_SUPPORTED]; + NvU32 DstnBlock[MAX_NAND_SUPPORTED]; + NvU32 SrcPlane[MAX_NAND_SUPPORTED]; + NvU32 DstnPlane[MAX_NAND_SUPPORTED]; + NvU32 BlocksPerZone = hNand->DevInfo.NoOfBlocks / hNand->DevInfo.ZonesPerDevice ; + NvBool DoInternalCopyBk = NV_FALSE; + #endif + NvU32 PagesPerInterleaveColumn; + NvBool IsTagRequired = NV_FALSE; + #if WRITE_VERIFY + NvU32 TotPageSize = 0; + NvU32 ErrCnt = 0; + NvError RdErr; + #endif + if (DebugPrintEnable) + { + NvOsDebugPrintf("\nDDK_Cpbk:Srcdev = %d, Dstdev = %d," + " number_of_pages = %d", DeviceNum, DstDeviceNum, + hNand->Params.NumberOfPages); + for (i = 0;i < 8; i++) + { + if (pSourcePageNumbers[i] != 0xFFFFFFFF) + NvOsDebugPrintf("\n SrcChip: %d, Page = %d, blk = %d\n", + i, pSourcePageNumbers[i], (pSourcePageNumbers[i]/hNand->DevInfo.PagesPerBlock)); + if (pDstnPageNumbers[i] != 0xFFFFFFFF) + NvOsDebugPrintf("\n DstChip: %d, Page = %d, blk = %d\n", + i, pDstnPageNumbers[i], (pDstnPageNumbers[i]/hNand->DevInfo.PagesPerBlock)); + } + } + + // Calculate number of CS interleaved in the current transaction + GetNumOfCsInterleaved(hNand, pSourcePageNumbers); + + for (i = 0; i < NDFLASH_CS_MAX; i++) + { + SrcPgNums[i] = pSourcePageNumbers[i]; + DstPgNums[i] = pDstnPageNumbers[i]; + #if ENABLE_INTERNAL_COPYBACK + SrcBlock[i] = (SrcPgNums[i] / hNand->DevInfo.PagesPerBlock); + DstnBlock[i] = (DstPgNums[i] / hNand->DevInfo.PagesPerBlock); + SrcPlane[i] = SrcBlock[i] / BlocksPerZone; + DstnPlane[i] = DstnBlock[i] / BlocksPerZone; + #endif + } + + if ((!(pSourcePageNumbers[DeviceNum] % hNand->DevInfo.PagesPerBlock)) && + (NoOfFullPg2Copyback == 1)) + IsTagRequired = NV_TRUE; + + while (NoOfFullPg2Copyback > 0) + { + #if ENABLE_INTERNAL_COPYBACK + for (i = 0; i < hNand->NumberOfChipsToBeInterleaved; i++) + { + if ((SrcPgNums[i] != -1) && + (DstPgNums[i] != -1) && + (SrcPlane[i] == DstnPlane[i]) && + ((SrcBlock[i] & 0x1) == (DstnBlock[i] & 0x1))) + DoInternalCopyBk = NV_TRUE; + } + if (DoInternalCopyBk) + { + NoOfPages = NoOfFullPg2Copyback; + Error = NandInternalCopyback(hNand); + if (Error != NvSuccess) + { + Error = NvError_NandCopyBackFailed; + NumOfPagesTransferred = p->NumberOfPagesCompleted; + goto fail; + } + NumOfPagesTransferred = NoOfPages; + } + else + #endif + { + NoOfPages = hNand->NandCapability.MaxDataTransferSize / + hNand->DevInfo.PageSize; + if (NoOfFullPg2Copyback < NoOfPages) + { + NoOfPages = NoOfFullPg2Copyback; + } + + p->DeviceNumber = DeviceNum; + p->NumberOfPagesCompleted = 0; + p->ColumnNumber = GetColumnNumber(hNand); + p->OperationName = NandOperation_Read; + p->NumberOfPages = NoOfPages; + p->pStartPageNumbers = SrcPgNums; + p->pDataBuffer = hNand->DataBuffer.pVirtualBuffer; + if (IsTagRequired) + { + p->pTagBuffer = hNand->TagBuffer.pVirtualBuffer; + } + else + { + p->pTagBuffer = NULL; + } + + Error = NandRead(hNand, IgnoreEccError); + if (Error != NvSuccess) + { + Error = NvError_NandReadEccFailed; + PrintBadBlockIfError(hNand, SrcPgNums, Error, NAND_OP_READ); + goto fail; + } + p->DeviceNumber = DstDeviceNum; + p->NumberOfPagesCompleted = 0; + p->OperationName = NandOperation_Write; + p->pStartPageNumbers = DstPgNums; + p->pDataBuffer = hNand->DataBuffer.pVirtualBuffer; + if (IsTagRequired) + { + p->pTagBuffer = hNand->TagBuffer.pVirtualBuffer; + } + else + { + p->pTagBuffer = NULL; + } + Error = NandWrite(hNand); + if (Error != NvSuccess) + { + Error = NvError_NandWriteFailed; + PrintBadBlockIfError(hNand, DstPgNums, Error, NAND_OP_WRITE); + goto fail; + } + +#if WRITE_VERIFY + p->DeviceNumber = DstDeviceNum; + p->NumberOfPagesCompleted = 0; + p->ColumnNumber = 0; + p->OperationName = NandOperation_Read; + p->NumberOfPages = NoOfPages; + p->pStartPageNumbers = DstPgNums; + p->pDataBuffer = s_WriteVerifyBuffer; + TotPageSize = NoOfPages * hNand->DevInfo.PageSize; + RdErr = NandRead(hNand, IgnoreEccError); + if (RdErr != NvSuccess) + { + PrintBadBlockIfError(hNand, SrcPgNums, Error, NAND_OP_READ); + NvOsDebugPrintf("rd in cpbk validation fail.post write errcode: %d", Error); + } + for (i = 0; i < TotPageSize; i++) + { + if (s_WriteVerifyBuffer[i] != hNand->DataBuffer.pVirtualBuffer[i]) + { + ErrCnt++; + } + } + if (ErrCnt) + { + NvOsDebugPrintf("\nWrong Cpbk post write, Numof Pages: %d, Cnt: %d", + NoOfPages, ErrCnt); + } +#endif + NumOfPagesTransferred += NoOfPages; + NoOfFullPg2Copyback -= NoOfPages; + PagesPerInterleaveColumn = NoOfPages / hNand->NumberOfChipsToBeInterleaved; + for (i = 0; i < NDFLASH_CS_MAX; i++) + { + if (SrcPgNums[i] != 0xFFFFFFFF) + { + SrcPgNums[i] += PagesPerInterleaveColumn; + } + if (DstPgNums[i] != 0xFFFFFFFF) + { + DstPgNums[i] += PagesPerInterleaveColumn; + } + } + } + } +fail: + p->NumberOfPagesCompleted = NumOfPagesTransferred; + return Error; +} + +#if ENABLE_INTERNAL_COPYBACK +static NvError NandInternalCopyback(NvDdkNandHandle hNand) +{ + NandParams *p = &hNand->Params; + NvError e = NvSuccess; + NvU32 i = 0; + NvU32 j = 0; + NvU8 DeviceNumber = 0; + NvU8 StartDeviceNumber = 0; + NvU32 PageNumber = 0; + NvU32 ReadPageNumberOffset = 0; + NvU32 WritePageNumberOffset = 0; + NvU32 NumberOfPages = 0; + + SetCommandQueueOperationState(hNand, p->NumberOfPages, NULL); + + // Calculate number of CS interleaved in the current transaction + GetNumOfCsInterleaved(hNand, p->pSourcePageNumbers); + + for (i = 0; i < p->NumberOfPages; i += NumberOfPages) + { + // Setup for copyback read. + SetupRegisters(hNand, NandOperation_CopybackRead); + StartDeviceNumber = p->DeviceNumber; + NumberOfPages = 0; + for (j = 0; j < hNand->NumberOfChipsToBeInterleaved; j++) + { + SkipUnusedDevices(hNand, p->pStartPageNumbers, &(p->DeviceNumber), + &ReadPageNumberOffset); + DeviceNumber = hNand->PhysicalDeviceNumber[p->DeviceNumber]; + PageNumber = p->pStartPageNumbers[p->DeviceNumber]; + SetupAddressAndDeviceReg(hNand, DeviceNumber, + (PageNumber + ReadPageNumberOffset)); + SetupInterrupt(hNand, NandOperation_Read); + // Start Nand operation. + StartNandOperation(hNand); + NV_CHECK_ERROR_CLEANUP(WaitForCommandDone(hNand)); + p->DeviceNumber++; + if (p->DeviceNumber == hNand->NumOfActiveDevices) + { + p->DeviceNumber = 0; + ReadPageNumberOffset++; + } + NumberOfPages++; + if ((i + NumberOfPages) == p->NumberOfPages) + break; + } + // Setup for copyback program. + p->DeviceNumber = StartDeviceNumber; + SetupRegisters(hNand, NandOperation_CopybackProgram); + NumberOfPages = 0; + p->DeviceNumber = StartDeviceNumber; + for (j = 0; j < hNand->NumberOfChipsToBeInterleaved; j++) + { + SkipUnusedDevices(hNand, p->pDstnPageNumbers, &(p->DeviceNumber), + &WritePageNumberOffset); + DeviceNumber = hNand->PhysicalDeviceNumber[p->DeviceNumber]; + PageNumber = p->pDstnPageNumbers[p->DeviceNumber]; + SetupAddressAndDeviceReg(hNand, DeviceNumber, + (PageNumber + WritePageNumberOffset)); + SetupInterrupt(hNand, NandOperation_Write); + // Start Nand operation. + StartNandOperation(hNand); + NV_CHECK_ERROR_CLEANUP(WaitForCommandDone(hNand)); + p->DeviceNumber++; + if (p->DeviceNumber == hNand->NumOfActiveDevices) + { + p->DeviceNumber = 0; + WritePageNumberOffset++; + } + NumberOfPages++; + if ((i + NumberOfPages) == p->NumberOfPages) + break; + } + // Check the status. + p->DeviceNumber = StartDeviceNumber; + SetupRegisters(hNand, NandOperation_CopybackProgram); + NumberOfPages = 0; + p->DeviceNumber = StartDeviceNumber; + for (j = 0; j < hNand->NumberOfChipsToBeInterleaved; j++) + { + SkipUnusedDevices(hNand, p->pDstnPageNumbers, &(p->DeviceNumber), + NULL); + DeviceNumber = hNand->PhysicalDeviceNumber[p->DeviceNumber]; + NV_CHECK_ERROR_CLEANUP(GetOperationStatus(hNand, DeviceNumber)); + p->DeviceNumber++; + if (p->DeviceNumber == hNand->NumOfActiveDevices) + { + p->DeviceNumber = 0; + } + p->NumberOfPagesCompleted++; + NumberOfPages++; + if ((i + NumberOfPages) == p->NumberOfPages) + break; + } + } +fail: + NAND_ASSERT(e); + if (hNand->IsCommandQueueOperation) + { + // Number of pages transferred to be divided by 2 for copy back as each + // copy back command requires two sets of command queue commands.i.e. one + // for copy-back-read & another for copy-back-write + if (e == NvError_NandCommandQueueError) + p->NumberOfPagesCompleted = (hNand->NumOfPagesTransferred / 2); + hNand->IsCommandQueueOperation = NV_FALSE; + } + if (e == NvError_Timeout) + { + DumpRegData(hNand); + NvRmModuleReset(hNand->RmDevHandle, NvRmModuleID_Nand); + SetTimingRegVal(hNand, NV_FALSE); + // We must restore the lock state after resets + NandRestoreLocks(hNand); + } + hNand->OperationStatus = e; + return e; +} +#endif + +NvError +NvDdkNandCopybackPages( + NvDdkNandHandle hNand, + NvU8 SrcStartDeviceNum, + NvU8 DstStartDeviceNum, + NvU32* pSrcPageNumbers, + NvU32* pDestPageNumbers, + NvU32 *pNoOfPages, + NvBool IgnoreEccError) +{ + NvError Error; + #if NAND_RANDOM_FAILURES + static NvU32 FakeErrCnt = 0; + NvBool RetFail = NV_FALSE; + NvU32 i = 0; + #endif + NV_ASSERT(hNand); + NV_ASSERT(*pNoOfPages); + NV_ASSERT(SrcStartDeviceNum < NDFLASH_CS_MAX); + NV_ASSERT(DstStartDeviceNum < NDFLASH_CS_MAX); + NV_ASSERT(hNand->IsNandOpen); + NvOsMutexLock(hNand->hMutex); + + hNand->Params.DeviceNumber = SrcStartDeviceNum; + hNand->Params.DstnDeviceNumber = DstStartDeviceNum; + hNand->Params.pStartPageNumbers = pSrcPageNumbers; + hNand->Params.pDstnPageNumbers = pDestPageNumbers; + hNand->Params.pDataBuffer = NULL; + hNand->Params.pTagBuffer = NULL; + hNand->Params.NumberOfPages = *pNoOfPages; + hNand->Params.NumSpareAreaBytes = 0; + hNand->Params.OperationName = NandOperation_CopybackRead; + #if NAND_DISPLAY_ALL + if (DebugPrintEnable) + { + PRINT_ALL(("\nDDk_CpyBk: Dev1 = 0x%x, Dev2 = 0x%x, SrcPage = 0x%x, DstnPage = 0x%x, " + "NoOfPages = 0x%x", SrcStartDeviceNum, DstStartDeviceNum, + pSrcPageNumbers[SrcStartDeviceNum], + pDestPageNumbers[DstStartDeviceNum], + *pNoOfPages)); + } + #endif + #if NAND_RANDOM_FAILURES + if (DebugPrintEnable) + NvOsDebugPrintf("\r\n copyBack FakeErrCnt %d", FakeErrCnt); + FakeErrCnt++; + if (!(FakeErrCnt % NUMBER_OF_ITERATIONS_BEFORE_ERROR) && DebugPrintEnable) + if (hNand->Params.NumberOfPages > 1) + { + hNand->Params.NumberOfPages -= 1; + + NvOsDebugPrintf("\n\n\n\n $$$$$$ Returning copyback Failure for FAKE BAD BLOCK test"); + for (i = 0;i < 8; i++) + { + if (pSrcPageNumbers[i] != 0xFFFFFFFF) + NvOsDebugPrintf("\n FAKE BB Chip: %d, Page = %d, blk = %d\n", + i, pDestPageNumbers[i], (pDestPageNumbers[i]/hNand->DevInfo.PagesPerBlock)); + } + RetFail = NV_TRUE; + } + #endif + Error = NandCopyback(hNand, IgnoreEccError); + *pNoOfPages = hNand->Params.NumberOfPagesCompleted; + #if NAND_RANDOM_FAILURES + if (RetFail && DebugPrintEnable) + return NvError_NandWriteFailed; + #endif + NvOsMutexUnlock(hNand->hMutex); + return Error; +} + +NvError +NvDdkNandGetDeviceInfo( + NvDdkNandHandle hNand, + NvU8 DeviceNumber, + NvDdkNandDeviceInfo* pDeviceInfo) +{ + NvError e; + NvU32 ReadID = 0; + NvU32 BlockSize = 0; + NvU32 TempValue = 0; + NvU32 SpareSizePer512Bytes = 0; + NvU32 SpareAreaSize = 0; + const NvU32 TValueArray[] = {0, 1, 2, 0}; + NvOdmNandFlashParams *pFlashParams; + + /* validate input params */ + NV_ASSERT(hNand); + NV_ASSERT(pDeviceInfo); + NV_ASSERT(DeviceNumber < NDFLASH_CS_MAX); + NV_ASSERT(hNand->IsNandOpen); + + NvOsMutexLock(hNand->hMutex); + + SetCommandQueueOperationState(hNand, 0, NULL); + NV_CHECK_ERROR_CLEANUP(NandReadID(hNand, DeviceNumber, &ReadID, NV_FALSE)); + pFlashParams = NvOdmNandGetFlashInfo(ReadID); + if (!pFlashParams) + { + NV_CHECK_ERROR_CLEANUP(NvError_NandFlashNotSupported); + } + else + NvOsMemcpy(&(hNand->FlashParams), pFlashParams, + sizeof(NvOdmNandFlashParams)); + hNand->DevInfo.VendorId = hNand->FlashParams.VendorId; + hNand->DevInfo.DeviceId = hNand->FlashParams.DeviceId; + hNand->DevInfo.NandType = hNand->FlashParams.NandType; + // Currently internal copy back is disabled, till error handling in FTL is + //fixed. +// hNand->IsCopybackSupported = pFlashParams->IsCopyBackCommandSupported; + hNand->IsCopybackSupported = NV_FALSE; + + if (hNand->FlashParams.NandDeviceType == NvOdmNandDeviceType_Type2) + { + TempValue = NV_DRF_VAL(DDK_NAND, ID_DECODE, PAGE_SIZE, ReadID); + NV_ASSERT(TempValue <= 3); + hNand->DevInfo.PageSize = (1 << (11 + TempValue)); + + // If MSB bit is Reserved it is unknown flash. + // This should be 0. This can be updated if any flash supports. + TempValue = NV_DRF_VAL(DDK_42NM_NAND, ID_DECODE, BLOCK_SIZE_MSB, ReadID); + if (TempValue) + NV_ASSERT(0); + + // Extracting the block size + TempValue = NV_DRF_VAL(DDK_NAND, ID_DECODE, BLOCK_SIZE, ReadID); + NV_ASSERT(TempValue <= 3 ); + BlockSize = (1 << (17 + TempValue)); + + // If MSB bit is Reserved it is unknown flash. + // This should be 0. This can be updated if any flash supports. + TempValue = + NV_DRF_VAL(DDK_42NM_NAND, ID_DECODE, REDUNDANT_AREA_SIZE_MSB, ReadID); + if (TempValue) + NV_ASSERT(0); + + // Extracting the redundant data size. + TempValue = + NV_DRF_VAL(DDK_42NM_NAND, ID_DECODE, REDUNDANT_AREA_SIZE, ReadID); + if (TempValue == 1) + SpareAreaSize = 128; + else if (TempValue == 2) + SpareAreaSize = 218; + else + NV_ASSERT(0); + + // Bus width cannot be decoded from ReadId like other Nand Flashes. + // So bus width is 8 for 42nm Falsh. + hNand->DevInfo.BusWidth = 8; + } + else + { + TempValue = NV_DRF_VAL(DDK_NAND, ID_DECODE, PAGE_SIZE, ReadID); + NV_ASSERT(TempValue <= 3); + hNand->DevInfo.PageSize = (1 << (10 + TempValue)); + // Extracting the block size + TempValue = NV_DRF_VAL(DDK_NAND, ID_DECODE, BLOCK_SIZE, ReadID); + NV_ASSERT(TempValue <= 3 ); + BlockSize = (1 << (16 + TempValue)); + + // Extracting redundant Area size per 512 bytes + TempValue = NV_DRF_VAL(DDK_NAND, ID_DECODE, REDUNDANT_AREA_SIZE, ReadID); + // If TempValue calculated above is 0 then redundant area per 512 bytes is + // 8 bytes and if it is 1 then redundant area per 512 bytes is 16 bytes. + SpareSizePer512Bytes = TempValue? 16: 8; + // Calculate spare area size per flash page, from the + // spare area per 512 bytes read from the flash. + SpareAreaSize = ((hNand->DevInfo.PageSize / 512) * + SpareSizePer512Bytes); + + // Extracting flash organization 8bit or 16 bit + TempValue = NV_DRF_VAL(DDK_NAND, ID_DECODE, BUS_WIDTH, ReadID); + hNand->DevInfo.BusWidth = TempValue? 16: 8; + } + + hNand->SpareAreaSize = SpareAreaSize; + hNand->DevInfo.PagesPerBlock = BlockSize / hNand->DevInfo.PageSize; + if (hNand->NandCapability.IsEccSupported) + { + if (pFlashParams->EccAlgorithm == NvOdmNandECCAlgorithm_BCH) + { + if (hNand->IsBCHEccSupported) + { + hNand->EccAlgorithm = ECCAlgorithm_BCH; + hNand->TValue = TValueArray[pFlashParams->ErrorsCorrectable]; + } + else // fall back to next best Ecc algorithm available, for ap15 + { + hNand->EccAlgorithm = ECCAlgorithm_ReedSolomon; + hNand->TValue = TValueArray[pFlashParams->ErrorsCorrectable]; + } + } + else if (pFlashParams->EccAlgorithm == NvOdmNandECCAlgorithm_ReedSolomon) + { + hNand->EccAlgorithm = ECCAlgorithm_ReedSolomon; + hNand->TValue = TValueArray[pFlashParams->ErrorsCorrectable]; + } + else if (pFlashParams->EccAlgorithm == NvOdmNandECCAlgorithm_Hamming) + hNand->EccAlgorithm = ECCAlgorithm_Hamming; + else if (pFlashParams->EccAlgorithm == NvOdmNandECCAlgorithm_NoEcc) + { + hNand->EccAlgorithm = ECCAlgorithm_None; + hNand->NandCapability.IsEccSupported = NV_FALSE; + } + else + NV_ASSERT(NV_FALSE); + } + hNand->DevInfo.TagOffset = GetNumOfParityBytesForMainArea(hNand) + + (hNand->FlashParams.SkippedSpareBytes << 2); + + // Redundant area size per page to write any Tag information. This will be + // calculated as TagSize = spareAreaSize - mainAreaEcc - SpareAreaEcc. + if (hNand->EccAlgorithm == ECCAlgorithm_None) + hNand->DevInfo.TagSize = SpareAreaSize; + else + hNand->DevInfo.TagSize = SpareAreaSize - + GetNumOfParityBytesForMainArea(hNand) - + NDFLASH_PARITY_SZ_HAMMING_SPARE; + hNand->DevInfo.TagSize -= (hNand->FlashParams.SkippedSpareBytes << 2); + hNand->DevInfo.NumSpareAreaBytes = SpareAreaSize; + NV_ASSERT(SpareAreaSize > hNand->DevInfo.TagOffset); + if (hNand->DevInfo.TagSize % 4) + { + hNand->DevInfo.TagSize -= (hNand->DevInfo.TagSize % 4); + } + // Assert here if Tag size is less than 12 bytes, as 12 bytes are required + // for storing bad block management etc. + NV_ASSERT(hNand->DevInfo.TagSize >= 8); +#if 1 + hNand->DevInfo.NoOfBlocks = (hNand->FlashParams.BlocksPerZone) * + (hNand->FlashParams.ZonesPerDevice); +#else + hNand->DevInfo.NoOfBlocks = 2048; +#endif + hNand->DevInfo.DeviceCapacityInKBytes = hNand->DevInfo.NoOfBlocks * + (BlockSize / 1024); + hNand->DevInfo.InterleaveCapability = hNand->FlashParams.InterleaveCapability; + hNand->DevInfo.ZonesPerDevice = hNand->FlashParams.ZonesPerDevice; + hNand->DevInfo.NumberOfDevices = hNand->NumOfActiveDevices; + NvOsMemcpy(pDeviceInfo, &(hNand->DevInfo), sizeof(NvDdkNandDeviceInfo)); +fail: + NvOsMutexUnlock(hNand->hMutex); + return e; +} + +void NvDdkNandGetCapabilities( + NvDdkNandHandle hNand, + NvDdkNandDriverCapabilities* pNandDriverCapabilities) +{ + static NvDdkNandDriverCapabilities s_NandCap[2]; + static NvRmModuleCapability s_NandCaps[] = + { + {1, 1, 0, &s_NandCap[0]}, // (Major version, Minor version) = (1,1) for AP15 + {1, 2, 0, &s_NandCap[1]} // (Major version, Minor version) = (1,2) for AP20 + }; + + NvDdkNandDriverCapabilities *pNandCapability = NULL; + NvU32 i = 0; + + NV_ASSERT(hNand); + NV_ASSERT(pNandDriverCapabilities); + NvOsMutexLock(hNand->hMutex); + for (i = 0; i < 2; i++) + { + #if IS_CQ_ENABLED + s_NandCap[i].IsCommandQueueModeSupported = NV_TRUE; + #else + s_NandCap[i].IsCommandQueueModeSupported = NV_FALSE; + #endif + s_NandCap[i].IsEccSupported = NV_TRUE; + s_NandCap[i].IsEdoModeSupported = NV_TRUE; + s_NandCap[i].IsInterleavingSupported = NV_FALSE; + s_NandCap[i].NumberOfDevicesSupported = NDFLASH_CS_MAX; +#if NV_OAL + s_NandCap[i].MaxDataTransferSize = NAND_MAX_BYTES_PER_PAGE; +#else + s_NandCap[i].MaxDataTransferSize = NDFLASH_DMA_MAX_BYTES; +#endif + s_NandCap[i].TagEccParitySize = NDFLASH_PARITY_SZ_HAMMING_SPARE; + s_NandCap[i].ControllerDefaultTiming = TIMING_VALUE; + } + // (Major version, Minor version) = (1,1) for AP15 + s_NandCap[0].IsBCHEccSupported = NV_FALSE; + // (Major version, Minor version) = (1,2) for AP20 + s_NandCap[1].IsBCHEccSupported = NV_TRUE; + s_NandCap[1].NumberOfDevicesSupported = 0x2; + NV_ASSERT_SUCCESS(NvRmModuleGetCapabilities(hNand->RmDevHandle, + NVRM_MODULE_ID(NvRmModuleID_Nand, 0), + s_NandCaps, 2, (void **)&(pNandCapability))); + NvOsMemcpy(pNandDriverCapabilities, pNandCapability, + sizeof(NvDdkNandDriverCapabilities)); + hNand->IsBCHEccSupported = pNandCapability->IsBCHEccSupported; + + NvOsMutexUnlock(hNand->hMutex); +} + +NvU8 GetBitPosition(NvU32 Number) +{ + NvU8 BitPosition = 0; + while(Number) + { + Number >>= 1; + BitPosition++; + } + return BitPosition-1; +} + +void NvDdkNandGetLockedRegions( + NvDdkNandHandle hNand, + LockParams* pFlashLockParams) +{ + NvU32 i; + NvU32 LockApertureMask; + NvU32 LockCtrlReg; + NvU32 LockRegOffset; + + NvOsMutexLock(hNand->hMutex); + LockCtrlReg = Nand_REGR(hNand, LOCK_CONTROL); + LockApertureMask = 1; + hNand->NumberOfAperturesUsed = 0; + for (i = 0; i < NDFLASH_CS_MAX; i++) + { + pFlashLockParams[i].DeviceNumber = 0xFF; + if(LockCtrlReg & LockApertureMask) + { + // Lock aperture enabled...read the aperture cfg + LockRegOffset = + (NAND_LOCK_APER_CHIPID1_0 - NAND_LOCK_APER_CHIPID0_0) * i; + pFlashLockParams[hNand->NumberOfAperturesUsed].StartPageNumber = + Nand_REGR_OFFSET(hNand, LOCK_APER_START0, LockRegOffset); + pFlashLockParams[hNand->NumberOfAperturesUsed].EndPageNumber = + Nand_REGR_OFFSET(hNand, LOCK_APER_END0, LockRegOffset); + pFlashLockParams[hNand->NumberOfAperturesUsed].DeviceNumber = + GetBitPosition(Nand_REGR_OFFSET(hNand, LOCK_APER_CHIPID0, + LockRegOffset)); + hNand->NumberOfAperturesUsed++; + } + LockApertureMask <<= 1; + } + NvOsMutexUnlock(hNand->hMutex); +} + + +void NvDdkNandSetFlashLock(NvDdkNandHandle hNand, LockParams* pFlashLockParams) +{ + NvU32 Offset; + + NV_ASSERT(hNand); + NV_ASSERT(hNand->NumberOfAperturesUsed < NDFLASH_CS_MAX); + + NvOsMutexLock(hNand->hMutex); + if (hNand->NumberOfAperturesUsed < NDFLASH_CS_MAX) + { + Offset = (NAND_LOCK_APER_CHIPID1_0 - NAND_LOCK_APER_CHIPID0_0) * + hNand->NumberOfAperturesUsed; + // Program the startpage/endpage NAND row address into the start/end Lock aperture + // registers + Nand_REGW_OFFSET(hNand, LOCK_APER_START0, Offset, pFlashLockParams->StartPageNumber); + Nand_REGW_OFFSET(hNand, LOCK_APER_END0, Offset, pFlashLockParams->EndPageNumber); + Nand_REGW_OFFSET(hNand, LOCK_APER_CHIPID0, Offset, + (1 << pFlashLockParams->DeviceNumber)); + Nand_REGW(hNand, LOCK_CONTROL, (1 << hNand->NumberOfAperturesUsed)); + + // Store away a copy of the new lock settings so they can be restored should a NAND + // controller reset be necessary (NAND controller reset unlocks all flash). + hNand->LockAperStart[hNand->NumberOfAperturesUsed] = pFlashLockParams->StartPageNumber; + hNand->LockAperEnd[hNand->NumberOfAperturesUsed] = pFlashLockParams->EndPageNumber; + hNand->LockAperChipId[hNand->NumberOfAperturesUsed] = (1 << pFlashLockParams->DeviceNumber); + + hNand->NumberOfAperturesUsed++; + } + NvOsMutexUnlock(hNand->hMutex); +} + +void NvDdkNandReleaseFlashLock(NvDdkNandHandle hNand) +{ + NvU32 i; + NV_ASSERT(hNand); + NvOsMutexLock(hNand->hMutex); + // Issue a H/W reset to the NAND controller to release all Locked regions + NvRmModuleReset(hNand->RmDevHandle, NvRmModuleID_Nand); + // Re-initialize controller timing registers. + SetTimingRegVal(hNand, NV_FALSE); + // Reset NAND lock apertures + hNand->NumberOfAperturesUsed = 0; + for(i = 0; i < NDFLASH_CS_MAX; i++) + { + hNand->LockAperStart[i] = 0; + hNand->LockAperEnd[i] = 0; + hNand->LockAperChipId[i] = 0; + } + NvOsMutexUnlock(hNand->hMutex); +} + +NvError NvDdkNandSuspendClocks(NvDdkNandHandle hNand) +{ + NvError e = NvSuccess; + + NvOsMutexLock(hNand->hMutex); + if (!hNand->IsNandClkEnabled) + { + e = NvSuccess; + goto fail; + } + + /* Disable the clock */ + NV_CHECK_ERROR_CLEANUP(NvRmPowerModuleClockControl(hNand->RmDevHandle, + NvRmModuleID_Nand, hNand->RmPowerClientId, NV_FALSE)); + hNand->IsNandClkEnabled = NV_FALSE; +fail: + NvOsMutexUnlock(hNand->hMutex); + return e; +} + +NvError NvDdkNandResumeClocks(NvDdkNandHandle hNand) +{ + NvError e = NvSuccess; + NvRmDfsBusyHint BusyHints[3]; + NvBool BusyAttribute = NV_TRUE; + + NvOsMutexLock(hNand->hMutex); + if (hNand->IsNandClkEnabled) + { + e = NvSuccess; + goto fail; + } + BusyHints[0].ClockId = NvRmDfsClockId_Emc; + BusyHints[0].BoostDurationMs = 50; + BusyHints[0].BoostKHz = 100000; + BusyHints[0].BusyAttribute = BusyAttribute; + + BusyHints[1].ClockId = NvRmDfsClockId_Ahb; + BusyHints[1].BoostDurationMs = 50; + BusyHints[1].BoostKHz = 100000; + BusyHints[1].BusyAttribute = BusyAttribute; + + BusyHints[2].ClockId = NvRmDfsClockId_Cpu; + BusyHints[2].BoostDurationMs = 50; + BusyHints[2].BoostKHz = 350000; + BusyHints[2].BusyAttribute = BusyAttribute; + + NvRmPowerBusyHintMulti(hNand->RmDevHandle, + hNand->RmPowerClientId, + BusyHints, + 3, + NvRmDfsBusyHintSyncMode_Async); + /* Enable clk to Nand controller */ + NV_CHECK_ERROR_CLEANUP(EnableNandClock(hNand)); + SetTimingRegVal(hNand, NV_FALSE); + hNand->IsNandClkEnabled = NV_TRUE; +fail: + NvOsMutexUnlock(hNand->hMutex); + return e; +} + +NvError NvDdkNandSuspend(NvDdkNandHandle hNand) +{ + NvError e = NvSuccess; + + if (hNand->IsNandSuspended) + { + /* already in suspend state */ + return e; + } + /* disable clock */ + NvDdkNandSuspendClocks(hNand); + NvOsMutexLock(hNand->hMutex); + /* save lock data */ + if (hNand->IsLockStatusAvailable) + NandLoadLockCfg(hNand); + /* disable power */ + NandPowerRailEnable(hNand, NV_FALSE); + NV_CHECK_ERROR_CLEANUP(NvRmPowerVoltageControl(hNand->RmDevHandle, + NvRmModuleID_Nand, hNand->RmPowerClientId, NvRmVoltsOff, NvRmVoltsOff, + NULL, 0, NULL)); + /* enter suspend state */ + hNand->IsNandSuspended = NV_TRUE; +fail: + NvOsMutexUnlock(hNand->hMutex); + return e; +} + +NvError NvDdkNandResume(NvDdkNandHandle hNand) +{ + NvError e = NvSuccess; + + if (!hNand->IsNandSuspended) { + /* already in resume state */ + return e; + } + NvOsMutexLock(hNand->hMutex); + /* Enable power to the Nand controller */ + NV_CHECK_ERROR_CLEANUP(EnableNandPower(hNand)); + /* Restore lock data into Nand registers */ + if (hNand->IsLockStatusAvailable) { + NandRestoreLocks(hNand); + } + NvOsMutexUnlock(hNand->hMutex); + /* enable clock outside mutex lock */ + e = NvDdkNandResumeClocks(hNand); + if (e != NvSuccess) { + /* failed clock enable */ + return e; + } + /* enter resume state */ + hNand->IsNandSuspended = NV_FALSE; + return e; +fail: + NvOsMutexUnlock(hNand->hMutex); + return e; +} + |