Digi Release Code from del-5.6/main2.6.31-digi-201102141643

201 files changed, 3841 insertions, 5818 deletions

diff --git a/arch/alpha/kernel/core_marvel.c b/arch/alpha/kernel/core_marvel.c
index e302daecbe56..8e059e58b0ac 100644
--- a/arch/alpha/kernel/core_marvel.c
+++ b/arch/alpha/kernel/core_marvel.c
@@ -1016,7 +1016,7 @@ marvel_agp_bind_memory(alpha_agp_info *agp, off_t pg_start, struct agp_memory *m
 {
 	struct marvel_agp_aperture *aper = agp->aperture.sysdata;
 	return iommu_bind(aper->arena, aper->pg_start + pg_start, 
-			  mem->page_count, mem->memory);
+			  mem->page_count, mem->pages);
 }
 
 static int 
diff --git a/arch/alpha/kernel/core_titan.c b/arch/alpha/kernel/core_titan.c
index 319fcb74611e..76686497b1e2 100644
--- a/arch/alpha/kernel/core_titan.c
+++ b/arch/alpha/kernel/core_titan.c
@@ -680,7 +680,7 @@ titan_agp_bind_memory(alpha_agp_info *agp, off_t pg_start, struct agp_memory *me
 {
 	struct titan_agp_aperture *aper = agp->aperture.sysdata;
 	return iommu_bind(aper->arena, aper->pg_start + pg_start, 
-			  mem->page_count, mem->memory);
+			  mem->page_count, mem->pages);
 }
 
 static int 
diff --git a/arch/alpha/kernel/pci_impl.h b/arch/alpha/kernel/pci_impl.h
index 00edd04b585e..85457b2d4516 100644
--- a/arch/alpha/kernel/pci_impl.h
+++ b/arch/alpha/kernel/pci_impl.h
@@ -198,7 +198,7 @@ extern unsigned long size_for_memory(unsigned long max);
 
 extern int iommu_reserve(struct pci_iommu_arena *, long, long);
 extern int iommu_release(struct pci_iommu_arena *, long, long);
-extern int iommu_bind(struct pci_iommu_arena *, long, long, unsigned long *);
+extern int iommu_bind(struct pci_iommu_arena *, long, long, struct page **);
 extern int iommu_unbind(struct pci_iommu_arena *, long, long);
 
 
diff --git a/arch/alpha/kernel/pci_iommu.c b/arch/alpha/kernel/pci_iommu.c
index bfb880af959d..eadd63bec4c0 100644
--- a/arch/alpha/kernel/pci_iommu.c
+++ b/arch/alpha/kernel/pci_iommu.c
@@ -880,7 +880,7 @@ iommu_release(struct pci_iommu_arena *arena, long pg_start, long pg_count)
 
 int
 iommu_bind(struct pci_iommu_arena *arena, long pg_start, long pg_count, 
-	   unsigned long *physaddrs)
+	   struct page **pages)
 {
 	unsigned long flags;
 	unsigned long *ptes;
@@ -900,7 +900,7 @@ iommu_bind(struct pci_iommu_arena *arena, long pg_start, long pg_count,
 	}
 		
 	for(i = 0, j = pg_start; i < pg_count; i++, j++)
-		ptes[j] = mk_iommu_pte(physaddrs[i]);
+		ptes[j] = mk_iommu_pte(page_to_phys(pages[i]));
 
 	spin_unlock_irqrestore(&arena->lock, flags);
 
diff --git a/arch/alpha/kernel/vmlinux.lds.S b/arch/alpha/kernel/vmlinux.lds.S
index b9d6568e5f7f..1e0c7121c57d 100644
--- a/arch/alpha/kernel/vmlinux.lds.S
+++ b/arch/alpha/kernel/vmlinux.lds.S
@@ -1,4 +1,5 @@
 #include <asm-generic/vmlinux.lds.h>
+#include <asm/thread_info.h>
 #include <asm/page.h>
 
 OUTPUT_FORMAT("elf64-alpha")
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 7f161d76e5d2..3f1b470beacf 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1502,8 +1502,6 @@ source "drivers/accessibility/Kconfig"
 
 source "drivers/leds/Kconfig"
 
-source "drivers/switch/Kconfig"
-
 source "drivers/rtc/Kconfig"
 
 source "drivers/dma/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 3ca5dd71b3ae..3fe66f3935ed 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -14,7 +14,7 @@ LDFLAGS_vmlinux	:=-p --no-undefined -X
 ifeq ($(CONFIG_CPU_ENDIAN_BE8),y)
 LDFLAGS_vmlinux	+= --be8
 endif
-CPPFLAGS_vmlinux.lds = -DTEXT_OFFSET=$(TEXT_OFFSET)
+
 OBJCOPYFLAGS	:=-O binary -R .note -R .note.gnu.build-id -R .comment -S
 GZFLAGS		:=-9
 #KBUILD_CFLAGS	+=-pipe
diff --git a/arch/arm/configs/imx23evk_updater_defconfig b/arch/arm/configs/imx23evk_updater_defconfig
index f6a430b5bf5f..739e7bd912ec 100644
--- a/arch/arm/configs/imx23evk_updater_defconfig
+++ b/arch/arm/configs/imx23evk_updater_defconfig
@@ -558,7 +558,6 @@ CONFIG_HW_RANDOM=y
 # CONFIG_I2C is not set
 # CONFIG_I2C_SLAVE is not set
 # CONFIG_SPI is not set
-CONFIG_FSL_OTP=y
 CONFIG_ARCH_REQUIRE_GPIOLIB=y
 CONFIG_GPIOLIB=y
 # CONFIG_GPIO_SYSFS is not set
diff --git a/arch/arm/configs/imx28evk_defconfig b/arch/arm/configs/imx28evk_defconfig
index 9d3b1c98d198..40c35b60a811 100644
--- a/arch/arm/configs/imx28evk_defconfig
+++ b/arch/arm/configs/imx28evk_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
 # Linux kernel version: 2.6.31
-# Tue Aug  3 11:34:57 2010
+# Tue Jun  8 11:22:27 2010
 #
 CONFIG_ARM=y
 CONFIG_SYS_SUPPORTS_APM_EMULATION=y
@@ -851,7 +851,6 @@ CONFIG_MXS_VIIM=y
 #
 CONFIG_SERIAL_MXS_DUART=y
 CONFIG_SERIAL_MXS_AUART=y
-# CONFIG_SERIAL_MXS_AUART_CONSOLE is not set
 CONFIG_SERIAL_MXS_DUART_CONSOLE=y
 CONFIG_SERIAL_CORE=y
 CONFIG_SERIAL_CORE_CONSOLE=y
@@ -1256,18 +1255,16 @@ CONFIG_USB_ARCH_HAS_HCD=y
 CONFIG_USB_ARCH_HAS_EHCI=y
 CONFIG_USB=y
 # CONFIG_USB_DEBUG is not set
-# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
 
 #
 # Miscellaneous USB options
 #
 # CONFIG_USB_DEVICEFS is not set
 # CONFIG_USB_DEVICE_CLASS is not set
-# CONFIG_USB_DYNAMIC_MINORS is not set
-CONFIG_USB_SUSPEND=y
-CONFIG_USB_OTG=y
-# CONFIG_USB_OTG_WHITELIST is not set
-# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+CONFIG_USB_DYNAMIC_MINORS=y
+# CONFIG_USB_SUSPEND is not set
+# CONFIG_USB_OTG is not set
 # CONFIG_USB_MON is not set
 # CONFIG_USB_WUSB is not set
 # CONFIG_USB_WUSB_CBAF is not set
@@ -1276,15 +1273,11 @@ CONFIG_USB_OTG=y
 # USB Host Controller Drivers
 #
 # CONFIG_USB_C67X00_HCD is not set
-CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_HCD=m
 CONFIG_USB_EHCI_ARC=y
 CONFIG_USB_EHCI_ARC_H1=y
-CONFIG_USB_EHCI_ARC_OTG=y
+# CONFIG_USB_EHCI_ARC_OTG is not set
 # CONFIG_USB_STATIC_IRAM is not set
-# CONFIG_USB_EHCI_FSL_MC13783 is not set
-# CONFIG_USB_EHCI_FSL_1301 is not set
-# CONFIG_USB_EHCI_FSL_1504 is not set
-CONFIG_USB_EHCI_FSL_UTMI=y
 CONFIG_USB_EHCI_ROOT_HUB_TT=y
 # CONFIG_USB_EHCI_TT_NEWSCHED is not set
 # CONFIG_USB_OXU210HP_HCD is not set
@@ -1361,7 +1354,7 @@ CONFIG_USB_STORAGE=y
 # CONFIG_USB_TEST is not set
 # CONFIG_USB_ISIGHTFW is not set
 # CONFIG_USB_VST is not set
-CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET=m
 # CONFIG_USB_GADGET_DEBUG_FILES is not set
 # CONFIG_USB_GADGET_DEBUG_FS is not set
 CONFIG_USB_GADGET_VBUS_DRAW=2
@@ -1383,7 +1376,7 @@ CONFIG_USB_GADGET_SELECTED=y
 # CONFIG_USB_GADGET_NET2280 is not set
 # CONFIG_USB_GADGET_GOKU is not set
 CONFIG_USB_GADGET_ARC=y
-CONFIG_USB_ARC=y
+CONFIG_USB_ARC=m
 CONFIG_WORKAROUND_ARCUSB_REG_RW=y
 # CONFIG_USB_GADGET_LANGWELL is not set
 # CONFIG_USB_GADGET_DUMMY_HCD is not set
@@ -1407,7 +1400,7 @@ CONFIG_USB_G_SERIAL=m
 CONFIG_USB_OTG_UTILS=y
 # CONFIG_USB_GPIO_VBUS is not set
 # CONFIG_NOP_USB_XCEIV is not set
-CONFIG_MXC_OTG=y
+# CONFIG_MXC_OTG is not set
 CONFIG_MMC=y
 # CONFIG_MMC_DEBUG is not set
 CONFIG_MMC_UNSAFE_RESUME=y
@@ -1506,7 +1499,6 @@ CONFIG_DMADEVICES=y
 #
 # DMA Devices
 #
-# CONFIG_MXC_PXP is not set
 # CONFIG_AUXDISPLAY is not set
 CONFIG_REGULATOR=y
 # CONFIG_REGULATOR_DEBUG is not set
@@ -1517,7 +1509,6 @@ CONFIG_REGULATOR=y
 # CONFIG_REGULATOR_MAX1586 is not set
 # CONFIG_REGULATOR_LP3971 is not set
 CONFIG_REGULATOR_MXS=y
-# CONFIG_REGULATOR_MAX17135 is not set
 # CONFIG_UIO is not set
 # CONFIG_STAGING is not set
 
diff --git a/arch/arm/configs/imx28evk_updater_defconfig b/arch/arm/configs/imx28evk_updater_defconfig
index fe9a908e7e62..21223ed3f678 100644
--- a/arch/arm/configs/imx28evk_updater_defconfig
+++ b/arch/arm/configs/imx28evk_updater_defconfig
@@ -531,7 +531,6 @@ CONFIG_SERIAL_CORE_CONSOLE=y
 # CONFIG_I2C is not set
 # CONFIG_I2C_SLAVE is not set
 # CONFIG_SPI is not set
-CONFIG_FSL_OTP=y
 CONFIG_ARCH_REQUIRE_GPIOLIB=y
 CONFIG_GPIOLIB=y
 # CONFIG_GPIO_SYSFS is not set
diff --git a/arch/arm/configs/imx5_defconfig b/arch/arm/configs/imx5_defconfig
index 47cf51acaa53..8336690d1bf4 100644
--- a/arch/arm/configs/imx5_defconfig
+++ b/arch/arm/configs/imx5_defconfig
@@ -204,8 +204,6 @@ CONFIG_MACH_MX51_3DS=y
 CONFIG_MACH_MX51_BABBAGE=y
 CONFIG_MACH_MX53_EVK=y
 CONFIG_MACH_MX50_ARM2=y
-CONFIG_MACH_MX50_RDP=y
-CONFIG_ARCH_MXC_IOMUX_V3=y
 
 #
 # MX5x Options:
@@ -489,7 +487,7 @@ CONFIG_CONNECTOR=y
 CONFIG_PROC_EVENTS=y
 CONFIG_MTD=y
 # CONFIG_MTD_DEBUG is not set
-CONFIG_MTD_CONCAT=y
+# CONFIG_MTD_CONCAT is not set
 CONFIG_MTD_PARTITIONS=y
 # CONFIG_MTD_TESTS is not set
 # CONFIG_MTD_REDBOOT_PARTS is not set
@@ -827,7 +825,6 @@ CONFIG_DEVKMEM=y
 # CONFIG_SERIAL_NONSTANDARD is not set
 CONFIG_FM_SI4702=m
 CONFIG_MXC_IIM=y
-CONFIG_MXS_VIIM=y
 CONFIG_IMX_SIM=m
 
 #
@@ -1310,7 +1307,6 @@ CONFIG_FB_MXC_EPSON_VGA_SYNC_PANEL=y
 CONFIG_FB_MXC_TVOUT_TVE=y
 CONFIG_FB_MXC_LDB=y
 # CONFIG_FB_MXC_CLAA_WVGA_SYNC_PANEL is not set
-CONFIG_FB_MXC_SII9022=y
 CONFIG_FB_MXC_CH7026=y
 # CONFIG_FB_MXC_TVOUT_CH7024 is not set
 # CONFIG_FB_MXC_ASYNC_PANEL is not set
@@ -2065,8 +2061,8 @@ CONFIG_CRYPTO=y
 # CONFIG_CRYPTO_NULL is not set
 # CONFIG_CRYPTO_CRYPTD is not set
 # CONFIG_CRYPTO_AUTHENC is not set
-CONFIG_CRYPTO_TEST=m
-CONFIG_CRYPTO_CRYPTODEV=y
+# CONFIG_CRYPTO_TEST is not set
+# CONFIG_CRYPTO_CRYPTODEV is not set
 
 #
 # Authenticated Encryption with Associated Data
@@ -2078,10 +2074,10 @@ CONFIG_CRYPTO_CRYPTODEV=y
 #
 # Block modes
 #
-CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CBC is not set
 # CONFIG_CRYPTO_CTR is not set
 # CONFIG_CRYPTO_CTS is not set
-CONFIG_CRYPTO_ECB=y
+# CONFIG_CRYPTO_ECB is not set
 # CONFIG_CRYPTO_LRW is not set
 # CONFIG_CRYPTO_PCBC is not set
 # CONFIG_CRYPTO_XTS is not set
@@ -2112,7 +2108,7 @@ CONFIG_CRYPTO_ECB=y
 #
 # Ciphers
 #
-CONFIG_CRYPTO_AES=y
+# CONFIG_CRYPTO_AES is not set
 # CONFIG_CRYPTO_ANUBIS is not set
 # CONFIG_CRYPTO_ARC4 is not set
 # CONFIG_CRYPTO_BLOWFISH is not set
diff --git a/arch/arm/configs/imx5_updater_defconfig b/arch/arm/configs/imx5_updater_defconfig
index f594185b5e0a..801eca586a13 100644
--- a/arch/arm/configs/imx5_updater_defconfig
+++ b/arch/arm/configs/imx5_updater_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
 # Linux kernel version: 2.6.31
-# Tue Jul 27 15:14:58 2010
+# Wed Jun 23 17:31:28 2010
 #
 CONFIG_ARM=y
 CONFIG_HAVE_PWM=y
@@ -192,13 +192,11 @@ CONFIG_FORCE_MAX_ZONEORDER=13
 CONFIG_ARCH_MXC_HAS_NFC_V3=y
 CONFIG_ARCH_MX51=y
 CONFIG_ARCH_MX53=y
-CONFIG_ARCH_MX50=y
 CONFIG_MX5_OPTIONS=y
 CONFIG_MX5_MULTI_ARCH=y
 CONFIG_MACH_MX51_3DS=y
 CONFIG_MACH_MX51_BABBAGE=y
 CONFIG_MACH_MX53_EVK=y
-CONFIG_MACH_MX50_ARM2=y
 
 #
 # MX5x Options:
@@ -208,8 +206,7 @@ CONFIG_MXC_TZIC=y
 CONFIG_ISP1504_MXC=y
 # CONFIG_MXC_IRQ_PRIOR is not set
 CONFIG_MXC_PWM=y
-CONFIG_ARCH_MXC_IOMUX_V3=y
-CONFIG_MXC_DVFS_PER=y
+# CONFIG_MXC_DVFS_PER is not set
 
 #
 # Processor Type
@@ -303,16 +300,16 @@ CONFIG_CPU_FREQ_TABLE=y
 # CONFIG_CPU_FREQ_DEBUG is not set
 CONFIG_CPU_FREQ_STAT=y
 # CONFIG_CPU_FREQ_STAT_DETAILS is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
 # CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
-CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
 # CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
 # CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
 CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
+# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
 # CONFIG_CPU_FREQ_GOV_ONDEMAND is not set
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
 CONFIG_CPU_FREQ_IMX=y
 # CONFIG_CPU_IDLE is not set
 
@@ -525,7 +522,14 @@ CONFIG_SCSI_LOWLEVEL=y
 # CONFIG_SCSI_DEBUG is not set
 # CONFIG_SCSI_DH is not set
 # CONFIG_SCSI_OSD_INITIATOR is not set
-# CONFIG_ATA is not set
+CONFIG_ATA=y
+# CONFIG_ATA_NONSTANDARD is not set
+# CONFIG_SATA_PMP is not set
+# CONFIG_SATA_AHCI_PLATFORM is not set
+CONFIG_ATA_SFF=y
+# CONFIG_SATA_MV is not set
+# CONFIG_PATA_PLATFORM is not set
+CONFIG_PATA_FSL=y
 # CONFIG_MD is not set
 
 #
@@ -636,7 +640,6 @@ CONFIG_LEGACY_PTYS=y
 CONFIG_LEGACY_PTY_COUNT=256
 # CONFIG_IPMI_HANDLER is not set
 CONFIG_HW_RANDOM=y
-CONFIG_FSL_OTP=y
 # CONFIG_HW_RANDOM_TIMERIOMEM is not set
 # CONFIG_R3964 is not set
 # CONFIG_RAW_DRIVER is not set
@@ -830,7 +833,7 @@ CONFIG_WATCHDOG_NOWAYOUT=y
 #
 # Watchdog Device Drivers
 #
-CONFIG_SOFT_WATCHDOG=y
+# CONFIG_SOFT_WATCHDOG is not set
 CONFIG_MXC_WATCHDOG=y
 
 #
@@ -867,12 +870,196 @@ CONFIG_MEDIA_SUPPORT=y
 #
 # Multimedia core support
 #
-# CONFIG_VIDEO_DEV is not set
-# CONFIG_VIDEO_MEDIA is not set
+CONFIG_VIDEO_DEV=y
+CONFIG_VIDEO_V4L2_COMMON=y
+CONFIG_VIDEO_ALLOW_V4L1=y
+CONFIG_VIDEO_V4L1_COMPAT=y
+CONFIG_VIDEO_MEDIA=y
 
 #
 # Multimedia drivers
 #
+CONFIG_MEDIA_TUNER=y
+CONFIG_MEDIA_TUNER_CUSTOMISE=y
+# CONFIG_MEDIA_TUNER_SIMPLE is not set
+# CONFIG_MEDIA_TUNER_TDA8290 is not set
+# CONFIG_MEDIA_TUNER_TDA827X is not set
+# CONFIG_MEDIA_TUNER_TDA18271 is not set
+# CONFIG_MEDIA_TUNER_TDA9887 is not set
+# CONFIG_MEDIA_TUNER_TEA5761 is not set
+# CONFIG_MEDIA_TUNER_TEA5767 is not set
+# CONFIG_MEDIA_TUNER_MT20XX is not set
+# CONFIG_MEDIA_TUNER_MT2060 is not set
+# CONFIG_MEDIA_TUNER_MT2266 is not set
+# CONFIG_MEDIA_TUNER_MT2131 is not set
+# CONFIG_MEDIA_TUNER_QT1010 is not set
+# CONFIG_MEDIA_TUNER_XC2028 is not set
+# CONFIG_MEDIA_TUNER_XC5000 is not set
+# CONFIG_MEDIA_TUNER_MXL5005S is not set
+# CONFIG_MEDIA_TUNER_MXL5007T is not set
+# CONFIG_MEDIA_TUNER_MC44S803 is not set
+CONFIG_VIDEO_V4L2=y
+CONFIG_VIDEO_V4L1=y
+CONFIG_VIDEO_CAPTURE_DRIVERS=y
+# CONFIG_VIDEO_ADV_DEBUG is not set
+# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
+# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set
+
+#
+# Encoders/decoders and other helper chips
+#
+
+#
+# Audio decoders
+#
+# CONFIG_VIDEO_TVAUDIO is not set
+# CONFIG_VIDEO_TDA7432 is not set
+# CONFIG_VIDEO_TDA9840 is not set
+# CONFIG_VIDEO_TDA9875 is not set
+# CONFIG_VIDEO_TEA6415C is not set
+# CONFIG_VIDEO_TEA6420 is not set
+# CONFIG_VIDEO_MSP3400 is not set
+# CONFIG_VIDEO_CS5345 is not set
+# CONFIG_VIDEO_CS53L32A is not set
+# CONFIG_VIDEO_M52790 is not set
+# CONFIG_VIDEO_TLV320AIC23B is not set
+# CONFIG_VIDEO_WM8775 is not set
+# CONFIG_VIDEO_WM8739 is not set
+# CONFIG_VIDEO_VP27SMPX is not set
+
+#
+# RDS decoders
+#
+# CONFIG_VIDEO_SAA6588 is not set
+
+#
+# Video decoders
+#
+# CONFIG_VIDEO_BT819 is not set
+# CONFIG_VIDEO_BT856 is not set
+# CONFIG_VIDEO_BT866 is not set
+# CONFIG_VIDEO_KS0127 is not set
+# CONFIG_VIDEO_OV7670 is not set
+# CONFIG_VIDEO_MT9V011 is not set
+# CONFIG_VIDEO_TCM825X is not set
+# CONFIG_VIDEO_SAA7110 is not set
+# CONFIG_VIDEO_SAA711X is not set
+# CONFIG_VIDEO_SAA717X is not set
+# CONFIG_VIDEO_SAA7191 is not set
+# CONFIG_VIDEO_TVP514X is not set
+# CONFIG_VIDEO_TVP5150 is not set
+# CONFIG_VIDEO_VPX3220 is not set
+
+#
+# Video and audio decoders
+#
+# CONFIG_VIDEO_CX25840 is not set
+
+#
+# MPEG video encoders
+#
+# CONFIG_VIDEO_CX2341X is not set
+
+#
+# Video encoders
+#
+# CONFIG_VIDEO_SAA7127 is not set
+# CONFIG_VIDEO_SAA7185 is not set
+# CONFIG_VIDEO_ADV7170 is not set
+# CONFIG_VIDEO_ADV7175 is not set
+# CONFIG_VIDEO_THS7303 is not set
+# CONFIG_VIDEO_ADV7343 is not set
+
+#
+# Video improvement chips
+#
+# CONFIG_VIDEO_UPD64031A is not set
+# CONFIG_VIDEO_UPD64083 is not set
+# CONFIG_VIDEO_VIVI is not set
+CONFIG_VIDEO_MXC_CAMERA=y
+
+#
+# MXC Camera/V4L2 PRP Features support
+#
+CONFIG_VIDEO_MXC_IPU_CAMERA=y
+# CONFIG_VIDEO_MXC_CSI_CAMERA is not set
+# CONFIG_MXC_CAMERA_MC521DA is not set
+# CONFIG_MXC_EMMA_CAMERA_MICRON111 is not set
+# CONFIG_MXC_CAMERA_OV2640_EMMA is not set
+# CONFIG_MXC_CAMERA_MICRON111 is not set
+# CONFIG_MXC_CAMERA_OV2640 is not set
+CONFIG_MXC_CAMERA_OV3640=y
+# CONFIG_MXC_TVIN_ADV7180 is not set
+CONFIG_MXC_IPU_PRP_VF_SDC=y
+CONFIG_MXC_IPU_PRP_ENC=y
+CONFIG_MXC_IPU_CSI_ENC=y
+CONFIG_VIDEO_MXC_OUTPUT=y
+CONFIG_VIDEO_MXC_IPU_OUTPUT=y
+# CONFIG_VIDEO_MXC_IPUV1_WVGA_OUTPUT is not set
+# CONFIG_VIDEO_MXC_OPL is not set
+# CONFIG_VIDEO_CPIA is not set
+# CONFIG_VIDEO_CPIA2 is not set
+# CONFIG_VIDEO_SAA5246A is not set
+# CONFIG_VIDEO_SAA5249 is not set
+# CONFIG_SOC_CAMERA is not set
+CONFIG_V4L_USB_DRIVERS=y
+CONFIG_USB_VIDEO_CLASS=y
+CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
+CONFIG_USB_GSPCA=y
+# CONFIG_USB_M5602 is not set
+# CONFIG_USB_STV06XX is not set
+# CONFIG_USB_GSPCA_CONEX is not set
+# CONFIG_USB_GSPCA_ETOMS is not set
+# CONFIG_USB_GSPCA_FINEPIX is not set
+# CONFIG_USB_GSPCA_MARS is not set
+# CONFIG_USB_GSPCA_MR97310A is not set
+# CONFIG_USB_GSPCA_OV519 is not set
+# CONFIG_USB_GSPCA_OV534 is not set
+# CONFIG_USB_GSPCA_PAC207 is not set
+# CONFIG_USB_GSPCA_PAC7311 is not set
+# CONFIG_USB_GSPCA_SN9C20X is not set
+# CONFIG_USB_GSPCA_SONIXB is not set
+# CONFIG_USB_GSPCA_SONIXJ is not set
+# CONFIG_USB_GSPCA_SPCA500 is not set
+# CONFIG_USB_GSPCA_SPCA501 is not set
+# CONFIG_USB_GSPCA_SPCA505 is not set
+# CONFIG_USB_GSPCA_SPCA506 is not set
+# CONFIG_USB_GSPCA_SPCA508 is not set
+# CONFIG_USB_GSPCA_SPCA561 is not set
+# CONFIG_USB_GSPCA_SQ905 is not set
+# CONFIG_USB_GSPCA_SQ905C is not set
+# CONFIG_USB_GSPCA_STK014 is not set
+# CONFIG_USB_GSPCA_SUNPLUS is not set
+# CONFIG_USB_GSPCA_T613 is not set
+# CONFIG_USB_GSPCA_TV8532 is not set
+# CONFIG_USB_GSPCA_VC032X is not set
+# CONFIG_USB_GSPCA_ZC3XX is not set
+# CONFIG_VIDEO_PVRUSB2 is not set
+# CONFIG_VIDEO_HDPVR is not set
+# CONFIG_VIDEO_EM28XX is not set
+# CONFIG_VIDEO_CX231XX is not set
+# CONFIG_VIDEO_USBVISION is not set
+# CONFIG_USB_VICAM is not set
+# CONFIG_USB_IBMCAM is not set
+# CONFIG_USB_KONICAWC is not set
+# CONFIG_USB_QUICKCAM_MESSENGER is not set
+# CONFIG_USB_ET61X251 is not set
+# CONFIG_VIDEO_OVCAMCHIP is not set
+# CONFIG_USB_OV511 is not set
+# CONFIG_USB_SE401 is not set
+# CONFIG_USB_SN9C102 is not set
+# CONFIG_USB_STV680 is not set
+# CONFIG_USB_ZC0301 is not set
+# CONFIG_USB_PWC is not set
+CONFIG_USB_PWC_INPUT_EVDEV=y
+# CONFIG_USB_ZR364XX is not set
+# CONFIG_USB_STKWEBCAM is not set
+# CONFIG_USB_S2255 is not set
+CONFIG_RADIO_ADAPTERS=y
+# CONFIG_USB_DSBR is not set
+# CONFIG_USB_SI470X is not set
+# CONFIG_USB_MR800 is not set
+# CONFIG_RADIO_TEA5764 is not set
 # CONFIG_DAB is not set
 
 #
@@ -904,15 +1091,13 @@ CONFIG_FB_MODE_HELPERS=y
 #
 CONFIG_FB_MXC=y
 CONFIG_FB_MXC_SYNC_PANEL=y
-# CONFIG_FB_MXC_EPSON_VGA_SYNC_PANEL is not set
-# CONFIG_FB_MXC_TVOUT_TVE is not set
-# CONFIG_FB_MXC_LDB is not set
+CONFIG_FB_MXC_EPSON_VGA_SYNC_PANEL=y
+CONFIG_FB_MXC_TVOUT_TVE=y
+CONFIG_FB_MXC_LDB=y
 # CONFIG_FB_MXC_CLAA_WVGA_SYNC_PANEL is not set
-# CONFIG_FB_MXC_CH7026 is not set
+CONFIG_FB_MXC_CH7026=y
 # CONFIG_FB_MXC_TVOUT_CH7024 is not set
 # CONFIG_FB_MXC_ASYNC_PANEL is not set
-# CONFIG_FB_MXC_EINK_PANEL is not set
-# CONFIG_FB_MXC_ELCDIF_FB is not set
 # CONFIG_FB_S1D13XXX is not set
 # CONFIG_FB_VIRTUAL is not set
 # CONFIG_FB_METRONOME is not set
@@ -954,7 +1139,52 @@ CONFIG_LOGO=y
 # CONFIG_LOGO_LINUX_MONO is not set
 # CONFIG_LOGO_LINUX_VGA16 is not set
 CONFIG_LOGO_LINUX_CLUT224=y
-# CONFIG_SOUND is not set
+CONFIG_SOUND=y
+CONFIG_SOUND_OSS_CORE=y
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+CONFIG_SND_JACK=y
+# CONFIG_SND_SEQUENCER is not set
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_MIXER_OSS=y
+CONFIG_SND_PCM_OSS=y
+CONFIG_SND_PCM_OSS_PLUGINS=y
+# CONFIG_SND_HRTIMER is not set
+# CONFIG_SND_DYNAMIC_MINORS is not set
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+# CONFIG_SND_RAWMIDI_SEQ is not set
+# CONFIG_SND_OPL3_LIB_SEQ is not set
+# CONFIG_SND_OPL4_LIB_SEQ is not set
+# CONFIG_SND_SBAWE_SEQ is not set
+# CONFIG_SND_EMU10K1_SEQ is not set
+CONFIG_SND_DRIVERS=y
+# CONFIG_SND_DUMMY is not set
+# CONFIG_SND_MTPAV is not set
+# CONFIG_SND_SERIAL_U16550 is not set
+# CONFIG_SND_MPU401 is not set
+CONFIG_SND_ARM=y
+CONFIG_SND_MXC_SPDIF=y
+CONFIG_SND_SPI=y
+CONFIG_SND_USB=y
+# CONFIG_SND_USB_AUDIO is not set
+# CONFIG_SND_USB_CAIAQ is not set
+CONFIG_SND_SOC=y
+CONFIG_SND_MXC_SOC=y
+CONFIG_SND_MXC_SOC_SSI=y
+CONFIG_SND_MXC_SOC_IRAM=y
+CONFIG_SND_SOC_IMX_3STACK_SGTL5000=y
+# CONFIG_SND_SOC_IMX_3STACK_AK4647 is not set
+# CONFIG_SND_SOC_IMX_3STACK_WM8580 is not set
+# CONFIG_SND_SOC_IMX_3STACK_AK5702 is not set
+# CONFIG_SND_SOC_IMX_3STACK_BLUETOOTH is not set
+CONFIG_SND_SOC_I2C_AND_SPI=y
+# CONFIG_SND_SOC_ALL_CODECS is not set
+CONFIG_SND_SOC_SGTL5000=y
+# CONFIG_SOUND_PRIME is not set
 CONFIG_HID_SUPPORT=y
 CONFIG_HID=y
 # CONFIG_HID_DEBUG is not set
@@ -1255,20 +1485,7 @@ CONFIG_RTC_INTF_DEV_UIE_EMUL=y
 # CONFIG_RTC_DRV_MXC_V2 is not set
 # CONFIG_RTC_DRV_IMXDI is not set
 CONFIG_RTC_MC13892=y
-CONFIG_DMADEVICES=y
-
-#
-# DMA Devices
-#
-CONFIG_MXC_PXP=y
-CONFIG_MXC_PXP_CLIENT_DEVICE=y
-CONFIG_DMA_ENGINE=y
-
-#
-# DMA Clients
-#
-# CONFIG_ASYNC_TX_DMA is not set
-# CONFIG_DMATEST is not set
+# CONFIG_DMADEVICES is not set
 # CONFIG_AUXDISPLAY is not set
 CONFIG_REGULATOR=y
 # CONFIG_REGULATOR_DEBUG is not set
@@ -1279,7 +1496,6 @@ CONFIG_REGULATOR=y
 # CONFIG_REGULATOR_MAX1586 is not set
 # CONFIG_REGULATOR_LP3971 is not set
 CONFIG_REGULATOR_MC13892=y
-CONFIG_REGULATOR_MAX17135=y
 CONFIG_UIO=y
 # CONFIG_UIO_PDRV is not set
 CONFIG_UIO_PDRV_GENIRQ=y
@@ -1351,8 +1567,9 @@ CONFIG_MXC_MC13892_POWER=y
 #
 # MXC VPU(Video Processing Unit) support
 #
-# CONFIG_MXC_VPU is not set
-# CONFIG_MXC_VPU_IRAM is not set
+CONFIG_MXC_VPU=y
+CONFIG_MXC_VPU_IRAM=y
+# CONFIG_MXC_VPU_DEBUG is not set
 
 #
 # MXC Asynchronous Sample Rate Converter support
@@ -1379,11 +1596,6 @@ CONFIG_MXC_MLB=y
 # CONFIG_IMX_ADC is not set
 
 #
-# MXC GPU support
-#
-# CONFIG_MXC_AMD_GPU is not set
-
-#
 # File systems
 #
 CONFIG_EXT2_FS=y
@@ -1553,8 +1765,8 @@ CONFIG_NLS_UTF8=y
 # Kernel hacking
 #
 # CONFIG_PRINTK_TIME is not set
-# CONFIG_ENABLE_WARN_DEPRECATED is not set
-# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
 CONFIG_FRAME_WARN=1024
 # CONFIG_MAGIC_SYSRQ is not set
 # CONFIG_UNUSED_SYMBOLS is not set
@@ -1565,16 +1777,15 @@ CONFIG_FRAME_WARN=1024
 # CONFIG_SLUB_STATS is not set
 # CONFIG_DEBUG_BUGVERBOSE is not set
 # CONFIG_DEBUG_MEMORY_INIT is not set
-CONFIG_FRAME_POINTER=y
 # CONFIG_RCU_CPU_STALL_DETECTOR is not set
 # CONFIG_LATENCYTOP is not set
-# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+CONFIG_SYSCTL_SYSCALL_CHECK=y
 CONFIG_HAVE_FUNCTION_TRACER=y
 CONFIG_TRACING_SUPPORT=y
 # CONFIG_FTRACE is not set
 # CONFIG_SAMPLES is not set
 CONFIG_HAVE_ARCH_KGDB=y
-# CONFIG_ARM_UNWIND is not set
+CONFIG_ARM_UNWIND=y
 # CONFIG_DEBUG_USER is not set
 
 #
diff --git a/arch/arm/include/asm/kmap_types.h b/arch/arm/include/asm/kmap_types.h
index d16ec97ec9a9..c019949a5189 100644
--- a/arch/arm/include/asm/kmap_types.h
+++ b/arch/arm/include/asm/kmap_types.h
@@ -22,4 +22,10 @@ enum km_type {
 	KM_TYPE_NR
 };
 
+#ifdef CONFIG_DEBUG_HIGHMEM
+#define KM_NMI		(-1)
+#define KM_NMI_PTE	(-1)
+#define KM_IRQ_PTE	(-1)
+#endif
+
 #endif
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index ff89d0b3abc5..60be28ddc813 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -2,7 +2,8 @@
 # Makefile for the linux kernel.
 #
 
-AFLAGS_head.o := -DTEXT_OFFSET=$(TEXT_OFFSET)
+CPPFLAGS_vmlinux.lds := -DTEXT_OFFSET=$(TEXT_OFFSET)
+AFLAGS_head.o        := -DTEXT_OFFSET=$(TEXT_OFFSET)
 
 ifdef CONFIG_DYNAMIC_FTRACE
 CFLAGS_REMOVE_ftrace.o = -pg
diff --git a/arch/arm/mach-mx23/device.c b/arch/arm/mach-mx23/device.c
index cda2285ec3bc..814c4ef59266 100644
--- a/arch/arm/mach-mx23/device.c
+++ b/arch/arm/mach-mx23/device.c
@@ -931,49 +931,6 @@ static void mx23_init_persistent()
 }
 #endif
 
-#if defined(CONFIG_FSL_OTP)
-/* Building up eight registers's names of a bank */
-#define BANK(a, b, c, d, e, f, g, h)	\
-	{\
-	("HW_OCOTP_"#a), ("HW_OCOTP_"#b), ("HW_OCOTP_"#c), ("HW_OCOTP_"#d), \
-	("HW_OCOTP_"#e), ("HW_OCOTP_"#f), ("HW_OCOTP_"#g), ("HW_OCOTP_"#h) \
-	}
-
-#define BANKS		(4)
-#define BANK_ITEMS	(8)
-static const char *bank_reg_desc[BANKS][BANK_ITEMS] = {
-	BANK(CUST0, CUST1, CUST2, CUST3, CRYPTO0, CRYPTO1, CRYPTO2, CRYPTO3),
-	BANK(HWCAP0, HWCAP1, HWCAP2, HWCAP3, HWCAP4, HWCAP5, SWCAP, CUSTCAP),
-	BANK(LOCK, OPS0, OPS1, OPS2, OPS3, UN0, UN1, UN2),
-	BANK(ROM0, ROM1, ROM2, ROM3, ROM4, ROM5, ROM6, ROM7),
-};
-
-static struct fsl_otp_data otp_data = {
-	.fuse_name	= (char **)bank_reg_desc,
-	.regulator_name	= "vddio",
-	.fuse_num	= BANKS * BANK_ITEMS,
-};
-#undef BANK
-#undef BANKS
-#undef BANK_ITEMS
-
-static void mx23_init_otp(void)
-{
-	struct platform_device *pdev;
-	pdev = mxs_get_device("ocotp", 0);
-	if (pdev == NULL || IS_ERR(pdev))
-		return;
-	pdev->dev.platform_data = &otp_data;
-	pdev->resource = NULL;
-	pdev->num_resources = 0;
-	mxs_add_device(pdev, 3);
-}
-#else
-static void mx23_init_otp(void)
-{
-}
-#endif
-
 int __init mx23_device_init(void)
 {
 	mx23_init_dma();
@@ -994,7 +951,6 @@ int __init mx23_device_init(void)
 	mx23_init_pxp();
 	mx23_init_battery();
 	mx23_init_persistent();
-	mx23_init_otp();
 
 	return 0;
 }
diff --git a/arch/arm/mach-mx23/mx23evk_pins.c b/arch/arm/mach-mx23/mx23evk_pins.c
index cdf86cfbea63..c12235d75e8c 100644
--- a/arch/arm/mach-mx23/mx23evk_pins.c
+++ b/arch/arm/mach-mx23/mx23evk_pins.c
@@ -61,28 +61,6 @@ static struct pin_desc mx23evk_fixed_pins[] = {
 	 },
 #endif
 
-#ifdef CONFIG_MXS_AUART2_DEVICE_ENABLE
-	{
-	 .name  = "AUART2.RX",
-	 .id    = PINID_GPMI_D14,
-	 .fun   = PIN_FUN2,
-	},
-	{
-	 .name  = "AUART2.TX",
-	 .id    = PINID_GPMI_D15,
-	 .fun   = PIN_FUN2,
-	},
-	{
-	 .name  = "AUART2.CTS",
-	 .id    = PINID_ROTARYB,
-	 .fun   = PIN_FUN2,
-	},
-	{
-	 .name  = "AUART2.RTS",
-	 .id    = PINID_ROTARYA,
-	 .fun   = PIN_FUN2,
-	},
-#endif
 #if defined(CONFIG_I2C_MXS) || \
 	defined(CONFIG_I2C_MXS_MODULE)
 	{
diff --git a/arch/arm/mach-mx23/usb_dr.c b/arch/arm/mach-mx23/usb_dr.c
index 4c702ffcd07c..ed4bde71391c 100644
--- a/arch/arm/mach-mx23/usb_dr.c
+++ b/arch/arm/mach-mx23/usb_dr.c
@@ -64,7 +64,7 @@ static struct fsl_usb2_platform_data __maybe_unused dr_utmi_config = {
 };
 
 /*
- * OTG resources
+ * resources
  */
 static struct resource otg_resources[] = {
 	[0] = {
@@ -84,28 +84,6 @@ static struct resource otg_resources[] = {
 	},
 };
 
-/*
- * UDC resources (same as OTG resource)
- */
-static struct resource udc_resources[] = {
-	[0] = {
-		.start	= (u32)USBCTRL_PHYS_ADDR,
-		.end	= (u32)(USBCTRL_PHYS_ADDR + 0x1ff),
-		.flags	= IORESOURCE_MEM,
-	},
-
-	[1] = {
-		.start	= IRQ_USB_CTRL,
-		.flags	= IORESOURCE_IRQ,
-	},
-
-	[2] = {
-		.start = IRQ_USB_WAKEUP,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-
 static u64 dr_udc_dmamask = ~(u32) 0;
 static void dr_udc_release(struct device *dev)
 {
@@ -123,8 +101,8 @@ static struct platform_device dr_udc_device = {
 		.dma_mask          = &dr_udc_dmamask,
 		.coherent_dma_mask = 0xffffffff,
 	},
-	.resource      = udc_resources,
-	.num_resources = ARRAY_SIZE(udc_resources),
+	.resource      = otg_resources,
+	.num_resources = ARRAY_SIZE(otg_resources),
 };
 
 static u64 dr_otg_dmamask = ~(u32) 0;
@@ -189,5 +167,5 @@ void fsl_phy_set_power(struct fsl_xcvr_ops *this,
 #ifdef CONFIG_MXS_VBUS_CURRENT_DRAW
 	fs_initcall(usb_dr_init);
 #else
-	subsys_initcall(usb_dr_init);
+	module_init(usb_dr_init);
 #endif
diff --git a/arch/arm/mach-mx25/mx25_3stack.c b/arch/arm/mach-mx25/mx25_3stack.c
index c73bcbf6371e..cc651bf713ec 100644
--- a/arch/arm/mach-mx25/mx25_3stack.c
+++ b/arch/arm/mach-mx25/mx25_3stack.c
@@ -318,7 +318,7 @@ static struct spi_board_info mxc_spi_board_info[] __initdata = {
 	 .max_speed_hz = 18000000,
 	 .bus_num = 1,
 	 .chip_select = 0,
-	 .mode = SPI_MODE_0,
+	 .mode = SPI_MODE_2,
 	 },
 	{
 	 .modalias = "wm8580_spi",
diff --git a/arch/arm/mach-mx25/usb_dr.c b/arch/arm/mach-mx25/usb_dr.c
index b3d024cb06f8..b185d5cdeff5 100644
--- a/arch/arm/mach-mx25/usb_dr.c
+++ b/arch/arm/mach-mx25/usb_dr.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved.
  */
 
 /*
@@ -39,7 +39,7 @@ static struct fsl_usb2_platform_data __maybe_unused dr_utmi_config = {
 };
 
 /*
- * OTG resources
+ * resources
  */
 static struct resource otg_resources[] = {
 	[0] = {
@@ -53,22 +53,6 @@ static struct resource otg_resources[] = {
 	       },
 };
 
-/*
- * UDC resources (same as OTG resource)
- */
-static struct resource udc_resources[] = {
-	[0] = {
-	       .start = (u32)(USB_OTGREGS_BASE),
-	       .end   = (u32)(USB_OTGREGS_BASE + 0x1ff),
-	       .flags = IORESOURCE_MEM,
-	       },
-	[1] = {
-	       .start = MXC_INT_USB_OTG,
-	       .flags = IORESOURCE_IRQ,
-	       },
-};
-
-
 static u64 dr_udc_dmamask = ~(u32) 0;
 static void dr_udc_release(struct device *dev)
 {
@@ -91,8 +75,8 @@ static struct platform_device __maybe_unused dr_udc_device = {
 		.dma_mask          = &dr_udc_dmamask,
 		.coherent_dma_mask = 0xffffffff,
 	},
-	.resource      = udc_resources,
-	.num_resources = ARRAY_SIZE(udc_resources),
+	.resource      = otg_resources,
+	.num_resources = ARRAY_SIZE(otg_resources),
 };
 
 static struct platform_device __maybe_unused dr_otg_device = {
diff --git a/arch/arm/mach-mx28/bus_freq.c b/arch/arm/mach-mx28/bus_freq.c
index ef01a41fc095..1ea76cbdb4e3 100644
--- a/arch/arm/mach-mx28/bus_freq.c
+++ b/arch/arm/mach-mx28/bus_freq.c
@@ -49,14 +49,16 @@
 #define BF(value, field) (((value) << BP_##field) & BM_##field)
 
 struct profile profiles[] = {
-	{ 454736, 151570, 205710, 0, 1550000,
+	{ 454736, 151580, 196360, 0, 1550000,
 	1450000, 355000, 3300000, 1750000, 24000, 0 },
-	{ 360000, 120000, 130910, 0, 1350000,
-	1250000, 200000, 3300000, 1750000, 24000, 0 },
-	{ 261818, 130910, 130910, 0, 1350000,
-	1250000, 173000, 3300000, 1750000, 24000, 0 },
-	{  64000,  64000, 130910, 3, 1350000,
-	1250000, 150000, 3300000, 1750000, 24000, 0 },
+	{ 392727, 130910, 160000, 0, 1475000,
+	1375000, 225000, 3300000, 1750000, 24000, 0 },
+	{ 360000, 120000, 130910, 0, 1375000,
+	1275000, 200000, 3300000, 1750000, 24000, 0 },
+	{ 261818, 130910, 130910, 0, 1275000,
+	1175000, 173000, 3300000, 1750000, 24000, 0 },
+	{  64000,  64000, 130910, 3, 1050000,
+	975000, 150000, 3300000, 1750000, 24000, 0 },
 	{  0,  0,  0, 0, 0,
 	0, 0, 0, 0, 0, 0 },
 };
diff --git a/arch/arm/mach-mx28/device.c b/arch/arm/mach-mx28/device.c
index 35e8f14a5568..7305b35bc74b 100644
--- a/arch/arm/mach-mx28/device.c
+++ b/arch/arm/mach-mx28/device.c
@@ -27,7 +27,6 @@
 #include <linux/platform_device.h>
 #include <linux/mmc/host.h>
 #include <linux/phy.h>
-#include <linux/etherdevice.h>
 #include <linux/fec.h>
 #include <linux/gpmi-nfc.h>
 
@@ -36,7 +35,6 @@
 #include <mach/hardware.h>
 #include <mach/regs-timrot.h>
 #include <mach/regs-lradc.h>
-#include <mach/regs-ocotp.h>
 #include <mach/device.h>
 #include <mach/dma.h>
 #include <mach/lradc.h>
@@ -556,10 +554,9 @@ static struct mxs_mmc_platform_data mmc0_data = {
 	.get_wp		= mxs_mmc_get_wp_ssp0,
 	.cmd_pullup	= mxs_mmc_cmd_pullup_ssp0,
 	.setclock	= mxs_mmc_setclock_ssp0,
-	.caps 		= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA
-				| MMC_CAP_DATA_DDR,
+	.caps 		= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
 	.min_clk	= 400000,
-	.max_clk	= 48000000,
+	.max_clk	= 52000000,
 	.read_uA        = 50000,
 	.write_uA       = 70000,
 	.clock_mmc = "ssp.0",
@@ -595,10 +592,9 @@ static struct mxs_mmc_platform_data mmc1_data = {
 	.get_wp		= mxs_mmc_get_wp_ssp1,
 	.cmd_pullup	= mxs_mmc_cmd_pullup_ssp1,
 	.setclock	= mxs_mmc_setclock_ssp1,
-	.caps 		= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA
-				| MMC_CAP_DATA_DDR,
+	.caps 		= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
 	.min_clk	= 400000,
-	.max_clk	= 48000000,
+	.max_clk	= 52000000,
 	.read_uA        = 50000,
 	.write_uA       = 70000,
 	.clock_mmc = "ssp.1",
@@ -761,16 +757,7 @@ static void __init mx28_init_fec(void)
 {
 	struct platform_device *pdev;
 	struct mxs_dev_lookup *lookup;
-	struct fec_platform_data *pfec;
 	int i;
-	u32 val;
-
-	__raw_writel(BM_OCOTP_CTRL_RD_BANK_OPEN,
-			IO_ADDRESS(OCOTP_PHYS_ADDR) + HW_OCOTP_CTRL_SET);
-
-	while (BM_OCOTP_CTRL_BUSY &
-		__raw_readl(IO_ADDRESS(OCOTP_PHYS_ADDR) + HW_OCOTP_CTRL))
-		udelay(10);
 
 	lookup = mxs_get_devices("mxs-fec");
 	if (lookup == NULL || IS_ERR(lookup))
@@ -778,8 +765,6 @@ static void __init mx28_init_fec(void)
 
 	for (i = 0; i < lookup->size; i++) {
 		pdev = lookup->pdev + i;
-		val =  __raw_readl(IO_ADDRESS(OCOTP_PHYS_ADDR) +
-						HW_OCOTP_CUSTn(pdev->id));
 		switch (pdev->id) {
 		case 0:
 			pdev->resource = fec0_resource;
@@ -794,15 +779,6 @@ static void __init mx28_init_fec(void)
 		default:
 			return;
 		}
-
-		pfec = (struct fec_platform_data *)pdev->dev.platform_data;
-		pfec->mac[0] = 0x00;
-		pfec->mac[1] = 0x04;
-		pfec->mac[2] = (val >> 24) & 0xFF;
-		pfec->mac[3] = (val >> 16) & 0xFF;
-		pfec->mac[4] = (val >> 8) & 0xFF;
-		pfec->mac[5] = (val >> 0) & 0xFF;
-
 		mxs_add_device(pdev, 2);
 	}
 }
@@ -848,36 +824,13 @@ static struct switch_platform_data l2switch_data = {
 static void __init mx28_init_l2switch(void)
 {
 	struct platform_device *pdev;
-	struct switch_platform_data *pswitch;
-	struct fec_platform_data *pfec;
-	u32 val;
-
-	__raw_writel(BM_OCOTP_CTRL_RD_BANK_OPEN,
-			IO_ADDRESS(OCOTP_PHYS_ADDR) + HW_OCOTP_CTRL_SET);
-
-	while (BM_OCOTP_CTRL_BUSY &
-		__raw_readl(IO_ADDRESS(OCOTP_PHYS_ADDR) + HW_OCOTP_CTRL))
-		udelay(10);
-
 	pdev = mxs_get_device("mxs-l2switch", 0);
 	if (pdev == NULL || IS_ERR(pdev))
 		return;
 
-	val =  __raw_readl(IO_ADDRESS(OCOTP_PHYS_ADDR) +
-					HW_OCOTP_CUSTn(pdev->id));
 	pdev->resource = l2switch_resources;
 	pdev->num_resources = ARRAY_SIZE(l2switch_resources);
 	pdev->dev.platform_data = &l2switch_data;
-
-	pswitch = (struct switch_platform_data *)pdev->dev.platform_data;
-	pfec = pswitch->fec_enet;
-	pfec->mac[0] = 0x00;
-	pfec->mac[1] = 0x04;
-	pfec->mac[2] = (val >> 24) & 0xFF;
-	pfec->mac[3] = (val >> 16) & 0xFF;
-	pfec->mac[4] = (val >> 8) & 0xFF;
-	pfec->mac[5] = (val >> 0) & 0xFF;
-
 	mxs_add_device(pdev, 2);
 }
 #else
@@ -1459,50 +1412,6 @@ static void mx28_init_persistent()
 }
 #endif
 
-#if defined(CONFIG_FSL_OTP)
-/* Building up eight registers's names of a bank */
-#define BANK(a, b, c, d, e, f, g, h)	\
-	{\
-	("HW_OCOTP_"#a), ("HW_OCOTP_"#b), ("HW_OCOTP_"#c), ("HW_OCOTP_"#d), \
-	("HW_OCOTP_"#e), ("HW_OCOTP_"#f), ("HW_OCOTP_"#g), ("HW_OCOTP_"#h) \
-	}
-
-#define BANKS		(5)
-#define BANK_ITEMS	(8)
-static const char *bank_reg_desc[BANKS][BANK_ITEMS] = {
-	BANK(CUST0, CUST1, CUST2, CUST3, CRYPTO0, CRYPTO1, CRYPTO2, CRYPTO3),
-	BANK(HWCAP0, HWCAP1, HWCAP2, HWCAP3, HWCAP4, HWCAP5, SWCAP, CUSTCAP),
-	BANK(LOCK, OPS0, OPS1, OPS2, OPS3, UN0, UN1, UN2),
-	BANK(ROM0, ROM1, ROM2, ROM3, ROM4, ROM5, ROM6, ROM7),
-	BANK(SRK0, SRK1, SRK2, SRK3, SRK4, SRK5, SRK6, SRK7),
-};
-
-static struct fsl_otp_data otp_data = {
-	.fuse_name	= (char **)bank_reg_desc,
-	.regulator_name	= "vddio",
-	.fuse_num	= BANKS * BANK_ITEMS,
-};
-#undef BANK
-#undef BANKS
-#undef BANK_ITEMS
-
-static void __init mx28_init_otp(void)
-{
-	struct platform_device *pdev;
-	pdev = mxs_get_device("ocotp", 0);
-	if (pdev == NULL || IS_ERR(pdev))
-		return;
-	pdev->dev.platform_data = &otp_data;
-	pdev->resource = NULL;
-	pdev->num_resources = 0;
-	mxs_add_device(pdev, 3);
-}
-#else
-static void mx28_init_otp(void)
-{
-}
-#endif
-
 int __init mx28_device_init(void)
 {
 	mx28_init_dma();
@@ -1527,7 +1436,6 @@ int __init mx28_device_init(void)
 	mx28_init_dcp();
 	mx28_init_battery();
 	mx28_init_persistent();
-	mx28_init_otp();
 	return 0;
 }
 
diff --git a/arch/arm/mach-mx28/emi_settings.c b/arch/arm/mach-mx28/emi_settings.c
index 56df6ad0c0d4..7dd62b9dd65a 100644
--- a/arch/arm/mach-mx28/emi_settings.c
+++ b/arch/arm/mach-mx28/emi_settings.c
@@ -27,6 +27,7 @@
 #include <linux/platform_device.h>
 #include <linux/mmc/host.h>
 #include <linux/phy.h>
+#include <linux/fec.h>
 
 #include <asm/mach/map.h>
 
diff --git a/arch/arm/mach-mx28/mx28evk.c b/arch/arm/mach-mx28/mx28evk.c
index 37beb27f7065..768b21a5ffe5 100644
--- a/arch/arm/mach-mx28/mx28evk.c
+++ b/arch/arm/mach-mx28/mx28evk.c
@@ -39,7 +39,7 @@ static struct i2c_board_info __initdata mxs_i2c_device[] = {
 	{ I2C_BOARD_INFO("sgtl5000-i2c", 0x14), .flags = I2C_M_TEN }
 };
 
-static void __init i2c_device_init(void)
+static void i2c_device_init(void)
 {
 	i2c_register_board_info(0, mxs_i2c_device, ARRAY_SIZE(mxs_i2c_device));
 }
diff --git a/arch/arm/mach-mx28/mx28evk.h b/arch/arm/mach-mx28/mx28evk.h
index d973c0f7ef19..58910271343d 100644
--- a/arch/arm/mach-mx28/mx28evk.h
+++ b/arch/arm/mach-mx28/mx28evk.h
@@ -21,8 +21,5 @@
 
 extern void __init mx28evk_pins_init(void);
 extern int mx28evk_enet_gpio_init(void);
-void mx28evk_enet_io_lowerpower_enter(void);
-void mx28evk_enet_io_lowerpower_exit(void);
-
 
 #endif /* __ASM_ARM_MACH_MX28EVK_H */
diff --git a/arch/arm/mach-mx28/mx28evk_pins.c b/arch/arm/mach-mx28/mx28evk_pins.c
index 7d5b64328324..a7c81b3cf023 100644
--- a/arch/arm/mach-mx28/mx28evk_pins.c
+++ b/arch/arm/mach-mx28/mx28evk_pins.c
@@ -531,106 +531,16 @@ static struct pin_desc mx28evk_fixed_pins[] = {
 	 .name	= "SSP0_SCK",
 	 .id	= PINID_SSP0_SCK,
 	 .fun	= PIN_FUN1,
-	 .strength	= PAD_12MA,
+	 .strength	= PAD_8MA,
 	 .voltage	= PAD_3_3V,
 	 .pullup	= 0,
-	 .drive 	= 2,
-	 .pull 		= 0,
-	 },
-#endif
-#if defined(CONFIG_LEDS_MXS) || defined(CONFIG_LEDS_MXS_MODULE)
-	{
-	 .name = "LEDS_PWM0",
-	 .id = PINID_AUART1_RX,
-	 .fun           = PIN_FUN3,
-	 .strength      = PAD_8MA,
-	 .voltage       = PAD_3_3V,
-	 .pullup        = 1,
-	 .drive         = 1,
-	 .pull          = 1,
-	 },
-	{
-	 .name = "LEDS_PWM1",
-	 .id = PINID_AUART1_TX,
-	 .fun           = PIN_FUN3,
-	 .strength      = PAD_8MA,
-	 .voltage       = PAD_3_3V,
-	 .pullup        = 1,
-	 .drive         = 1,
-	 .pull          = 1,
-	 },
-#endif
-#if defined(CONFIG_SND_MXS_SOC_DAI) || defined(CONFIG_SND_MXS_SOC_DAI_MODULE)
-	/* Configurations of SAIF0 port pins */
-	{
-	 .name	= "SAIF0_MCLK",
-	 .id	= PINID_SAIF0_MCLK,
-	 .fun	= PIN_FUN1,
-	 .strength	= PAD_12MA,
-	 .voltage	= PAD_3_3V,
-	 .pullup	= 1,
-	 .drive 	= 1,
-	 .pull 		= 1,
-	 },
-	{
-	 .name	= "SAIF0_LRCLK",
-	 .id	= PINID_SAIF0_LRCLK,
-	 .fun	= PIN_FUN1,
-	 .strength	= PAD_12MA,
-	 .voltage	= PAD_3_3V,
-	 .pullup	= 1,
 	 .drive 	= 1,
-	 .pull 		= 1,
-	 },
-	{
-	 .name	= "SAIF0_BITCLK",
-	 .id	= PINID_SAIF0_BITCLK,
-	 .fun	= PIN_FUN1,
-	 .strength	= PAD_12MA,
-	 .voltage	= PAD_3_3V,
-	 .pullup	= 1,
-	 .drive 	= 1,
-	 .pull 		= 1,
-	 },
-	{
-	 .name	= "SAIF0_SDATA0",
-	 .id	= PINID_SAIF0_SDATA0,
-	 .fun	= PIN_FUN1,
-	 .strength	= PAD_12MA,
-	 .voltage	= PAD_3_3V,
-	 .pullup	= 1,
-	 .drive 	= 1,
-	 .pull 		= 1,
-	 },
-	{
-	 .name	= "SAIF1_SDATA0",
-	 .id	= PINID_SAIF1_SDATA0,
-	 .fun	= PIN_FUN1,
-	 .strength	= PAD_12MA,
-	 .voltage	= PAD_3_3V,
-	 .pullup	= 1,
-	 .drive 	= 1,
-	 .pull 		= 1,
+	 .pull 		= 0,
 	 },
 #endif
-#if defined(CONFIG_SND_SOC_MXS_SPDIF) || \
-       defined(CONFIG_SND_SOC_MXS_SPDIF_MODULE)
-	{
-	 .name	= "SPDIF",
-	 .id	= PINID_SPDIF,
-	 .fun	= PIN_FUN1,
-	 .strength	= PAD_12MA,
-	 .voltage	= PAD_3_3V,
-	 .pullup	= 1,
-	 .drive 	= 1,
-	 .pull 		= 1,
-	},
-#endif
-};
 
 #if defined(CONFIG_FEC) || defined(CONFIG_FEC_MODULE)\
 	|| defined(CONFIG_FEC_L2SWITCH)
-static struct pin_desc mx28evk_eth_pins[] = {
 	{
 	 .name = "ENET0_MDC",
 	 .id = PINID_ENET0_MDC,
@@ -781,8 +691,97 @@ static struct pin_desc mx28evk_eth_pins[] = {
 	 .voltage = PAD_3_3V,
 	 .drive	= 1,
 	 },
-};
 #endif
+#if defined(CONFIG_LEDS_MXS) || defined(CONFIG_LEDS_MXS_MODULE)
+	{
+	 .name = "LEDS_PWM0",
+	 .id = PINID_AUART1_RX,
+	 .fun           = PIN_FUN3,
+	 .strength      = PAD_8MA,
+	 .voltage       = PAD_3_3V,
+	 .pullup        = 1,
+	 .drive         = 1,
+	 .pull          = 1,
+	 },
+	{
+	 .name = "LEDS_PWM1",
+	 .id = PINID_AUART1_TX,
+	 .fun           = PIN_FUN3,
+	 .strength      = PAD_8MA,
+	 .voltage       = PAD_3_3V,
+	 .pullup        = 1,
+	 .drive         = 1,
+	 .pull          = 1,
+	 },
+#endif
+#if defined(CONFIG_SND_MXS_SOC_DAI) || defined(CONFIG_SND_MXS_SOC_DAI_MODULE)
+	/* Configurations of SAIF0 port pins */
+	{
+	 .name	= "SAIF0_MCLK",
+	 .id	= PINID_SAIF0_MCLK,
+	 .fun	= PIN_FUN1,
+	 .strength	= PAD_12MA,
+	 .voltage	= PAD_3_3V,
+	 .pullup	= 1,
+	 .drive 	= 1,
+	 .pull 		= 1,
+	 },
+	{
+	 .name	= "SAIF0_LRCLK",
+	 .id	= PINID_SAIF0_LRCLK,
+	 .fun	= PIN_FUN1,
+	 .strength	= PAD_12MA,
+	 .voltage	= PAD_3_3V,
+	 .pullup	= 1,
+	 .drive 	= 1,
+	 .pull 		= 1,
+	 },
+	{
+	 .name	= "SAIF0_BITCLK",
+	 .id	= PINID_SAIF0_BITCLK,
+	 .fun	= PIN_FUN1,
+	 .strength	= PAD_12MA,
+	 .voltage	= PAD_3_3V,
+	 .pullup	= 1,
+	 .drive 	= 1,
+	 .pull 		= 1,
+	 },
+	{
+	 .name	= "SAIF0_SDATA0",
+	 .id	= PINID_SAIF0_SDATA0,
+	 .fun	= PIN_FUN1,
+	 .strength	= PAD_12MA,
+	 .voltage	= PAD_3_3V,
+	 .pullup	= 1,
+	 .drive 	= 1,
+	 .pull 		= 1,
+	 },
+	{
+	 .name	= "SAIF1_SDATA0",
+	 .id	= PINID_SAIF1_SDATA0,
+	 .fun	= PIN_FUN1,
+	 .strength	= PAD_12MA,
+	 .voltage	= PAD_3_3V,
+	 .pullup	= 1,
+	 .drive 	= 1,
+	 .pull 		= 1,
+	 },
+#endif
+#if defined(CONFIG_SND_SOC_MXS_SPDIF) || \
+       defined(CONFIG_SND_SOC_MXS_SPDIF_MODULE)
+	{
+	 .name	= "SPDIF",
+	 .id	= PINID_SPDIF,
+	 .fun	= PIN_FUN1,
+	 .strength	= PAD_12MA,
+	 .voltage	= PAD_3_3V,
+	 .pullup	= 1,
+	 .drive 	= 1,
+	 .pull 		= 1,
+	},
+#endif
+};
+
 
 static int __initdata enable_ssp1 = { 0 };
 static int __init ssp1_setup(char *__unused)
@@ -898,10 +897,10 @@ static struct pin_desc mx28evk_ssp1_pins[] = {
 	 .name	= "SSP1_SCK",
 	 .id	= PINID_GPMI_WRN,
 	 .fun	= PIN_FUN2,
-	 .strength	= PAD_12MA,
+	 .strength	= PAD_8MA,
 	 .voltage	= PAD_3_3V,
 	 .pullup	= 0,
-	 .drive 	= 2,
+	 .drive 	= 1,
 	 .pull 		= 0,
 	 },
 };
@@ -1088,49 +1087,11 @@ int mx28evk_enet_gpio_init(void)
 
 	return 0;
 }
-
-void mx28evk_enet_io_lowerpower_enter(void)
-{
-	int i;
-	gpio_direction_output(MXS_PIN_TO_GPIO(PINID_SSP1_DATA3), 1);
-	gpio_direction_output(MXS_PIN_TO_GPIO(PINID_ENET0_RX_CLK), 0);
-	gpio_request(MXS_PIN_TO_GPIO(PINID_ENET0_TX_CLK), "ETH_INT");
-	gpio_direction_output(MXS_PIN_TO_GPIO(PINID_ENET0_TX_CLK), 0);
-
-	for (i = 0; i < ARRAY_SIZE(mx28evk_eth_pins); i++) {
-		mxs_release_pin(mx28evk_eth_pins[i].id,
-			mx28evk_eth_pins[i].name);
-		gpio_request(MXS_PIN_TO_GPIO(mx28evk_eth_pins[i].id),
-			mx28evk_eth_pins[i].name);
-		gpio_direction_output(
-			MXS_PIN_TO_GPIO(mx28evk_eth_pins[i].id), 0);
-	}
-
-}
-
-void mx28evk_enet_io_lowerpower_exit(void)
-{
-	int i;
-	gpio_direction_output(MXS_PIN_TO_GPIO(PINID_SSP1_DATA3), 0);
-	gpio_direction_output(MXS_PIN_TO_GPIO(PINID_ENET0_RX_CLK), 1);
-	gpio_free(MXS_PIN_TO_GPIO(PINID_ENET0_TX_CLK));
-	for (i = 0; i < ARRAY_SIZE(mx28evk_eth_pins); i++) {
-		gpio_free(MXS_PIN_TO_GPIO(mx28evk_eth_pins[i].id));
-		mxs_request_pin(mx28evk_eth_pins[i].id,
-			mx28evk_eth_pins[i].fun,
-			mx28evk_eth_pins[i].name);
-	}
-}
-
 #else
 int mx28evk_enet_gpio_init(void)
 {
 	return 0;
 }
-void mx28evk_enet_io_lowerpower_enter(void)
-{}
-void mx28evk_enet_io_lowerpower_exit(void)
-{}
 #endif
 
 void __init mx28evk_init_pin_group(struct pin_desc *pins, unsigned count)
@@ -1174,9 +1135,5 @@ void __init mx28evk_pins_init(void)
 		mx28evk_init_pin_group(mx28evk_gpmi_pins,
 						ARRAY_SIZE(mx28evk_gpmi_pins));
 	}
-#if defined(CONFIG_FEC) || defined(CONFIG_FEC_MODULE)\
-	|| defined(CONFIG_FEC_L2SWITCH)
-		mx28evk_init_pin_group(mx28evk_eth_pins,
-						ARRAY_SIZE(mx28evk_eth_pins));
-#endif
+
 }
diff --git a/arch/arm/mach-mx28/pm.c b/arch/arm/mach-mx28/pm.c
index 4ac13bc3248c..c26a495f59e2 100644
--- a/arch/arm/mach-mx28/pm.c
+++ b/arch/arm/mach-mx28/pm.c
@@ -36,13 +36,12 @@
 #include <mach/dma.h>
 #include <mach/regs-rtc.h>
 #include "regs-clkctrl.h"
+#include "regs-pinctrl.h"
 #include <mach/regs-power.h>
 #include <mach/regs-pwm.h>
 #include <mach/regs-rtc.h>
 #include <mach/../../regs-icoll.h>
 #include "regs-dram.h"
-#include "mx28_pins.h"
-#include "mx28evk.h"
 
 #include "sleep.h"
 
@@ -80,8 +79,7 @@ static inline void do_standby(void)
 	u32 reg_clkctrl_clkseq, reg_clkctrl_xtal;
 	unsigned long iram_phy_addr;
 	void *iram_virtual_addr;
-	int wakeupirq;
-	mx28evk_enet_io_lowerpower_enter();
+
 	/*
 	 * 1) switch clock domains from PLL to 24MHz
 	 * 2) lower voltage (TODO)
@@ -112,8 +110,7 @@ static inline void do_standby(void)
 		cpu_parent = clk_get_parent(cpu_clk);
 		hbus_rate = clk_get_rate(hbus_clk);
 		clk_set_parent(cpu_clk, osc_clk);
-	} else
-		pr_err("fail to get cpu clk\n");
+	}
 
 	local_fiq_disable();
 
@@ -125,18 +122,15 @@ static inline void do_standby(void)
 
 	reg_clkctrl_xtal = __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL);
 
-
 	/* do suspend */
 	mx28_cpu_standby_ptr = iram_virtual_addr;
 
 	mx28_cpu_standby_ptr();
 
-	wakeupirq = __raw_readl(IO_ADDRESS(ICOLL_PHYS_ADDR) + HW_ICOLL_STAT);
-
-	pr_info("wakeup irq = %d\n", wakeupirq);
 
 	__raw_writel(reg_clkctrl_clkseq, REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ);
 	__raw_writel(reg_clkctrl_xtal, REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL);
+
 	saved_sleep_state = 0;  /* waking from standby */
 	__raw_writel(BM_POWER_CTRL_PSWITCH_IRQ,
 		REGS_POWER_BASE + HW_POWER_CTRL_CLR);
@@ -155,7 +149,6 @@ static inline void do_standby(void)
 	clk_put(cpu_clk);
 
 	iram_free(iram_phy_addr, MAX_POWEROFF_CODE_SIZE);
-	mx28evk_enet_io_lowerpower_exit();
 }
 
 static noinline void do_mem(void)
@@ -262,52 +255,38 @@ static struct mx28_pswitch_state pswitch_state = {
 	.dev_running = 0,
 };
 
-#define PSWITCH_POWER_DOWN_DELAY 30
-static 	struct delayed_work pswitch_work;
-static void pswitch_check_work(struct work_struct *work)
+static irqreturn_t pswitch_interrupt(int irq, void *dev)
 {
 	int pin_value, i;
-	for (i = 0; i < PSWITCH_POWER_DOWN_DELAY; i++) {
+
+	/* check if irq by pswitch */
+	if (!(__raw_readl(REGS_POWER_BASE + HW_POWER_CTRL) &
+		BM_POWER_CTRL_PSWITCH_IRQ))
+		return IRQ_HANDLED;
+	for (i = 0; i < 3000; i++) {
 		pin_value = __raw_readl(REGS_POWER_BASE + HW_POWER_STS) &
 			BF_POWER_STS_PSWITCH(0x1);
 		if (pin_value == 0)
 			break;
-		msleep(100);
+		mdelay(1);
 	}
-	if (i < PSWITCH_POWER_DOWN_DELAY) {
+	if (i < 3000) {
 		pr_info("pswitch goto suspend\n");
 		complete(&suspend_request);
 	} else {
 		pr_info("release pswitch to power down\n");
-		for (i = 0; i < 500; i++) {
+		for (i = 0; i < 5000; i++) {
 			pin_value = __raw_readl(REGS_POWER_BASE + HW_POWER_STS)
 				& BF_POWER_STS_PSWITCH(0x1);
 			if (pin_value == 0)
 				break;
-			msleep(10);
+			mdelay(1);
 		}
 		pr_info("pswitch power down\n");
 		mx28_pm_power_off();
 	}
 	__raw_writel(BM_POWER_CTRL_PSWITCH_IRQ,
 		REGS_POWER_BASE + HW_POWER_CTRL_CLR);
-	__raw_writel(BM_POWER_CTRL_ENIRQ_PSWITCH,
-		REGS_POWER_BASE + HW_POWER_CTRL_SET);
-	__raw_writel(BM_POWER_CTRL_PSWITCH_IRQ,
-		REGS_POWER_BASE + HW_POWER_CTRL_CLR);
-}
-
-
-static irqreturn_t pswitch_interrupt(int irq, void *dev)
-{
-
-	/* check if irq by pswitch */
-	if (!(__raw_readl(REGS_POWER_BASE + HW_POWER_CTRL) &
-		BM_POWER_CTRL_PSWITCH_IRQ))
-		return IRQ_HANDLED;
-	__raw_writel(BM_POWER_CTRL_ENIRQ_PSWITCH,
-		REGS_POWER_BASE + HW_POWER_CTRL_CLR);
-	schedule_delayed_work(&pswitch_work, 1);
 	return IRQ_HANDLED;
 }
 
@@ -320,7 +299,6 @@ static struct irqaction pswitch_irq = {
 
 static void init_pswitch(void)
 {
-	INIT_DELAYED_WORK(&pswitch_work, pswitch_check_work);
 	kthread_run(suspend_thread_fn, NULL, "pswitch");
 	__raw_writel(BM_POWER_CTRL_PSWITCH_IRQ,
 		REGS_POWER_BASE + HW_POWER_CTRL_CLR);
diff --git a/arch/arm/mach-mx28/sleep.S b/arch/arm/mach-mx28/sleep.S
index 54e86bd4f717..438f588f85d3 100644
--- a/arch/arm/mach-mx28/sleep.S
+++ b/arch/arm/mach-mx28/sleep.S
@@ -25,7 +25,6 @@
 #include <mach/hardware.h>
 #include <mach/regs-power.h>
 #include <mach/regs-rtc.h>
-#include "regs-pinctrl.h"
 #include "regs-clkctrl.h"
 #include "regs-dram.h"
 #include "sleep.h"
@@ -40,104 +39,11 @@
 
 #define HW_DRAM_CTL17_ADDR \
 	(MX28_SOC_IO_ADDRESS(DRAM_PHYS_ADDR) + HW_DRAM_CTL17)
-#define HW_DRAM_CTL22_ADDR \
-	(MX28_SOC_IO_ADDRESS(DRAM_PHYS_ADDR) + HW_DRAM_CTL22)
-
 #define HW_RTC_PERSISTENT0_ADDR \
 	(MX28_SOC_IO_ADDRESS(RTC_PHYS_ADDR) + HW_RTC_PERSISTENT0)
-#define HW_CLKCTRL_EMI_ADDR \
-	(MX28_SOC_IO_ADDRESS(CLKCTRL_PHYS_ADDR) + HW_CLKCTRL_EMI)
-#define HW_CLKCTRL_PLL0CTRL0_ADDR \
-	(MX28_SOC_IO_ADDRESS(CLKCTRL_PHYS_ADDR) + HW_CLKCTRL_PLL0CTRL0)
-#define HW_POWER_VDDIOCTRL_ADDR \
-	(MX28_SOC_IO_ADDRESS(POWER_PHYS_ADDR) + HW_POWER_VDDIOCTRL)
-#define HW_POWER_VDDDCTRL_ADDR \
-	(MX28_SOC_IO_ADDRESS(POWER_PHYS_ADDR) + HW_POWER_VDDDCTRL)
-#define HW_POWER_VDDACTRL_ADDR \
-	(MX28_SOC_IO_ADDRESS(POWER_PHYS_ADDR) + HW_POWER_VDDACTRL)
-#define HW_PINCTRL_EMI_DS_CTRL_ADDR \
-	(MX28_SOC_IO_ADDRESS(PINCTRL_PHYS_ADDR) + HW_PINCTRL_EMI_DS_CTRL)
-
-#define HW_POWER_LOOPCTRL_ADDR \
-	(MX28_SOC_IO_ADDRESS(POWER_PHYS_ADDR) + HW_POWER_LOOPCTRL)
-
-#define HW_POWER_MINPWR_ADDR \
-	(MX28_SOC_IO_ADDRESS(POWER_PHYS_ADDR) + HW_POWER_MINPWR)
 
 #define PHYS_RAM_START		0x40000000
 
-#define LOWER_VDDIO 6
-#define LOWER_VDDA 9
-#define LOWER_VDDD 0x16
-
-#define VDDIOCTRL_BACKUP 0
-#define VDDACTRL_BACKUP 1
-#define VDDDCTRL_BACKUP 2
-#define POWER_LOOPCTRL_BACKUP 3
-#define POWER_MINPWR_BACKUP 4
-
-.macro PM_BITS_SET, addr, val
-	mov	r0, #(\addr & 0x000000FF)
-	orr	r0, r0, #(\addr & 0x0000FF00)
-	orr	r0, r0, #(\addr & 0x00FF0000)
-	orr	r0, r0, #(\addr & 0xFF000000)
-	ldr	r1, [r0]
-	orr	r1, r1, #(\val)
-	str r1, [r0]
-.endm
-
-.macro PM_BITS_CLR, addr, val
-	mov	r0, #(\addr & 0x000000FF)
-	orr	r0, r0, #(\addr & 0x0000FF00)
-	orr	r0, r0, #(\addr & 0x00FF0000)
-	orr	r0, r0, #(\addr & 0xFF000000)
-	ldr	r1, [r0]
-	bic	r1, r1, #(\val)
-	str r1, [r0]
-.endm
-
-.macro PM_BACKUP_REG, addr, num
-	mov	r0, #(\addr & 0x000000FF)
-	orr	r0, r0, #(\addr & 0x0000FF00)
-	orr	r0, r0, #(\addr & 0x00FF0000)
-	orr	r0, r0, #(\addr & 0xFF000000)
-	ldr	r1, [r0]
-	str r1, __mx28_temp_stack + \num * 4
-.endm
-
-.macro PM_WRITE_REG_MASK, addr, bitmask, val
-	mov	r0, #(\addr & 0x000000FF)
-	orr	r0, r0, #(\addr & 0x0000FF00)
-	orr	r0, r0, #(\addr & 0x00FF0000)
-	orr	r0, r0, #(\addr & 0xFF000000)
-	ldr	r1, [r0]
-	bic r1, r1, #(\bitmask)
-	orr r1, r1, #(\val)
-	str r1, [r0]
-.endm
-
-.macro PM_SET_AND_BACKUP_REG, addr, bitmask, val, num
-	mov	r0, #(\addr & 0x000000FF)
-	orr	r0, r0, #(\addr & 0x0000FF00)
-	orr	r0, r0, #(\addr & 0x00FF0000)
-	orr	r0, r0, #(\addr & 0xFF000000)
-	ldr	r1, [r0]
-	str r1, __mx28_temp_stack + \num * 4
-	bic r1, r1, #(\bitmask)
-	orr r1, r1, #(\val)
-	str r1, [r0]
-.endm
-
-.macro PM_SET_RESTORE_REG, addr, num
-	mov	r0, #(\addr & 0x000000FF)
-	orr	r0, r0, #(\addr & 0x0000FF00)
-	orr	r0, r0, #(\addr & 0x00FF0000)
-	orr	r0, r0, #(\addr & 0xFF000000)
-	ldr r1, __mx28_temp_stack + \num * 4
-	str r1, [r0]
-.endm
-
-
 .global cpu_arm926_switch_mm
 
 		.text
@@ -153,6 +59,7 @@ ENTRY(mx28_cpu_standby)
 	ldr	r1, __mx28_flush_cache_addr
 	mov	lr, pc
 	mov	pc, r1
+
 	@ put DRAM into self refresh
 	mov	r0, #(HW_DRAM_CTL17_ADDR & 0x000000FF)
 	orr	r0, r0, #(HW_DRAM_CTL17_ADDR & 0x0000FF00)
@@ -162,67 +69,6 @@ ENTRY(mx28_cpu_standby)
 	orr	r1, r1, #(BM_DRAM_CTL17_SREFRESH)
 	str	r1, [r0]
 	@ wait for it to actually happen
-	mov	r0, #24 << 5
-11:	sub	r0, r0, #1
-	cmp	r0, #0
-	bne	11b
-
-	@ gate clk
-	mov	r0, #(HW_CLKCTRL_EMI_ADDR & 0x000000FF)
-	orr	r0, r0, #(HW_CLKCTRL_EMI_ADDR & 0x0000FF00)
-	orr	r0, r0, #(HW_CLKCTRL_EMI_ADDR & 0x00FF0000)
-	orr	r0, r0, #(HW_CLKCTRL_EMI_ADDR & 0xFF000000)
-	ldr	r1, [r0]
-	orr	r1, r1, #(BM_CLKCTRL_EMI_CLKGATE)
-	str	r1, [r0]
-
-//	PM_SET_AND_BACKUP_REG HW_PINCTRL_EMI_DS_CTRL_ADDR,\
-//	BM_PINCTRL_EMI_DS_CTRL_DDR_MODE,\
-//	BF_PINCTRL_EMI_DS_CTRL_DDR_MODE(0x1), 4
-
-	// vddio
-	PM_SET_AND_BACKUP_REG HW_POWER_VDDIOCTRL_ADDR,\
-	BM_POWER_VDDIOCTRL_TRG, LOWER_VDDIO, VDDIOCTRL_BACKUP
-	mov	r0, #24 << 10
-1:	sub	r0, r0, #1
-	cmp	r0, #0
-	bne	1b
-
-	PM_SET_AND_BACKUP_REG HW_POWER_VDDACTRL_ADDR,\
-	BM_POWER_VDDACTRL_TRG, LOWER_VDDA, VDDACTRL_BACKUP
-	mov	r0, #24 << 10
-2:	sub	r0, r0, #1
-	cmp	r0, #0
-	bne	2b
-
-	PM_SET_AND_BACKUP_REG HW_POWER_VDDDCTRL_ADDR,\
-	BM_POWER_VDDDCTRL_TRG, LOWER_VDDD, VDDDCTRL_BACKUP
-	mov	r0, #24 << 10
-3:	sub	r0, r0, #1
-	cmp	r0, #0
-	bne	3b
-
-	PM_BACKUP_REG HW_POWER_LOOPCTRL_ADDR, POWER_LOOPCTRL_BACKUP
-	PM_BACKUP_REG HW_POWER_MINPWR_ADDR, POWER_MINPWR_BACKUP
-
-//	PM_BITS_CLR	HW_POWER_LOOPCTRL_ADDR, BM_POWER_LOOPCTRL_EN_RCSCALE
-//	PM_WRITE_REG_MASK	HW_POWER_LOOPCTRL_ADDR, BM_POWER_LOOPCTRL_DC_R,\
-//		(2<<BP_POWER_LOOPCTRL_DC_R)
-
-	// half fets
-	PM_BITS_SET HW_POWER_MINPWR_ADDR, BM_POWER_MINPWR_HALF_FETS
-
-	PM_BITS_CLR	HW_POWER_LOOPCTRL_ADDR, BM_POWER_LOOPCTRL_CM_HYST_THRESH
-	PM_BITS_CLR	HW_POWER_LOOPCTRL_ADDR, BM_POWER_LOOPCTRL_EN_CM_HYST
-	PM_BITS_CLR	HW_POWER_LOOPCTRL_ADDR, BM_POWER_LOOPCTRL_EN_DF_HYST
-
-	// enable PFM
-	PM_BITS_SET	HW_POWER_LOOPCTRL_ADDR, BM_POWER_LOOPCTRL_HYST_SIGN
-	PM_BITS_SET HW_POWER_MINPWR_ADDR, BM_POWER_MINPWR_EN_DC_PFM
-
-
-    //Gated PLL0
-	PM_BITS_CLR	HW_CLKCTRL_PLL0CTRL0_ADDR, BM_CLKCTRL_PLL0CTRL0_POWER
 
 	@ do enter standby
 	mov	r0, #(HW_CLKCTRL_CPU_ADDR & 0x000000FF)
@@ -243,39 +89,6 @@ ENTRY(mx28_cpu_standby)
 	nop
 	nop
 
-	PM_BITS_SET	HW_CLKCTRL_PLL0CTRL0_ADDR, BM_CLKCTRL_PLL0CTRL0_POWER
-
-	PM_SET_RESTORE_REG HW_POWER_MINPWR_ADDR, POWER_MINPWR_BACKUP
-
-	PM_SET_RESTORE_REG HW_POWER_LOOPCTRL_ADDR, POWER_LOOPCTRL_BACKUP
-
-	// vddio
-	PM_SET_RESTORE_REG HW_POWER_VDDIOCTRL_ADDR, VDDIOCTRL_BACKUP
-	mov	r0, #24 << 10
-10:	sub	r0, r0, #1
-	cmp	r0, #0
-	bne	10b
-	PM_SET_RESTORE_REG HW_POWER_VDDACTRL_ADDR, VDDACTRL_BACKUP
-	mov	r0, #24 << 10
-20:	sub	r0, r0, #1
-	cmp	r0, #0
-	bne	20b
-	PM_SET_RESTORE_REG HW_POWER_VDDDCTRL_ADDR, VDDDCTRL_BACKUP
-	mov	r0, #24 << 10
-30:	sub	r0, r0, #1
-	cmp	r0, #0
-	bne	30b
-
-	@ ungate clk
-	mov	r0, #(HW_CLKCTRL_EMI_ADDR & 0x000000FF)
-	orr	r0, r0, #(HW_CLKCTRL_EMI_ADDR & 0x0000FF00)
-	orr	r0, r0, #(HW_CLKCTRL_EMI_ADDR & 0x00FF0000)
-	orr	r0, r0, #(HW_CLKCTRL_EMI_ADDR & 0xFF000000)
-	ldr	r1, [r0]
-	bic	r1, r1, #(BM_CLKCTRL_EMI_CLKGATE)
-	str	r1, [r0]
-
-//	PM_SET_RESTORE_REG HW_PINCTRL_EMI_DS_CTRL_ADDR, 4
 	@ restore normal DRAM mode
 	mov	r0, #(HW_DRAM_CTL17_ADDR & 0x000000FF)
 	orr	r0, r0, #(HW_DRAM_CTL17_ADDR & 0x0000FF00)
@@ -285,10 +98,6 @@ ENTRY(mx28_cpu_standby)
 	bic	r1, r1, #BM_DRAM_CTL17_SREFRESH
 	str	r1, [r0]
 	@ wait for it to actually happen
-	mov	r0, #24 << 5
-12:	sub	r0, r0, #1
-	cmp	r0, #0
-	bne	12b
 
 	nop
 	nop
@@ -299,7 +108,7 @@ ENTRY(mx28_cpu_standby)
 
 	.space	0x100
 __mx28_temp_stack:
-	.space	128
+	.word	0
 
 #ifdef CONFIG_STMP378X_RAM_FREQ_SCALING
 #include "emi.inc"
diff --git a/arch/arm/mach-mx28/usb_dr.c b/arch/arm/mach-mx28/usb_dr.c
index 50a2f8b381af..13344ef0e26f 100644
--- a/arch/arm/mach-mx28/usb_dr.c
+++ b/arch/arm/mach-mx28/usb_dr.c
@@ -63,7 +63,7 @@ static struct fsl_usb2_platform_data __maybe_unused dr_utmi_config = {
 };
 
 /*
- * OTG resources
+ * resources
  */
 static struct resource otg_resources[] = {
 	[0] = {
@@ -78,22 +78,6 @@ static struct resource otg_resources[] = {
 	},
 };
 
-/*
- * UDC resources (same as OTG resource)
- */
-static struct resource udc_resources[] = {
-	[0] = {
-		.start	= (u32)USBCTRL0_PHYS_ADDR,
-		.end	= (u32)(USBCTRL0_PHYS_ADDR + 0x1ff),
-		.flags	= IORESOURCE_MEM,
-	},
-
-	[1] = {
-		.start	= IRQ_USB0,
-		.flags	= IORESOURCE_IRQ,
-	},
-};
-
 static u64 dr_udc_dmamask = ~(u32) 0;
 static void dr_udc_release(struct device *dev)
 {
@@ -127,8 +111,8 @@ static struct platform_device __maybe_unused dr_otg_device = {
 		.dma_mask          = &dr_otg_dmamask,
 		.coherent_dma_mask = 0xffffffff,
 	},
-	.resource      = udc_resources,
-	.num_resources = ARRAY_SIZE(udc_resources),
+	.resource      = otg_resources,
+	.num_resources = ARRAY_SIZE(otg_resources),
 };
 
 
@@ -172,5 +156,5 @@ void fsl_phy_set_power(struct fsl_xcvr_ops *this,
 #ifdef CONFIG_MXS_VBUS_CURRENT_DRAW
 	fs_initcall(usb_dr_init);
 #else
-	subsys_initcall(usb_dr_init);
+	module_init(usb_dr_init);
 #endif
diff --git a/arch/arm/mach-mx3/devices.c b/arch/arm/mach-mx3/devices.c
index c7d9560f0850..2861ecf81235 100644
--- a/arch/arm/mach-mx3/devices.c
+++ b/arch/arm/mach-mx3/devices.c
@@ -891,22 +891,6 @@ static inline void mxc_init_iim(void)
 }
 #endif
 
-static struct platform_device mxc_v4l2_device = {
-	.name = "mxc_v4l2_capture",
-	.id = 0,
-};
-
-static struct platform_device mxc_v4l2out_device = {
-	.name = "mxc_v4l2_output",
-	.id = 0,
-};
-
-static inline void mxc_init_v4l2()
-{
-	platform_device_register(&mxc_v4l2_device);
-	platform_device_register(&mxc_v4l2out_device);
-}
-
 int __init mxc_init_devices(void)
 {
 	mxc_init_wdt();
@@ -926,7 +910,6 @@ int __init mxc_init_devices(void)
 	mxc_init_vpu();
 	mxc_init_rnga();
 	mxc_init_iim();
-	mxc_init_v4l2();
 
 	return 0;
 }
diff --git a/arch/arm/mach-mx3/usb_dr.c b/arch/arm/mach-mx3/usb_dr.c
index d84fea7f1a80..7331463173e9 100644
--- a/arch/arm/mach-mx3/usb_dr.c
+++ b/arch/arm/mach-mx3/usb_dr.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved.
  */
 
 /*
@@ -59,7 +59,7 @@ static struct fsl_usb2_platform_data __maybe_unused dr_1504_config = {
 
 
 /*
- * OTG resources
+ * resources
  */
 static struct resource otg_resources[] = {
 	[0] = {
@@ -73,20 +73,6 @@ static struct resource otg_resources[] = {
 	},
 };
 
-/*
- * UDC resources (same as OTG resource)
- */
-static struct resource udc_resources[] = {
-	[0] = {
-		.start = (u32)(USB_OTGREGS_BASE),
-		.end   = (u32)(USB_OTGREGS_BASE + 0x1ff),
-		.flags = IORESOURCE_MEM,
-	},
-	[1] = {
-		.start = MXC_INT_USB3,
-		.flags = IORESOURCE_IRQ,
-	},
-};
 
 static u64 dr_udc_dmamask = ~(u32) 0;
 static void dr_udc_release(struct device *dev)
@@ -110,8 +96,8 @@ static struct platform_device __maybe_unused dr_udc_device = {
 		.dma_mask          = &dr_udc_dmamask,
 		.coherent_dma_mask = 0xffffffff,
 	},
-	.resource      = udc_resources,
-	.num_resources = ARRAY_SIZE(udc_resources),
+	.resource      = otg_resources,
+	.num_resources = ARRAY_SIZE(otg_resources),
 };
 
 static struct platform_device __maybe_unused dr_otg_device = {
diff --git a/arch/arm/mach-mx35/devices.c b/arch/arm/mach-mx35/devices.c
index 02c971659bd4..9d030e1ecfeb 100644
--- a/arch/arm/mach-mx35/devices.c
+++ b/arch/arm/mach-mx35/devices.c
@@ -902,22 +902,6 @@ static inline void mxc_init_ssi(void)
 }
 #endif /* CONFIG_SND_MXC_SOC_SSI */
 
-static struct platform_device mxc_v4l2_device = {
-	.name = "mxc_v4l2_capture",
-	.id = 0,
-};
-
-static struct platform_device mxc_v4l2out_device = {
-	.name = "mxc_v4l2_output",
-	.id = 0,
-};
-
-static inline void mxc_init_v4l2()
-{
-	platform_device_register(&mxc_v4l2_device);
-	platform_device_register(&mxc_v4l2out_device);
-}
-
 int __init mxc_init_devices(void)
 {
 	mxc_init_wdt();
@@ -937,7 +921,6 @@ int __init mxc_init_devices(void)
 	mxc_init_gpu();
 	mxc_init_ssi();
 	mxc_init_esai();
-	mxc_init_v4l2();
 
 	return 0;
 }
diff --git a/arch/arm/mach-mx35/mx35_3stack.c b/arch/arm/mach-mx35/mx35_3stack.c
index 868cf12ca2e6..35d639b5a534 100644
--- a/arch/arm/mach-mx35/mx35_3stack.c
+++ b/arch/arm/mach-mx35/mx35_3stack.c
@@ -605,13 +605,6 @@ static struct mxc_mmc_platform_data mmc1_data = {
 #endif
 	.min_clk = 150000,
 	.max_clk = 52000000,
-	/* Do not disable the eSDHC clk on MX35 3DS board,
-	* since SYSTEM can't boot up after the reset key
-	* is pressed when the SD/MMC boot mode is used.
-	* The root cause is that the ROM code don't ensure
-	* the SD/MMC clk is running when boot system.
-	* */
-	.clk_always_on = 1,
 	.card_inserted_state = 0,
 	.status = sdhc_get_card_det_status,
 	.wp_status = sdhc_write_protect,
@@ -658,7 +651,6 @@ static struct mxc_mmc_platform_data mmc2_data = {
 	.caps = MMC_CAP_4_BIT_DATA,
 	.min_clk = 150000,
 	.max_clk = 50000000,
-	.clk_always_on = 1,
 	.card_inserted_state = 0,
 	.status = sdhc_get_card_det_status,
 	.wp_status = sdhc_write_protect,
diff --git a/arch/arm/mach-mx35/usb_dr.c b/arch/arm/mach-mx35/usb_dr.c
index 4ebb27c5342b..18f76b90907a 100644
--- a/arch/arm/mach-mx35/usb_dr.c
+++ b/arch/arm/mach-mx35/usb_dr.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved.
  */
 
 /*
@@ -37,7 +37,7 @@ static struct fsl_usb2_platform_data __maybe_unused dr_utmi_config = {
 
 
 /*
- * OTG resources
+ * resources
  */
 static struct resource otg_resources[] = {
 	[0] = {
@@ -51,20 +51,6 @@ static struct resource otg_resources[] = {
 	},
 };
 
-/*
- * UDC resources (same as OTG resource)
- */
-static struct resource udc_resources[] = {
-	[0] = {
-		.start = (u32)(USB_OTGREGS_BASE),
-		.end   = (u32)(USB_OTGREGS_BASE + 0x1ff),
-		.flags = IORESOURCE_MEM,
-	},
-	[1] = {
-		.start = MXC_INT_USBOTG,
-		.flags = IORESOURCE_IRQ,
-	},
-};
 
 static u64 dr_udc_dmamask = ~(u32) 0;
 static void dr_udc_release(struct device *dev)
@@ -88,8 +74,8 @@ static struct platform_device __maybe_unused dr_udc_device = {
 		.dma_mask          = &dr_udc_dmamask,
 		.coherent_dma_mask = 0xffffffff,
 	},
-	.resource      = udc_resources,
-	.num_resources = ARRAY_SIZE(udc_resources),
+	.resource      = otg_resources,
+	.num_resources = ARRAY_SIZE(otg_resources),
 };
 
 static struct platform_device __maybe_unused dr_otg_device = {
diff --git a/arch/arm/mach-mx37/cpu.c b/arch/arm/mach-mx37/cpu.c
index 3832473f781e..3729ac11ca80 100644
--- a/arch/arm/mach-mx37/cpu.c
+++ b/arch/arm/mach-mx37/cpu.c
@@ -25,7 +25,6 @@
 #include <asm/hardware/cache-l2x0.h>
 
 void __iomem *gpc_base;
-void __iomem *ccm_base;
 
 /*!
  * CPU initialization. It is called by fixup_mxc_board()
@@ -74,7 +73,6 @@ static int __init post_cpu_init(void)
 	iram_init(IRAM_BASE_ADDR, iram_size);
 
 	gpc_base = ioremap(GPC_BASE_ADDR, SZ_4K);
-	ccm_base = ioremap(CCM_BASE_ADDR, SZ_4K);
 
 	/* Set ALP bits to 000. Set ALP_EN bit in Arm Memory Controller reg. */
 	reg = __raw_readl(MXC_ARM1176_BASE + 0x1C);
diff --git a/arch/arm/mach-mx37/crm_regs.h b/arch/arm/mach-mx37/crm_regs.h
index bfb9bff13d46..607e7cfd5bdf 100644
--- a/arch/arm/mach-mx37/crm_regs.h
+++ b/arch/arm/mach-mx37/crm_regs.h
@@ -502,11 +502,6 @@
 #define MXC_CCM_CCGR5_CG1_OFFSET			2
 #define MXC_CCM_CCGR5_CG0_OFFSET			0
 
-/* CCM Register Offsets. */
-#define MXC_CCM_CDCR_OFFSET		0x6C
-#define MXC_CCM_CACRR_OFFSET		0x10
-#define MXC_CCM_CDHIPR_OFFSET	0x68
-
 #define MXC_ARM1176_BASE	IO_ADDRESS(ARM1176_BASE_ADDR)
 #define MXC_GPC_BASE		IO_ADDRESS(GPC_BASE_ADDR)
 #define MXC_DPTC_LP_BASE	IO_ADDRESS(GPC_BASE_ADDR + 0x80)
@@ -535,11 +530,6 @@
 #define MXC_GPC_PGR		(MXC_GPC_BASE + 0x4)
 #define MXC_GPC_VCR			(MXC_GPC_BASE + 0x8)
 
-/*GPC OFFSETS */
-#define MXC_GPC_CNTR_OFFSET		0x0
-#define MXC_GPC_PGR_OFFSET		0x4
-#define MXC_GPC_VCR_OFFSET		0x8
-
 /* DVFS CORE */
 #define MXC_DVFSTHRS		(MXC_DVFS_CORE_BASE + 0x00)
 #define MXC_DVFSCOUN		(MXC_DVFS_CORE_BASE + 0x04)
diff --git a/arch/arm/mach-mx37/devices.c b/arch/arm/mach-mx37/devices.c
index ce1f33112396..fd4011b36c31 100644
--- a/arch/arm/mach-mx37/devices.c
+++ b/arch/arm/mach-mx37/devices.c
@@ -661,11 +661,11 @@ struct mxc_dvfs_platform_data dvfs_core_data = {
 	.reg_id = "SW1",
 	.clk1_id = "cpu_clk",
 	.clk2_id = "gpc_dvfs_clk",
-	.gpc_cntr_offset = MXC_GPC_CNTR_OFFSET,
-	.gpc_vcr_offset = MXC_GPC_VCR_OFFSET,
-	.ccm_cdcr_offset = MXC_CCM_CDCR_OFFSET,
-	.ccm_cacrr_offset = MXC_CCM_CACRR_OFFSET,
-	.ccm_cdhipr_offset = MXC_CCM_CDHIPR_OFFSET,
+	.gpc_cntr_reg_addr = MXC_GPC_CNTR,
+	.gpc_vcr_reg_addr = MXC_GPC_VCR,
+	.ccm_cdcr_reg_addr = MXC_CCM_CDCR,
+	.ccm_cacrr_reg_addr = MXC_CCM_CACRR,
+	.ccm_cdhipr_reg_addr = MXC_CCM_CDHIPR,
 	.prediv_mask = 0x3800,
 	.prediv_offset = 11,
 	.prediv_val = 1,
@@ -1168,22 +1168,6 @@ static inline void mxc_init_ssi(void)
 }
 #endif /* CONFIG_SND_MXC_SOC_SSI */
 
-static struct platform_device mxc_v4l2_device = {
-	.name = "mxc_v4l2_capture",
-	.id = 0,
-};
-
-static struct platform_device mxc_v4l2out_device = {
-	.name = "mxc_v4l2_output",
-	.id = 0,
-};
-
-static inline void mxc_init_v4l2()
-{
-	platform_device_register(&mxc_v4l2_device);
-	platform_device_register(&mxc_v4l2out_device);
-}
-
 int __init mxc_init_devices(void)
 {
 	mxc_init_wdt();
@@ -1205,7 +1189,6 @@ int __init mxc_init_devices(void)
 	mxc_init_rngc();
 	mxc_init_iim();
 	mxc_init_ssi();
-	mxc_init_v4l2();
 
 	return 0;
 }
diff --git a/arch/arm/mach-mx37/usb_dr.c b/arch/arm/mach-mx37/usb_dr.c
index eb7fc463526c..c8cbed1cc2d4 100644
--- a/arch/arm/mach-mx37/usb_dr.c
+++ b/arch/arm/mach-mx37/usb_dr.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved.
  */
 
 /*
@@ -43,7 +43,7 @@ static struct fsl_usb2_platform_data __maybe_unused dr_utmi_config = {
 
 
 /*
- * OTG resources
+ * resources
  */
 static struct resource otg_resources[] = {
 	[0] = {
@@ -57,20 +57,7 @@ static struct resource otg_resources[] = {
 	},
 };
 
-/*
- * UDC resources (same as OTG resource)
- */
-static struct resource udc_resources[] = {
-	[0] = {
-		.start = (u32)(OTG_BASE_ADDR),
-		.end   = (u32)(OTG_BASE_ADDR + 0x620),
-		.flags = IORESOURCE_MEM,
-	},
-	[1] = {
-		.start = MXC_INT_USB_OTG,
-		.flags = IORESOURCE_IRQ,
-	},
-};
+
 static u64 dr_udc_dmamask = ~(u32) 0;
 static void dr_udc_release(struct device *dev)
 {
@@ -88,8 +75,8 @@ static struct platform_device dr_udc_device = {
 		.dma_mask          = &dr_udc_dmamask,
 		.coherent_dma_mask = 0xffffffff,
 	},
-	.resource      = udc_resources,
-	.num_resources = ARRAY_SIZE(udc_resources),
+	.resource      = otg_resources,
+	.num_resources = ARRAY_SIZE(otg_resources),
 };
 
 static u64 dr_otg_dmamask = ~(u32) 0;
diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig
index 7152e3c0f34f..c45880ff8521 100644
--- a/arch/arm/mach-mx5/Kconfig
+++ b/arch/arm/mach-mx5/Kconfig
@@ -2,14 +2,12 @@ if ARCH_MX5
 
 config ARCH_MX51
 	bool "MX51"
-	select ARCH_MXC_IOMUX_V3
 
 config ARCH_MX53
 	bool "MX53"
 
 config ARCH_MX50
        bool
-	   select ARCH_HAS_RNGC
 
 config FORCE_MAX_ZONEORDER
     int "MAX_ORDER"
@@ -63,14 +61,6 @@ config MODULE_CCXMX51
 config LATE_CPU_CLK_ENABLE
 	bool
 
-config MACH_MX50_RDP
-	bool "Support MX50 Reference Design Platform"
-	select ARCH_MX50
-	help
-	  Include support for MX50 RDP platform. This includes specific
-	  configurations for the board and its peripherals.
-
-
 config MACH_CCWMX51JS
 	bool "Support for the ConnectCore Wi-i.MX51 module, on the JSK base board"
 	select MODULE_CCXMX51
diff --git a/arch/arm/mach-mx5/Makefile b/arch/arm/mach-mx5/Makefile
index 90baa14638fe..34d8ae473789 100644
--- a/arch/arm/mach-mx5/Makefile
+++ b/arch/arm/mach-mx5/Makefile
@@ -5,20 +5,16 @@
 # Object file lists.
 
 obj-y   := system.o iomux.o cpu.o mm.o devices.o serial.o dma.o lpmodes.o pm.o \
-sdram_autogating.o bus_freq.o usb_dr.o usb_h1.o usb_h2.o dummy_gpio.o early_setup.o
+sdram_autogating.o bus_freq.o usb_dr.o usb_h1.o usb_h2.o dummy_gpio.o wfi.o suspend.o early_setup.o
 
--obj-$(CONFIG_ARCH_MX51) += clock.o
--obj-$(CONFIG_ARCH_MX53) += clock.o
--obj-$(CONFIG_ARCH_MX50) += clock_mx50.o
-obj-$(CONFIG_ARCH_MX51) += clock.o suspend.o
-obj-$(CONFIG_ARCH_MX53) += clock.o suspend.o
-obj-$(CONFIG_ARCH_MX50) += clock_mx50.o dmaengine.o dma-apbh.o mx50_suspend.o mx50_ddr_freq.o mx50_wfi.o
+obj-$(CONFIG_ARCH_MX51) += clock.o
+obj-$(CONFIG_ARCH_MX53) += clock.o
+obj-$(CONFIG_ARCH_MX50) += clock_mx50.o
 
 obj-$(CONFIG_MACH_MX51_3DS) += mx51_3stack.o mx51_3stack_gpio.o mx51_3stack_pmic_mc13892.o
-obj-$(CONFIG_MACH_MX51_BABBAGE) += mx51_babbage.o mx51_babbage_pmic_mc13892.o
-obj-$(CONFIG_MACH_MX53_EVK) += mx53_evk.o mx53_evk_pmic_mc13892.o
-obj-$(CONFIG_MACH_MX50_ARM2) += mx50_arm2.o mx50_arm2_pmic_mc13892.o
+obj-$(CONFIG_MACH_MX51_BABBAGE) += mx51_babbage.o mx51_babbage_gpio.o mx51_babbage_pmic_mc13892.o
+obj-$(CONFIG_MACH_MX53_EVK) += mx53_evk.o mx53_evk_gpio.o mx53_evk_pmic_mc13892.o
+obj-$(CONFIG_MACH_MX50_ARM2) += mx50_arm2.o mx50_arm2_gpio.o mx50_arm2_pmic_mc13892.o
 obj-$(CONFIG_MACH_CCWMX51JS) += devices_ccwmx51.o mx51_ccwmx51js.o mx51_ccwmx51js_gpio.o
 obj-$(CONFIG_MACH_CCMX51JS) += devices_ccwmx51.o mx51_ccwmx51js.o mx51_ccwmx51js_gpio.o
 obj-$(CONFIG_MXC_PMIC_MC13892) +=  mx51_ccwmx51js_pmic_mc13892.o
-obj-$(CONFIG_MACH_MX50_RDP) += mx50_rdp.o mx50_rdp_pmic_mc13892.o
diff --git a/arch/arm/mach-mx5/bus_freq.c b/arch/arm/mach-mx5/bus_freq.c
index ec2addfd977b..4fcaf95e3019 100644
--- a/arch/arm/mach-mx5/bus_freq.c
+++ b/arch/arm/mach-mx5/bus_freq.c
@@ -27,19 +27,12 @@
 #include <linux/delay.h>
 #include <linux/platform_device.h>
 #include <linux/regulator/consumer.h>
-#include <linux/iram_alloc.h>
-#include <linux/mutex.h>
 #include <mach/hardware.h>
 #include <mach/clock.h>
 #include <mach/mxc_dvfs.h>
 #include <mach/sdram_autogating.h>
-#include <asm/mach/map.h>
-#include <asm/cacheflush.h>
-#include <asm/tlb.h>
 #include "crm_regs.h"
 
-#define LP_LOW_VOLTAGE		1050000
-#define LP_NORMAL_VOLTAGE		1250000
 #define LP_APM_CLK   			24000000
 #define NAND_LP_APM_CLK			12000000
 #define AXI_A_NORMAL_CLK		166250000
@@ -48,9 +41,6 @@
 #define AHB_CLK_NORMAL_DIV		AXI_B_CLK_NORMAL_DIV
 #define EMI_SLOW_CLK_NORMAL_DIV		AXI_B_CLK_NORMAL_DIV
 #define NFC_CLK_NORMAL_DIV      	4
-#define SPIN_DELAY	1000000 /* in nanoseconds */
-
-DEFINE_SPINLOCK(ddr_freq_lock);
 
 static unsigned long lp_normal_rate;
 static unsigned long lp_med_rate;
@@ -59,24 +49,25 @@ static unsigned long ddr_low_rate;
 
 static struct clk *ddr_clk;
 static struct clk *pll1_sw_clk;
-static struct clk *pll1;
 static struct clk *pll2;
 static struct clk *pll3;
-static struct clk *pll4;
 static struct clk *main_bus_clk;
 static struct clk *axi_a_clk;
 static struct clk *axi_b_clk;
 static struct clk *cpu_clk;
 static struct clk *ddr_hf_clk;
+static struct clk *nfc_clk;
 static struct clk *ahb_clk;
+static struct clk *vpu_clk;
+static struct clk *vpu_core_clk;
+static struct clk *emi_slow_clk;
 static struct clk *ddr_clk;
+static struct clk *ipu_clk;
 static struct clk *periph_apm_clk;
 static struct clk *lp_apm;
 static struct clk *osc;
 static struct clk *gpc_dvfs_clk;
 static struct clk *emi_garb_clk;
-static void __iomem *pll1_base;
-static void __iomem *pll4_base;
 
 struct regulator *lp_regulator;
 int low_bus_freq_mode;
@@ -88,7 +79,6 @@ char *lp_reg_id = "SW2";
 static struct cpu_wp *cpu_wp_tbl;
 static struct device *busfreq_dev;
 static int busfreq_suspended;
-static int cpu_podf;
 /* True if bus_frequency is scaled not using DVFS-PER */
 int bus_freq_scaling_is_active;
 
@@ -96,20 +86,8 @@ int cpu_wp_nr;
 int lp_high_freq;
 int lp_med_freq;
 
-void enter_lpapm_mode_mx50(void);
-void enter_lpapm_mode_mx51(void);
-void exit_lpapm_mode_mx50(void);
-void exit_lpapm_mode_mx51(void);
-void *ddr_freq_change_iram_base;
-void (*change_ddr_freq)(void *ccm_addr, void *databahn_addr, u32 freq) = NULL;
-
-extern void mx50_ddr_freq_change(u32 ccm_base,
-					u32 databahn_addr, u32 freq);
 extern int dvfs_core_is_active;
 extern struct cpu_wp *(*get_cpu_wp)(int *wp);
-extern void propagate_rate(struct clk *tclk);
-extern void __iomem *ccm_base;
-extern void __iomem *databahn_base;
 
 struct dvfs_wp dvfs_core_setpoint[] = {
 						{33, 8, 33, 10, 10, 0x08},
@@ -120,198 +98,75 @@ struct dvfs_wp dvfs_core_setpoint[] = {
 int set_low_bus_freq(void)
 {
 	u32 reg;
-	struct timespec nstimeofday;
-	struct timespec curtime;
 
 	if (busfreq_suspended)
 		return 0;
 
 	if (bus_freq_scaling_initialized) {
 		/* can not enter low bus freq, when cpu is in highest freq */
-		if (clk_get_rate(cpu_clk) !=
-				cpu_wp_tbl[cpu_wp_nr - 1].cpu_rate) {
+		if (clk_get_rate(cpu_clk) != cpu_wp_tbl[cpu_wp_nr - 1].cpu_rate)
+			return 0;
+
+		/* currently not support on mx53 */
+		if (cpu_is_mx53())
 			return 0;
-		}
 
 		stop_dvfs_per();
 
 		stop_sdram_autogating();
+		/*Change the DDR freq to 133Mhz. */
+		clk_set_rate(ddr_hf_clk,
+		     clk_round_rate(ddr_hf_clk, ddr_low_rate));
+
 		/* Set PLL3 to 133Mhz if no-one is using it. */
-		if ((clk_get_usecount(pll3) == 0) && !cpu_is_mx53()) {
+		if (clk_get_usecount(pll3) == 0) {
 			u32 pll3_rate = clk_get_rate(pll3);
 
 			clk_enable(pll3);
 			clk_set_rate(pll3, clk_round_rate(pll3, 133000000));
-			if (cpu_is_mx50())
-				enter_lpapm_mode_mx50();
-			else
-				enter_lpapm_mode_mx51();
-
-			/* Set PLL3 back to original rate. */
-			clk_set_rate(pll3, clk_round_rate(pll3, pll3_rate));
-			clk_disable(pll3);
-
-		} else if (cpu_is_mx53()) {
-			/*Change the DDR freq to 133Mhz. */
-			clk_set_rate(ddr_hf_clk,
-			     clk_round_rate(ddr_hf_clk, ddr_low_rate));
-
-			/* move cpu clk to pll2, 400 / 3 = 133Mhz for cpu  */
-			clk_set_parent(pll1_sw_clk, pll2);
-
-			cpu_podf = __raw_readl(MXC_CCM_CACRR);
-			reg = __raw_readl(MXC_CCM_CDHIPR);
-			if ((reg & MXC_CCM_CDHIPR_ARM_PODF_BUSY) == 0)
-				__raw_writel(0x2, MXC_CCM_CACRR);
-			else
-				printk(KERN_DEBUG "ARM_PODF still in busy!!!!\n");
-
-			/* ahb = 400/8, axi_b = 400/8, axi_a = 133*/
+			/* Set the parent of Periph_apm_clk to be PLL3 */
+			clk_set_parent(periph_apm_clk, pll3);
+			clk_set_parent(main_bus_clk, periph_apm_clk);
+
+			/* Set the AHB dividers to be 1. */
+			/* Set the dividers to be  1, so the clock rates
+			  * are at 133MHz.
+			  */
 			reg = __raw_readl(MXC_CCM_CBCDR);
 			reg &= ~(MXC_CCM_CBCDR_AXI_A_PODF_MASK
-				| MXC_CCM_CBCDR_AXI_B_PODF_MASK
-				| MXC_CCM_CBCDR_AHB_PODF_MASK);
-			reg |= (2 << MXC_CCM_CBCDR_AXI_A_PODF_OFFSET
-				| 7 << MXC_CCM_CBCDR_AXI_B_PODF_OFFSET
-				| 7 << MXC_CCM_CBCDR_AHB_PODF_OFFSET);
+					| MXC_CCM_CBCDR_AXI_B_PODF_MASK
+					| MXC_CCM_CBCDR_AHB_PODF_MASK
+					| MXC_CCM_CBCDR_EMI_PODF_MASK
+					| MXC_CCM_CBCDR_NFC_PODF_OFFSET);
+			reg |= (0 << MXC_CCM_CBCDR_AXI_A_PODF_OFFSET
+					| 0 << MXC_CCM_CBCDR_AXI_B_PODF_OFFSET
+					| 0 << MXC_CCM_CBCDR_AHB_PODF_OFFSET
+					| 0 << MXC_CCM_CBCDR_EMI_PODF_OFFSET
+					| 3 << MXC_CCM_CBCDR_NFC_PODF_OFFSET);
 			__raw_writel(reg, MXC_CCM_CBCDR);
 
-			getnstimeofday(&nstimeofday);
-			while (__raw_readl(MXC_CCM_CDHIPR) &
-					(MXC_CCM_CDHIPR_AXI_A_PODF_BUSY |
-					 MXC_CCM_CDHIPR_AXI_B_PODF_BUSY |
-					 MXC_CCM_CDHIPR_AHB_PODF_BUSY)) {
-					getnstimeofday(&curtime);
-				if (curtime.tv_nsec - nstimeofday.tv_nsec
-					       > SPIN_DELAY)
-					panic("low bus freq set rate error\n");
-			}
+			clk_enable(emi_garb_clk);
+			while (__raw_readl(MXC_CCM_CDHIPR) & 0x1F)
+				udelay(10);
+			clk_disable(emi_garb_clk);
 
-			/* keep this infront of propagating */
-			low_bus_freq_mode = 1;
-			high_bus_freq_mode = 0;
+			/* Set the source of Periph_APM_Clock to be lp-apm. */
+			clk_set_parent(periph_apm_clk, lp_apm);
 
-			propagate_rate(main_bus_clk);
-			propagate_rate(pll1_sw_clk);
+			/* Set PLL3 back to original rate. */
+			clk_set_rate(pll3, clk_round_rate(pll3, pll3_rate));
+			clk_disable(pll3);
 
-			if (clk_get_usecount(pll1) == 0) {
-				reg = __raw_readl(pll1_base + MXC_PLL_DP_CTL);
-				reg &= ~MXC_PLL_DP_CTL_UPEN;
-				__raw_writel(reg, pll1_base + MXC_PLL_DP_CTL);
-			}
-			if (clk_get_usecount(pll4) == 0) {
-				reg = __raw_readl(pll4_base + MXC_PLL_DP_CTL);
-				reg &= ~MXC_PLL_DP_CTL_UPEN;
-				__raw_writel(reg, pll4_base + MXC_PLL_DP_CTL);
-			}
+			low_bus_freq_mode = 1;
+			high_bus_freq_mode = 0;
 		}
 	}
 	return 0;
 }
 
-void enter_lpapm_mode_mx50()
-{
-	u32 reg;
-	unsigned long flags;
-
-	spin_lock_irqsave(&ddr_freq_lock, flags);
-
-	/* Set the parent of main_bus_clk to be PLL3 */
-	clk_set_parent(main_bus_clk, pll3);
-
-	/* Set the AHB dividers to be 1. */
-	/* Set the dividers to be  1, so the clock rates
-	 * are at 133MHz.
-	 */
-	reg = __raw_readl(MXC_CCM_CBCDR);
-	reg &= ~(MXC_CCM_CBCDR_AXI_A_PODF_MASK
-			| MXC_CCM_CBCDR_AXI_B_PODF_MASK
-			| MXC_CCM_CBCDR_AHB_PODF_MASK
-			| MX50_CCM_CBCDR_WEIM_PODF_MASK);
-	reg |= (0 << MXC_CCM_CBCDR_AXI_A_PODF_OFFSET
-			| 0 << MXC_CCM_CBCDR_AXI_B_PODF_OFFSET
-			| 0 << MXC_CCM_CBCDR_AHB_PODF_OFFSET
-			| 0 << MX50_CCM_CBCDR_WEIM_PODF_OFFSET);
-	__raw_writel(reg, MXC_CCM_CBCDR);
-	while (__raw_readl(MXC_CCM_CDHIPR) & 0x0F)
-		udelay(10);
-	low_bus_freq_mode = 1;
-	high_bus_freq_mode = 0;
-
-	/* Set the source of main_bus_clk to be lp-apm. */
-	clk_set_parent(main_bus_clk, lp_apm);
-
-	/* Set SYS_CLK to 24MHz. sourced from XTAL*/
-	/* Turn on the XTAL_CLK_GATE. */
-	reg = __raw_readl(MXC_CCM_CLK_SYS);
-	reg |= 3 << MXC_CCM_CLK_SYS_SYS_XTAL_CLKGATE_OFFSET;
-	__raw_writel(reg, MXC_CCM_CLK_SYS);
-
-	/* Set the divider. */
-	reg = __raw_readl(MXC_CCM_CLK_SYS);
-	reg &= ~MXC_CCM_CLK_SYS_DIV_XTAL_MASK;
-	reg |= 1 << MXC_CCM_CLK_SYS_DIV_XTAL_OFFSET;
-	__raw_writel(reg, MXC_CCM_CLK_SYS);
-	while (__raw_readl(MXC_CCM_CSR2) & 0x1)
-		udelay(10);
-
-	/* Set the source to be XTAL. */
-	reg = __raw_readl(MXC_CCM_CLKSEQ_BYPASS);
-	reg &= ~0x1;
-	__raw_writel(reg, MXC_CCM_CLKSEQ_BYPASS);
-	while (!(__raw_readl(MXC_CCM_CSR2) & 0x400))
-		udelay(10);
-
-	/* Turn OFF the PLL_CLK_GATE. */
-	reg = __raw_readl(MXC_CCM_CLK_SYS);
-	reg &= ~MXC_CCM_CLK_SYS_SYS_PLL_CLKGATE_MASK;
-	__raw_writel(reg, MXC_CCM_CLK_SYS);
-	spin_unlock_irqrestore(&ddr_freq_lock, flags);
-
-}
-
-void enter_lpapm_mode_mx51()
-{
-	u32 reg;
-
-	/*Change the DDR freq to 133Mhz. */
-	clk_set_rate(ddr_hf_clk,
-	     clk_round_rate(ddr_hf_clk, ddr_low_rate));
-
-	/* Set the parent of Periph_apm_clk to be PLL3 */
-	clk_set_parent(periph_apm_clk, pll3);
-	clk_set_parent(main_bus_clk, periph_apm_clk);
-
-	/* Set the dividers to be  1, so the clock rates
-	  * are at 133MHz.
-	  */
-	reg = __raw_readl(MXC_CCM_CBCDR);
-	reg &= ~(MXC_CCM_CBCDR_AXI_A_PODF_MASK
-			| MXC_CCM_CBCDR_AXI_B_PODF_MASK
-			| MXC_CCM_CBCDR_AHB_PODF_MASK
-			| MXC_CCM_CBCDR_EMI_PODF_MASK
-			| MXC_CCM_CBCDR_NFC_PODF_OFFSET);
-	reg |= (0 << MXC_CCM_CBCDR_AXI_A_PODF_OFFSET
-			| 0 << MXC_CCM_CBCDR_AXI_B_PODF_OFFSET
-			| 0 << MXC_CCM_CBCDR_AHB_PODF_OFFSET
-			| 0 << MXC_CCM_CBCDR_EMI_PODF_OFFSET
-			| 3 << MXC_CCM_CBCDR_NFC_PODF_OFFSET);
-	__raw_writel(reg, MXC_CCM_CBCDR);
-
-	clk_enable(emi_garb_clk);
-	while (__raw_readl(MXC_CCM_CDHIPR) & 0x1F)
-		udelay(10);
-	clk_disable(emi_garb_clk);
-
-	/* Set the source of Periph_APM_Clock to be lp-apm. */
-	clk_set_parent(periph_apm_clk, lp_apm);
-}
-
 int set_high_bus_freq(int high_bus_freq)
 {
 	u32 reg;
-	struct timespec nstimeofday;
-	struct timespec curtime;
 
 	if (bus_freq_scaling_initialized) {
 
@@ -319,65 +174,48 @@ int set_high_bus_freq(int high_bus_freq)
 
 		if (low_bus_freq_mode) {
 			/* Relock PLL3 to 133MHz */
-			if ((clk_get_usecount(pll3) == 0) && !cpu_is_mx53()) {
+			if (clk_get_usecount(pll3) == 0) {
 				u32 pll3_rate = clk_get_rate(pll3);
 
 				clk_enable(pll3);
 				clk_set_rate(pll3,
 					clk_round_rate(pll3, 133000000));
-				if (cpu_is_mx50())
-					exit_lpapm_mode_mx50();
-				else
-					exit_lpapm_mode_mx51();
-
-				/* Relock PLL3 to its original rate */
-				clk_set_rate(pll3,
-					clk_round_rate(pll3, pll3_rate));
-				clk_disable(pll3);
-			} else if (cpu_is_mx53()) {
-				/* move cpu clk to pll1 */
-				reg = __raw_readl(MXC_CCM_CDHIPR);
-				if ((reg & MXC_CCM_CDHIPR_ARM_PODF_BUSY) == 0)
-					__raw_writel(cpu_podf & 0x7,
-							MXC_CCM_CACRR);
-				else
-					printk(KERN_DEBUG
-						"ARM_PODF still in busy!!!!\n");
-
-				clk_set_parent(pll1_sw_clk, pll1);
-
-				/* ahb = 400/3, axi_b = 400/3, axi_a = 400*/
+				clk_set_parent(periph_apm_clk, pll3);
+				/* Set the dividers to the default dividers */
 				reg = __raw_readl(MXC_CCM_CBCDR);
 				reg &= ~(MXC_CCM_CBCDR_AXI_A_PODF_MASK
 					| MXC_CCM_CBCDR_AXI_B_PODF_MASK
-					| MXC_CCM_CBCDR_AHB_PODF_MASK);
-				reg |= (0 << MXC_CCM_CBCDR_AXI_A_PODF_OFFSET
-					| 2 << MXC_CCM_CBCDR_AXI_B_PODF_OFFSET
-					| 2 << MXC_CCM_CBCDR_AHB_PODF_OFFSET);
+					| MXC_CCM_CBCDR_AHB_PODF_MASK
+					| MXC_CCM_CBCDR_EMI_PODF_MASK
+					| MXC_CCM_CBCDR_NFC_PODF_OFFSET);
+				reg |= (3 << MXC_CCM_CBCDR_AXI_A_PODF_OFFSET
+					| 4 << MXC_CCM_CBCDR_AXI_B_PODF_OFFSET
+					| 4 << MXC_CCM_CBCDR_AHB_PODF_OFFSET
+					| 4 << MXC_CCM_CBCDR_EMI_PODF_OFFSET
+					| 3 << MXC_CCM_CBCDR_NFC_PODF_OFFSET);
 				__raw_writel(reg, MXC_CCM_CBCDR);
 
-				getnstimeofday(&nstimeofday);
-				while (__raw_readl(MXC_CCM_CDHIPR) &
-					(MXC_CCM_CDHIPR_AXI_A_PODF_BUSY |
-					 MXC_CCM_CDHIPR_AXI_B_PODF_BUSY |
-					 MXC_CCM_CDHIPR_AHB_PODF_BUSY)) {
-						getnstimeofday(&curtime);
-					if (curtime.tv_nsec
-						- nstimeofday.tv_nsec
-						> SPIN_DELAY)
-						panic("bus freq error\n");
-				}
-
-				/* keep this infront of propagating */
-				low_bus_freq_mode = 1;
-				high_bus_freq_mode = 0;
+				clk_enable(emi_garb_clk);
+				while (__raw_readl(MXC_CCM_CDHIPR) & 0x1F)
+					udelay(10);
 
-				propagate_rate(main_bus_clk);
-				propagate_rate(pll1_sw_clk);
-				/*Change the DDR freq to mormal_rate*/
-				clk_set_rate(ddr_hf_clk,
-					clk_round_rate(ddr_hf_clk, ddr_normal_rate));
+				low_bus_freq_mode = 0;
+				high_bus_freq_mode = 1;
+				clk_disable(emi_garb_clk);
+
+				/*Set the main_bus_clk parent to be PLL2. */
+				clk_set_parent(main_bus_clk, pll2);
+
+				/* Relock PLL3 to its original rate */
+				clk_set_rate(pll3,
+					clk_round_rate(pll3, pll3_rate));
+				clk_disable(pll3);
 			}
+
+			/*Change the DDR freq to 200MHz*/
+			clk_set_rate(ddr_hf_clk,
+			    clk_round_rate(ddr_hf_clk, ddr_normal_rate));
+
 			start_dvfs_per();
 		}
 		if (bus_freq_scaling_is_active) {
@@ -418,105 +256,11 @@ int set_high_bus_freq(int high_bus_freq)
 	return 0;
 }
 
-void exit_lpapm_mode_mx50()
-{
-	u32 reg;
-	unsigned long flags;
-
-	spin_lock_irqsave(&ddr_freq_lock, flags);
-
-	/* Set SYS_CLK to source from PLL1 */
-	/* Set sys_clk back to 200MHz. */
-	/* Set the divider to 4. */
-	reg = __raw_readl(MXC_CCM_CLK_SYS);
-	reg &= ~MXC_CCM_CLK_SYS_DIV_PLL_MASK;
-	reg |= 0x4 << MXC_CCM_CLK_SYS_DIV_PLL_OFFSET;
-	__raw_writel(reg, MXC_CCM_CLK_SYS);
-	udelay(100);
-
-	/* Turn ON the PLL CLK_GATE. */
-	reg = __raw_readl(MXC_CCM_CLK_SYS);
-	reg |= 3 << MXC_CCM_CLK_SYS_SYS_PLL_CLKGATE_OFFSET;
-	__raw_writel(reg, MXC_CCM_CLK_SYS);
-
-	/* Source the SYS_CLK from PLL */
-	reg = __raw_readl(MXC_CCM_CLKSEQ_BYPASS);
-	reg |= 0x3;
-	__raw_writel(reg, MXC_CCM_CLKSEQ_BYPASS);
-	while (__raw_readl(MXC_CCM_CSR2) & 0x400)
-		udelay(10);
-
-	/* Turn OFF the XTAL_CLK_GATE. */
-	reg = __raw_readl(MXC_CCM_CLK_SYS);
-	reg &= ~MXC_CCM_CLK_SYS_SYS_XTAL_CLKGATE_MASK;
-	__raw_writel(reg, MXC_CCM_CLK_SYS);
-
-	clk_set_parent(main_bus_clk, pll3);
-
-	/* Set the dividers to the default dividers */
-	reg = __raw_readl(MXC_CCM_CBCDR);
-	reg &= ~(MXC_CCM_CBCDR_AXI_A_PODF_MASK
-		| MXC_CCM_CBCDR_AXI_B_PODF_MASK
-		| MXC_CCM_CBCDR_AHB_PODF_MASK
-		| MX50_CCM_CBCDR_WEIM_PODF_MASK);
-	reg |= (0 << MXC_CCM_CBCDR_AXI_A_PODF_OFFSET
-		|1 << MXC_CCM_CBCDR_AXI_B_PODF_OFFSET
-		|2 << MXC_CCM_CBCDR_AHB_PODF_OFFSET
-		|0 << MX50_CCM_CBCDR_WEIM_PODF_OFFSET);
-	__raw_writel(reg, MXC_CCM_CBCDR);
-
-	while (__raw_readl(MXC_CCM_CDHIPR) & 0xF)
-		udelay(10);
-
-	low_bus_freq_mode = 0;
-	high_bus_freq_mode = 1;
-
-	/*Set the main_bus_clk parent to be PLL2. */
-	clk_set_parent(main_bus_clk, pll2);
-	spin_unlock_irqrestore(&ddr_freq_lock, flags);
-
-	udelay(100);
-}
-
-void exit_lpapm_mode_mx51()
-{
-	u32 reg;
-
-	clk_set_parent(periph_apm_clk, pll3);
-
-	/* Set the dividers to the default dividers */
-	reg = __raw_readl(MXC_CCM_CBCDR);
-	reg &= ~(MXC_CCM_CBCDR_AXI_A_PODF_MASK
-		| MXC_CCM_CBCDR_AXI_B_PODF_MASK
-		| MXC_CCM_CBCDR_AHB_PODF_MASK
-		| MXC_CCM_CBCDR_EMI_PODF_MASK
-		| MXC_CCM_CBCDR_NFC_PODF_OFFSET);
-	reg |= (3 << MXC_CCM_CBCDR_AXI_A_PODF_OFFSET
-		| 4 << MXC_CCM_CBCDR_AXI_B_PODF_OFFSET
-		| 4 << MXC_CCM_CBCDR_AHB_PODF_OFFSET
-		| 4 << MXC_CCM_CBCDR_EMI_PODF_OFFSET
-		| 3 << MXC_CCM_CBCDR_NFC_PODF_OFFSET);
-	__raw_writel(reg, MXC_CCM_CBCDR);
-
-	clk_enable(emi_garb_clk);
-	while (__raw_readl(MXC_CCM_CDHIPR) & 0x1F)
-		udelay(10);
-
-	low_bus_freq_mode = 0;
-	high_bus_freq_mode = 1;
-	clk_disable(emi_garb_clk);
-
-	/*Set the main_bus_clk parent to be PLL2. */
-	clk_set_parent(main_bus_clk, pll2);
-
-	/*Change the DDR freq to 200MHz*/
-	clk_set_rate(ddr_hf_clk,
-	    clk_round_rate(ddr_hf_clk, ddr_normal_rate));
-}
-
 int low_freq_bus_used(void)
 {
-	if ((lp_high_freq == 0)
+	if ((clk_get_usecount(ipu_clk) == 0)
+	    && (clk_get_usecount(vpu_clk) == 0)
+	    && (lp_high_freq == 0)
 	    && (lp_med_freq == 0))
 		return 1;
 	else
@@ -542,7 +286,8 @@ static ssize_t bus_freq_scaling_enable_store(struct device *dev,
 {
 	u32 reg;
 
-	if (strncmp(buf, "1", 1) == 0) {
+
+	if (strstr(buf, "1") != NULL) {
 		if (dvfs_per_active()) {
 			printk(KERN_INFO "bus frequency scaling cannot be\
 				 enabled when DVFS-PER is active\n");
@@ -557,12 +302,12 @@ static ssize_t bus_freq_scaling_enable_store(struct device *dev,
 
 		bus_freq_scaling_is_active = 1;
 		set_high_bus_freq(0);
-	} else if (strncmp(buf, "0", 1) == 0) {
+	}
+	else if (strstr(buf, "0") != NULL) {
 		if (bus_freq_scaling_is_active)
 			set_high_bus_freq(1);
 		bus_freq_scaling_is_active = 0;
 	}
-
 	return size;
 }
 
@@ -595,11 +340,6 @@ static int __devinit busfreq_probe(struct platform_device *pdev)
 {
 	int err = 0;
 	unsigned long pll2_rate, pll1_rate;
-	unsigned long iram_paddr;
-
-	pll1_base = ioremap(MX53_BASE_ADDR(PLL1_BASE_ADDR), SZ_4K);
-	if (cpu_is_mx53())
-		pll4_base = ioremap(MX53_BASE_ADDR(PLL4_BASE_ADDR), SZ_4K);
 
 	busfreq_dev = &pdev->dev;
 
@@ -616,32 +356,41 @@ static int __devinit busfreq_probe(struct platform_device *pdev)
 		return PTR_ERR(pll1_sw_clk);
 	}
 
-	pll1 = clk_get(NULL, "pll1_main_clk");
-	if (IS_ERR(pll1)) {
-		printk(KERN_DEBUG "%s: failed to get pll1\n", __func__);
-		return PTR_ERR(pll1);
-	}
-
 	pll2 = clk_get(NULL, "pll2");
 	if (IS_ERR(pll2)) {
 		printk(KERN_DEBUG "%s: failed to get pll2\n", __func__);
 		return PTR_ERR(pll2);
 	}
 
+	pll1_rate = clk_get_rate(pll1_sw_clk);
+	pll2_rate = clk_get_rate(pll2);
+
+	if (pll2_rate == 665000000) {
+		/* for mx51 */
+		lp_normal_rate = pll2_rate / 5;
+		lp_med_rate = pll2_rate / 8;
+		ddr_normal_rate = pll1_rate / 4; /* 200M */
+		ddr_low_rate = pll1_rate / 6; /* 133M */
+	} else if (pll2_rate == 600000000) {
+		/* for mx53 evk rev.A */
+		lp_normal_rate = pll2_rate / 5;
+		lp_med_rate = pll2_rate / 8;
+		ddr_normal_rate = pll2_rate / 2;
+		ddr_low_rate = pll2_rate / 2;
+	} else if (pll2_rate == 400000000) {
+		/* for mx53 evk rev.B */
+		lp_normal_rate = pll2_rate / 3;
+		lp_med_rate = pll2_rate / 5;
+		ddr_normal_rate = pll2_rate / 1;
+		ddr_low_rate = pll2_rate / 3;
+	}
+
 	pll3 = clk_get(NULL, "pll3");
 	if (IS_ERR(pll3)) {
 		printk(KERN_DEBUG "%s: failed to get pll3\n", __func__);
 		return PTR_ERR(pll3);
 	}
 
-	if (cpu_is_mx53()) {
-		pll4 = clk_get(NULL, "pll4");
-		if (IS_ERR(pll4)) {
-			printk(KERN_DEBUG "%s: failed to get pll4\n", __func__);
-			return PTR_ERR(pll4);
-		}
-	}
-
 	axi_a_clk = clk_get(NULL, "axi_a_clk");
 	if (IS_ERR(axi_a_clk)) {
 		printk(KERN_DEBUG "%s: failed to get axi_a_clk\n",
@@ -656,14 +405,10 @@ static int __devinit busfreq_probe(struct platform_device *pdev)
 		return PTR_ERR(axi_b_clk);
 	}
 
-	ddr_clk = clk_get(NULL, "ddr_clk");
-	if (IS_ERR(ddr_clk)) {
-		printk(KERN_DEBUG "%s: failed to get ddr_clk\n",
-		       __func__);
-		return PTR_ERR(ddr_clk);
-	}
-
-	ddr_hf_clk = clk_get_parent(ddr_clk);
+	if (cpu_is_mx51())
+		ddr_hf_clk = clk_get(NULL, "ddr_hf_clk");
+	else
+		ddr_hf_clk = clk_get(NULL, "axi_a_clk");
 
 	if (IS_ERR(ddr_hf_clk)) {
 		printk(KERN_DEBUG "%s: failed to get ddr_hf_clk\n",
@@ -671,6 +416,20 @@ static int __devinit busfreq_probe(struct platform_device *pdev)
 		return PTR_ERR(ddr_hf_clk);
 	}
 
+	emi_slow_clk = clk_get(NULL, "emi_slow_clk");
+	if (IS_ERR(emi_slow_clk)) {
+		printk(KERN_DEBUG "%s: failed to get emi_slow_clk\n",
+		       __func__);
+		return PTR_ERR(emi_slow_clk);
+	}
+
+	nfc_clk = clk_get(NULL, "nfc_clk");
+	if (IS_ERR(nfc_clk)) {
+		printk(KERN_DEBUG "%s: failed to get nfc_clk\n",
+		       __func__);
+		return PTR_ERR(nfc_clk);
+	}
+
 	ahb_clk = clk_get(NULL, "ahb_clk");
 	if (IS_ERR(ahb_clk)) {
 		printk(KERN_DEBUG "%s: failed to get ahb_clk\n",
@@ -678,6 +437,20 @@ static int __devinit busfreq_probe(struct platform_device *pdev)
 		return PTR_ERR(ahb_clk);
 	}
 
+	vpu_core_clk = clk_get(NULL, "vpu_core_clk");
+	if (IS_ERR(vpu_core_clk)) {
+		printk(KERN_DEBUG "%s: failed to get vpu_core_clk\n",
+		       __func__);
+		return PTR_ERR(vpu_core_clk);
+	}
+
+	ddr_clk = clk_get(NULL, "ddr_clk");
+	if (IS_ERR(ddr_clk)) {
+		printk(KERN_DEBUG "%s: failed to get ddr_clk\n",
+		       __func__);
+		return PTR_ERR(ddr_clk);
+	}
+
 	cpu_clk = clk_get(NULL, "cpu_clk");
 	if (IS_ERR(cpu_clk)) {
 		printk(KERN_DEBUG "%s: failed to get cpu_clk\n",
@@ -685,25 +458,35 @@ static int __devinit busfreq_probe(struct platform_device *pdev)
 		return PTR_ERR(cpu_clk);
 	}
 
+	ipu_clk = clk_get(NULL, "ipu_clk");
+	if (IS_ERR(ipu_clk)) {
+		printk(KERN_DEBUG "%s: failed to get ipu_clk\n",
+		       __func__);
+		return PTR_ERR(ipu_clk);
+	}
+
 	if (cpu_is_mx51())
 		emi_garb_clk = clk_get(NULL, "emi_garb_clk");
-	else if (cpu_is_mx53())
-		emi_garb_clk = clk_get(NULL, "emi_intr_clk.1");
 	else
-		emi_garb_clk = clk_get(NULL, "ocram_clk");
+		emi_garb_clk = clk_get(NULL, "emi_intr_clk.1");
 	if (IS_ERR(emi_garb_clk)) {
 		printk(KERN_DEBUG "%s: failed to get emi_garb_clk\n",
 		       __func__);
 		return PTR_ERR(emi_garb_clk);
 	}
 
-	if (cpu_is_mx51()  || cpu_is_mx53()) {
-		periph_apm_clk = clk_get(NULL, "periph_apm_clk");
-		if (IS_ERR(periph_apm_clk)) {
-			printk(KERN_DEBUG "%s: failed to get periph_apm_clk\n",
-			       __func__);
-			return PTR_ERR(periph_apm_clk);
-		}
+	vpu_clk = clk_get(NULL, "vpu_clk");
+	if (IS_ERR(vpu_clk)) {
+		printk(KERN_DEBUG "%s: failed to get vpu_clk\n",
+		       __func__);
+		return PTR_ERR(vpu_clk);
+	}
+
+	periph_apm_clk = clk_get(NULL, "periph_apm_clk");
+	if (IS_ERR(periph_apm_clk)) {
+		printk(KERN_DEBUG "%s: failed to get periph_apm_clk\n",
+		       __func__);
+		return PTR_ERR(periph_apm_clk);
 	}
 
 	lp_apm = clk_get(NULL, "lp_apm");
@@ -732,49 +515,6 @@ static int __devinit busfreq_probe(struct platform_device *pdev)
 		return err;
 	}
 
-	pll1_rate = clk_get_rate(pll1_sw_clk);
-	pll2_rate = clk_get_rate(pll2);
-
-	if (pll2_rate == 665000000) {
-		/* for mx51 */
-		lp_normal_rate = pll2_rate / 5;
-		lp_med_rate = pll2_rate / 8;
-		ddr_normal_rate = pll1_rate / 4; /* 200M */
-		ddr_low_rate = pll1_rate / 6; /* 133M */
-	} else if (pll2_rate == 600000000) {
-		/* for mx53 evk rev.A */
-		lp_normal_rate = pll2_rate / 5;
-		lp_med_rate = pll2_rate / 8;
-		ddr_normal_rate = pll2_rate / 2;
-		ddr_low_rate = pll2_rate / 2;
-	} else if (pll2_rate == 400000000) {
-		/* for mx53 evk rev.B */
-		lp_normal_rate = pll2_rate / 3;
-		lp_med_rate = pll2_rate / 5;
-		if (cpu_is_mx53()) {
-			ddr_normal_rate = pll2_rate / 1;
-			ddr_low_rate = pll2_rate / 3;
-		} else if (cpu_is_mx50()) {
-			ddr_normal_rate = clk_get_rate(ddr_clk);
-			ddr_low_rate = LP_APM_CLK;
-		}
-	}
-	if (cpu_is_mx50()) {
-		iram_alloc(SZ_8K, &iram_paddr);
-		/* Need to remap the area here since we want the memory region
-			 to be executable. */
-		ddr_freq_change_iram_base = __arm_ioremap(iram_paddr,
-							SZ_8K, MT_HIGH_VECTORS);
-		memcpy(ddr_freq_change_iram_base, mx50_ddr_freq_change, SZ_8K);
-		change_ddr_freq = (void *)ddr_freq_change_iram_base;
-
-		lp_regulator = regulator_get(NULL, "SW2");
-		if (IS_ERR(lp_regulator)) {
-			printk(KERN_DEBUG
-			"%s: failed to get lp regulator\n", __func__);
-			return PTR_ERR(lp_regulator);
-		}
-	}
 	cpu_wp_tbl = get_cpu_wp(&cpu_wp_nr);
 	low_bus_freq_mode = 0;
 	high_bus_freq_mode = 1;
diff --git a/arch/arm/mach-mx5/clock.c b/arch/arm/mach-mx5/clock.c
index 5ec89a6570cd..09ea14084278 100644
--- a/arch/arm/mach-mx5/clock.c
+++ b/arch/arm/mach-mx5/clock.c
@@ -405,12 +405,7 @@ static int _clk_pll_enable(struct clk *clk)
 	struct timespec curtime;
 
 	pllbase = _get_pll_base(clk);
-	reg = __raw_readl(pllbase + MXC_PLL_DP_CTL);
-
-	if (reg & MXC_PLL_DP_CTL_UPEN)
-		return 0;
-
-	reg |=  MXC_PLL_DP_CTL_UPEN;
+	reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) | MXC_PLL_DP_CTL_UPEN;
 	__raw_writel(reg, pllbase + MXC_PLL_DP_CTL);
 
 	/* Wait for lock */
@@ -4742,15 +4737,15 @@ int __init mx53_clocks_init(unsigned long ckil, unsigned long osc, unsigned long
 		     1 << MXC_CCM_CCGR5_CG6_OFFSET |
 		     3 << MXC_CCM_CCGR5_CG7_OFFSET |
 		     1 << MXC_CCM_CCGR5_CG8_OFFSET |
-		     1 << MXC_CCM_CCGR5_CG9_OFFSET |
+		     3 << MXC_CCM_CCGR5_CG9_OFFSET |
 		     1 << MXC_CCM_CCGR5_CG10_OFFSET |
 		     3 << MXC_CCM_CCGR5_CG11_OFFSET, MXC_CCM_CCGR5);
 
-	__raw_writel(1 << MXC_CCM_CCGR6_CG0_OFFSET |
+	__raw_writel(3 << MXC_CCM_CCGR6_CG0_OFFSET |
 				3 << MXC_CCM_CCGR6_CG1_OFFSET |
-				1 << MXC_CCM_CCGR6_CG4_OFFSET |
-				1 << MXC_CCM_CCGR6_CG8_OFFSET |
-				1 << MXC_CCM_CCGR6_CG9_OFFSET |
+				3 << MXC_CCM_CCGR6_CG4_OFFSET |
+				3 << MXC_CCM_CCGR6_CG8_OFFSET |
+				3 << MXC_CCM_CCGR6_CG9_OFFSET |
 				3 << MXC_CCM_CCGR6_CG12_OFFSET |
 				3 << MXC_CCM_CCGR6_CG13_OFFSET , MXC_CCM_CCGR6);
 
diff --git a/arch/arm/mach-mx5/clock_mx50.c b/arch/arm/mach-mx5/clock_mx50.c
index a2a3c82fba77..6bd7fd3b96aa 100644
--- a/arch/arm/mach-mx5/clock_mx50.c
+++ b/arch/arm/mach-mx5/clock_mx50.c
@@ -39,18 +39,9 @@ static struct clk pll1_main_clk;
 static struct clk pll1_sw_clk;
 static struct clk pll2_sw_clk;
 static struct clk pll3_sw_clk;
-static struct clk apbh_dma_clk;
-static struct clk apll_clk;
-static struct clk pfd0_clk;
-static struct clk pfd1_clk;
-static struct clk pfd2_clk;
-static struct clk pfd3_clk;
-static struct clk pfd4_clk;
-static struct clk pfd5_clk;
-static struct clk pfd6_clk;
-static struct clk pfd7_clk;
+static struct clk pll4_sw_clk;
 static struct clk lp_apm_clk;
-static struct clk weim_clk[];
+static struct clk weim_clk;
 static struct clk ddr_clk;
 static struct clk axi_a_clk;
 static struct clk axi_b_clk;
@@ -61,30 +52,13 @@ static struct cpu_wp *cpu_wp_tbl;
 static void __iomem *pll1_base;
 static void __iomem *pll2_base;
 static void __iomem *pll3_base;
-static void __iomem *apll_base;
+static void __iomem *pll4_base;
 
 extern int cpu_wp_nr;
 extern int lp_high_freq;
 extern int lp_med_freq;
-void __iomem *databahn;
 
-#define DDR_SYNC_MODE		0x30000
 #define SPIN_DELAY	1000000 /* in nanoseconds */
-#define WAIT(exp, timeout) \
-({ \
-	struct timespec nstimeofday; \
-	struct timespec curtime; \
-	int result = 1; \
-	getnstimeofday(&nstimeofday); \
-	while (!(exp)) { \
-		getnstimeofday(&curtime); \
-		if ((curtime.tv_nsec - nstimeofday.tv_nsec) > (timeout)) { \
-			result = 0; \
-			break; \
-		} \
-	} \
-	result; \
-})
 
 extern int mxc_jtag_enabled;
 extern int uart_at_24;
@@ -249,6 +223,8 @@ static inline void __iomem *_get_pll_base(struct clk *pll)
 		return pll2_base;
 	else if (pll == &pll3_sw_clk)
 		return pll3_base;
+	else if (pll == &pll4_sw_clk)
+		return pll4_base;
 	else
 		BUG();
 
@@ -270,229 +246,48 @@ static struct clk osc_clk = {
 	.flags = RATE_PROPAGATES,
 };
 
-static int apll_enable(struct clk *clk)
-{
-	__raw_writel(1, apll_base + MXC_ANADIG_MISC_SET);
-	return 0;
-}
-
-static void apll_disable(struct clk *clk)
-{
-	__raw_writel(1, apll_base + MXC_ANADIG_MISC_CLR);
-}
-
 static struct clk apll_clk = {
 	.name = "apll",
-	.rate = 480000000,
-	.enable = apll_enable,
-	.disable = apll_disable,
 	.flags = RATE_PROPAGATES,
 };
 
-static void pfd_recalc(struct clk *clk)
-{
-	u32 frac;
-	u64 rate;
-	if (apbh_dma_clk.usecount == 0)
-		apbh_dma_clk.enable(&apbh_dma_clk);
-	frac = __raw_readl(apll_base +
-		(int)clk->enable_reg) >> clk->enable_shift;
-	frac &= MXC_ANADIG_PFD_FRAC_MASK;
-	rate = (u64)clk->parent->rate * 18;
-	do_div(rate, frac);
-	clk->rate = rate;
-	if (apbh_dma_clk.usecount == 0)
-		apbh_dma_clk.disable(&apbh_dma_clk);
-}
-
-static unsigned long pfd_round_rate(struct clk *clk, unsigned long rate)
-{
-	u32 frac;
-	u64 tmp;
-	tmp = (u64)clk->parent->rate * 18;
-	do_div(tmp, rate);
-	frac = tmp;
-	frac = frac < 18 ? 18 : frac;
-	frac = frac > 35 ? 35 : frac;
-	do_div(tmp, frac);
-	return tmp;
-}
-
-static int pfd_set_rate(struct clk *clk, unsigned long rate)
-{
-	u32 frac;
-	u64 tmp;
-
-	if (apbh_dma_clk.usecount == 0)
-		apbh_dma_clk.enable(&apbh_dma_clk);
-	tmp = (u64)clk->parent->rate * 18;
-	do_div(tmp, rate);
-	frac = tmp;
-	frac = frac < 18 ? 18 : frac;
-	frac = frac > 35 ? 35 : frac;
-	/* clear clk frac bits */
-	__raw_writel(MXC_ANADIG_PFD_FRAC_MASK << clk->enable_shift,
-			apll_base + (int)clk->enable_reg + 8);
-	/* set clk frac bits */
-	__raw_writel(frac << clk->enable_shift,
-			apll_base + (int)clk->enable_reg + 4);
-
-	tmp = (u64)clk->parent->rate * 18;
-	do_div(tmp, frac);
-	clk->rate = tmp;
-	if (apbh_dma_clk.usecount == 0)
-		apbh_dma_clk.disable(&apbh_dma_clk);
-	return 0;
-}
-
-static int pfd_enable(struct clk *clk)
-{
-	int index;
-
-	if (apbh_dma_clk.usecount == 0)
-		apbh_dma_clk.enable(&apbh_dma_clk);
-	index = _get_mux8(clk, &pfd0_clk, &pfd1_clk, &pfd2_clk, &pfd3_clk,
-			&pfd4_clk, &pfd5_clk, &pfd6_clk, &pfd7_clk);
-	__raw_writel(1 << (index + MXC_ANADIG_PFD_DIS_OFFSET),
-			apll_base + MXC_ANADIG_PLLCTRL_CLR);
-	/* clear clk gate bit */
-	__raw_writel((1 << (clk->enable_shift + 7)),
-			apll_base + (int)clk->enable_reg + 8);
-
-	/* check lock bit */
-	if (!WAIT(__raw_readl(apll_base + MXC_ANADIG_PLLCTRL)
-		  & MXC_ANADIG_APLL_LOCK, 50000)) {
-		__raw_writel(MXC_ANADIG_APLL_FORCE_LOCK,
-			     apll_base + MXC_ANADIG_PLLCTRL_CLR);
-		__raw_writel(MXC_ANADIG_APLL_FORCE_LOCK,
-			     apll_base + MXC_ANADIG_PLLCTRL_SET);
-		if (!WAIT(__raw_readl(apll_base + MXC_ANADIG_PLLCTRL)
-			  & MXC_ANADIG_APLL_LOCK, SPIN_DELAY))
-			panic("pfd_enable failed!\n");
-	}
-	if (apbh_dma_clk.usecount == 0)
-		apbh_dma_clk.disable(&apbh_dma_clk);
-	return 0;
-}
-
-static void pfd_disable(struct clk *clk)
-{
-	int index;
-
-	if (apbh_dma_clk.usecount == 0)
-		apbh_dma_clk.enable(&apbh_dma_clk);
-	index = _get_mux8(clk, &pfd0_clk, &pfd1_clk, &pfd2_clk, &pfd3_clk,
-			&pfd4_clk, &pfd5_clk, &pfd6_clk, &pfd7_clk);
-	/* set clk gate bit */
-	__raw_writel((1 << (clk->enable_shift + 7)),
-			apll_base + (int)clk->enable_reg + 4);
-	__raw_writel(1 << (index + MXC_ANADIG_PFD_DIS_OFFSET),
-			apll_base + MXC_ANADIG_PLLCTRL_SET);
-	if (apbh_dma_clk.usecount == 0)
-		apbh_dma_clk.disable(&apbh_dma_clk);
-}
-
 static struct clk pfd0_clk = {
 	.name = "pfd0",
-	.parent = &apll_clk,
-	.enable_reg = (void *)MXC_ANADIG_FRAC0,
-	.enable_shift = MXC_ANADIG_PFD0_FRAC_OFFSET,
-	.recalc = pfd_recalc,
-	.set_rate = pfd_set_rate,
-	.round_rate = pfd_round_rate,
-	.enable = pfd_enable,
-	.disable = pfd_disable,
 	.flags = RATE_PROPAGATES,
 };
 
 static struct clk pfd1_clk = {
 	.name = "pfd1",
-	.parent = &apll_clk,
-	.enable_reg = (void *)MXC_ANADIG_FRAC0,
-	.enable_shift = MXC_ANADIG_PFD1_FRAC_OFFSET,
-	.recalc = pfd_recalc,
-	.set_rate = pfd_set_rate,
-	.round_rate = pfd_round_rate,
-	.enable = pfd_enable,
-	.disable = pfd_disable,
 	.flags = RATE_PROPAGATES,
 };
 
 static struct clk pfd2_clk = {
 	.name = "pfd2",
-	.parent = &apll_clk,
-	.enable_reg = (void *)MXC_ANADIG_FRAC0,
-	.enable_shift = MXC_ANADIG_PFD2_FRAC_OFFSET,
-	.recalc = pfd_recalc,
-	.set_rate = pfd_set_rate,
-	.round_rate = pfd_round_rate,
-	.enable = pfd_enable,
-	.disable = pfd_disable,
 	.flags = RATE_PROPAGATES,
 };
 
 static struct clk pfd3_clk = {
 	.name = "pfd3",
-	.parent = &apll_clk,
-	.enable_reg = (void *)MXC_ANADIG_FRAC0,
-	.enable_shift = MXC_ANADIG_PFD3_FRAC_OFFSET,
-	.recalc = pfd_recalc,
-	.set_rate = pfd_set_rate,
-	.round_rate = pfd_round_rate,
-	.enable = pfd_enable,
-	.disable = pfd_disable,
 	.flags = RATE_PROPAGATES,
 };
 
 static struct clk pfd4_clk = {
 	.name = "pfd4",
-	.parent = &apll_clk,
-	.enable_reg = (void *)MXC_ANADIG_FRAC1,
-	.enable_shift = MXC_ANADIG_PFD4_FRAC_OFFSET,
-	.recalc = pfd_recalc,
-	.set_rate = pfd_set_rate,
-	.round_rate = pfd_round_rate,
-	.enable = pfd_enable,
-	.disable = pfd_disable,
 	.flags = RATE_PROPAGATES,
 };
 
 static struct clk pfd5_clk = {
 	.name = "pfd5",
-	.parent = &apll_clk,
-	.enable_reg = (void *)MXC_ANADIG_FRAC1,
-	.enable_shift = MXC_ANADIG_PFD5_FRAC_OFFSET,
-	.recalc = pfd_recalc,
-	.set_rate = pfd_set_rate,
-	.round_rate = pfd_round_rate,
-	.enable = pfd_enable,
-	.disable = pfd_disable,
 	.flags = RATE_PROPAGATES,
 };
 
 static struct clk pfd6_clk = {
 	.name = "pfd6",
-	.parent = &apll_clk,
-	.enable_reg = (void *)MXC_ANADIG_FRAC1,
-	.enable_shift = MXC_ANADIG_PFD6_FRAC_OFFSET,
-	.recalc = pfd_recalc,
-	.set_rate = pfd_set_rate,
-	.round_rate = pfd_round_rate,
-	.enable = pfd_enable,
-	.disable = pfd_disable,
 	.flags = RATE_PROPAGATES,
 };
 
 static struct clk pfd7_clk = {
 	.name = "pfd7",
-	.parent = &apll_clk,
-	.enable_reg = (void *)MXC_ANADIG_FRAC1,
-	.enable_shift = MXC_ANADIG_PFD7_FRAC_OFFSET,
-	.recalc = pfd_recalc,
-	.set_rate = pfd_set_rate,
-	.round_rate = pfd_round_rate,
-	.enable = pfd_enable,
-	.disable = pfd_disable,
 	.flags = RATE_PROPAGATES,
 };
 
@@ -552,6 +347,8 @@ static int _clk_pll_set_rate(struct clk *clk, unsigned long rate)
 {
 	u32 reg, reg1;
 	void __iomem *pllbase;
+	struct timespec nstimeofday;
+	struct timespec curtime;
 
 	long mfi, pdf, mfn, mfd = 999999;
 	s64 temp64;
@@ -599,9 +396,13 @@ static int _clk_pll_set_rate(struct clk *clk, unsigned long rate)
 			__raw_writel(reg1, pllbase + MXC_PLL_DP_CTL);
 		}
 		/* Wait for lock */
-		if (!WAIT(__raw_readl(pllbase + MXC_PLL_DP_CTL)
-			  & MXC_PLL_DP_CTL_LRF, SPIN_DELAY))
-			panic("pll_set_rate: pll relock failed\n");
+		getnstimeofday(&nstimeofday);
+		while (!(__raw_readl(pllbase + MXC_PLL_DP_CTL)
+					& MXC_PLL_DP_CTL_LRF)) {
+			getnstimeofday(&curtime);
+			if (curtime.tv_nsec - nstimeofday.tv_nsec > SPIN_DELAY)
+				panic("pll_set_rate: pll relock failed\n");
+		}
 	}
 	clk->rate = rate;
 	return 0;
@@ -611,20 +412,20 @@ static int _clk_pll_enable(struct clk *clk)
 {
 	u32 reg;
 	void __iomem *pllbase;
+	struct timespec nstimeofday;
+	struct timespec curtime;
 
 	pllbase = _get_pll_base(clk);
-	reg = __raw_readl(pllbase + MXC_PLL_DP_CTL);
-
-	if (reg & MXC_PLL_DP_CTL_UPEN)
-		return 0;
-
-	reg |=  MXC_PLL_DP_CTL_UPEN;
+	reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) | MXC_PLL_DP_CTL_UPEN;
 	__raw_writel(reg, pllbase + MXC_PLL_DP_CTL);
 
 	/* Wait for lock */
-	if (!WAIT(__raw_readl(pllbase + MXC_PLL_DP_CTL) & MXC_PLL_DP_CTL_LRF,
-				SPIN_DELAY))
-		panic("pll relock failed\n");
+	getnstimeofday(&nstimeofday);
+	while (!(__raw_readl(pllbase + MXC_PLL_DP_CTL) & MXC_PLL_DP_CTL_LRF)) {
+		getnstimeofday(&curtime);
+		if (curtime.tv_nsec - nstimeofday.tv_nsec > SPIN_DELAY)
+			panic("pll relock failed\n");
+	}
 	return 0;
 }
 
@@ -750,6 +551,17 @@ static struct clk pll3_sw_clk = {
 	.flags = RATE_PROPAGATES,
 };
 
+/* same as pll4_main_clk. These two clocks should always be the same */
+static struct clk pll4_sw_clk = {
+	.name = "pll4",
+	.parent = &osc_clk,
+	.set_rate = _clk_pll_set_rate,
+	.recalc = _clk_pll_recalc,
+	.enable = _clk_pll_enable,
+	.disable = _clk_pll_disable,
+	.flags = RATE_PROPAGATES,
+};
+
 static int _clk_lp_apm_set_parent(struct clk *clk, struct clk *parent)
 {
 	u32 reg;
@@ -841,7 +653,7 @@ static int _clk_main_bus_set_parent(struct clk *clk, struct clk *parent)
 	mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk,
 			&lp_apm_clk);
 	reg = __raw_readl(MXC_CCM_CBCDR) & ~MX50_CCM_CBCDR_PERIPH_CLK_SEL_MASK;
-	reg |= (mux << MX50_CCM_CBCDR_PERIPH_CLK_SEL_OFFSET);
+	reg |= mux;
 	__raw_writel(reg, MXC_CCM_CBCDR);
 
 	return 0;
@@ -868,6 +680,8 @@ static void _clk_axi_a_recalc(struct clk *clk)
 static int _clk_axi_a_set_rate(struct clk *clk, unsigned long rate)
 {
 	u32 reg, div;
+	struct timespec nstimeofday;
+	struct timespec curtime;
 
 	div = clk->parent->rate / rate;
 	if (div == 0)
@@ -880,9 +694,12 @@ static int _clk_axi_a_set_rate(struct clk *clk, unsigned long rate)
 	reg |= (div - 1) << MXC_CCM_CBCDR_AXI_A_PODF_OFFSET;
 	__raw_writel(reg, MXC_CCM_CBCDR);
 
-	if (!WAIT(!(__raw_readl(MXC_CCM_CDHIPR)
-	     & MXC_CCM_CDHIPR_AXI_A_PODF_BUSY), SPIN_DELAY))
-		panic("pll _clk_axi_a_set_rate failed\n");
+	getnstimeofday(&nstimeofday);
+	while (__raw_readl(MXC_CCM_CDHIPR) & MXC_CCM_CDHIPR_AXI_A_PODF_BUSY) {
+		getnstimeofday(&curtime);
+		if (curtime.tv_nsec - nstimeofday.tv_nsec > SPIN_DELAY)
+			panic("pll _clk_axi_a_set_rate failed\n");
+	}
 	clk->rate = rate;
 
 	return 0;
@@ -924,6 +741,8 @@ static void _clk_axi_b_recalc(struct clk *clk)
 static int _clk_axi_b_set_rate(struct clk *clk, unsigned long rate)
 {
 	u32 reg, div;
+	struct timespec nstimeofday;
+	struct timespec curtime;
 
 	div = clk->parent->rate / rate;
 	if (div == 0)
@@ -936,9 +755,12 @@ static int _clk_axi_b_set_rate(struct clk *clk, unsigned long rate)
 	reg |= (div - 1) << MXC_CCM_CBCDR_AXI_B_PODF_OFFSET;
 	__raw_writel(reg, MXC_CCM_CBCDR);
 
-	if (!WAIT(!(__raw_readl(MXC_CCM_CDHIPR)
-	     & MXC_CCM_CDHIPR_AXI_B_PODF_BUSY), SPIN_DELAY))
-		panic("_clk_axi_b_set_rate failed\n");
+	getnstimeofday(&nstimeofday);
+	while (__raw_readl(MXC_CCM_CDHIPR) & MXC_CCM_CDHIPR_AXI_B_PODF_BUSY) {
+		getnstimeofday(&curtime);
+		if (curtime.tv_nsec - nstimeofday.tv_nsec > SPIN_DELAY)
+			panic("_clk_axi_b_set_rate failed\n");
+	}
 
 	clk->rate = rate;
 
@@ -982,6 +804,8 @@ static void _clk_ahb_recalc(struct clk *clk)
 static int _clk_ahb_set_rate(struct clk *clk, unsigned long rate)
 {
 	u32 reg, div;
+	struct timespec nstimeofday;
+	struct timespec curtime;
 
 	div = clk->parent->rate / rate;
 	if (div == 0)
@@ -994,9 +818,12 @@ static int _clk_ahb_set_rate(struct clk *clk, unsigned long rate)
 	reg |= (div - 1) << MXC_CCM_CBCDR_AHB_PODF_OFFSET;
 	__raw_writel(reg, MXC_CCM_CBCDR);
 
-	if (!WAIT(!(__raw_readl(MXC_CCM_CDHIPR) & MXC_CCM_CDHIPR_AHB_PODF_BUSY),
-				SPIN_DELAY))
+	getnstimeofday(&nstimeofday);
+	while (__raw_readl(MXC_CCM_CDHIPR) & MXC_CCM_CDHIPR_AHB_PODF_BUSY) {
+		getnstimeofday(&curtime);
+		if (curtime.tv_nsec - nstimeofday.tv_nsec > SPIN_DELAY)
 			panic("_clk_ahb_set_rate failed\n");
+	}
 	clk->rate = rate;
 
 	return 0;
@@ -1062,6 +889,85 @@ static struct clk ahb_max_clk = {
 	.disable = _clk_max_disable,
 };
 
+static int _clk_weim_set_parent(struct clk *clk, struct clk *parent)
+{
+	u32 reg;
+
+	reg = __raw_readl(MXC_CCM_CBCDR);
+	if (parent == &ahb_clk)
+		reg |= MX50_CCM_CBCDR_WEIM_CLK_SEL;
+	else if (parent == &main_bus_clk)
+		reg &= ~MX50_CCM_CBCDR_WEIM_CLK_SEL;
+	else
+		BUG();
+	__raw_writel(reg, MXC_CCM_CBCDR);
+
+	return 0;
+}
+
+static void _clk_weim_recalc(struct clk *clk)
+{
+	u32 reg, div;
+
+	reg = __raw_readl(MXC_CCM_CBCDR);
+	div = ((reg & MXC_CCM_CBCDR_EMI_PODF_MASK) >>
+	       MXC_CCM_CBCDR_EMI_PODF_OFFSET) + 1;
+	clk->rate = clk->parent->rate / div;
+}
+
+static int _clk_weim_set_rate(struct clk *clk, unsigned long rate)
+{
+	u32 reg, div;
+	struct timespec nstimeofday;
+	struct timespec curtime;
+
+	div = clk->parent->rate / rate;
+	if (div == 0)
+		div++;
+	if (((clk->parent->rate / div) != rate) || (div > 8))
+		return -EINVAL;
+	reg = __raw_readl(MXC_CCM_CBCDR);
+	reg &= ~MXC_CCM_CBCDR_EMI_PODF_MASK;
+	reg |= (div - 1) << MXC_CCM_CBCDR_EMI_PODF_OFFSET;
+	__raw_writel(reg, MXC_CCM_CBCDR);
+	getnstimeofday(&nstimeofday);
+	while (__raw_readl(MXC_CCM_CDHIPR) & MXC_CCM_CDHIPR_EMI_PODF_BUSY) {
+		getnstimeofday(&curtime);
+		if ((curtime.tv_nsec - nstimeofday.tv_nsec) > SPIN_DELAY)
+			panic("_clk_emi_slow_set_rate failed\n");
+	}
+	clk->rate = rate;
+
+	return 0;
+}
+
+static unsigned long _clk_weim_round_rate(struct clk *clk,
+					      unsigned long rate)
+{
+	u32 div;
+
+	div = clk->parent->rate / rate;
+	if (div > 8)
+		div = 8;
+	else if (div == 0)
+		div++;
+	return clk->parent->rate / div;
+}
+
+
+static struct clk weim_clk = {
+	.name = "weim_clk",
+	.parent = &main_bus_clk,
+	.set_parent = _clk_weim_set_parent,
+	.recalc = _clk_weim_recalc,
+	.set_rate = _clk_weim_set_rate,
+	.round_rate = _clk_weim_round_rate,
+	.enable = _clk_enable,
+	.enable_reg = MXC_CCM_CCGR5,
+	.enable_shift = MXC_CCM_CCGR5_CG8_OFFSET,
+	.disable = _clk_disable_inwait,
+	.flags = RATE_PROPAGATES,
+};
 
 static struct clk ahbmux1_clk = {
 	.name = "ahbmux1_clk",
@@ -1156,138 +1062,6 @@ static struct clk ipmux2_clk = {
 	.disable = _clk_disable,
 };
 
-static int _clk_sys_clk_enable(struct clk *clk)
-{
-	u32 reg;
-
-	reg = __raw_readl(MXC_CCM_CLK_SYS);
-	reg &= ~(MXC_CCM_CLK_SYS_SYS_XTAL_CLKGATE_MASK |
-				MXC_CCM_CLK_SYS_SYS_PLL_CLKGATE_MASK);
-	if (__raw_readl(MXC_CCM_CLKSEQ_BYPASS) & 0x1)
-		reg |= MXC_CCM_CLK_SYS_SYS_PLL_CLKGATE_MASK;
-	else
-		reg |= MXC_CCM_CLK_SYS_SYS_XTAL_CLKGATE_MASK;
-	__raw_writel(reg, MXC_CCM_CLK_SYS);
-	return 0;
-}
-
-static void _clk_sys_clk_disable(struct clk *clk)
-{
-	u32 reg, reg1;
-
-	reg1 = (__raw_readl(databahn + DATABAHN_CTL_REG55))
-					& DDR_SYNC_MODE;
-	reg = __raw_readl(MXC_CCM_CLK_SYS);
-	reg &= ~(MXC_CCM_CLK_SYS_SYS_XTAL_CLKGATE_MASK |
-				MXC_CCM_CLK_SYS_SYS_PLL_CLKGATE_MASK);
-	if (__raw_readl(MXC_CCM_CLKSEQ_BYPASS) & 0x1)
-		reg |= 1 << MXC_CCM_CLK_SYS_SYS_PLL_CLKGATE_OFFSET;
-	else {
-		/* If DDR is sourced from SYS_CLK (in Sync mode), we cannot
-		 * gate its clock when ARM is in wait if the DDR is not in
-		 * self refresh.
-		 */
-		if (reg1 == DDR_SYNC_MODE)
-			reg |= 3 << MXC_CCM_CLK_SYS_SYS_XTAL_CLKGATE_OFFSET;
-		else
-			reg |= 1 << MXC_CCM_CLK_SYS_SYS_XTAL_CLKGATE_OFFSET;
-	}
-	__raw_writel(reg, MXC_CCM_CLK_SYS);
-}
-
-static struct clk sys_clk = {
-	.name = "sys_clk",
-	.enable = _clk_sys_clk_enable,
-	.disable = _clk_sys_clk_disable,
-};
-
-
-static int _clk_weim_set_parent(struct clk *clk, struct clk *parent)
-{
-	u32 reg;
-
-	reg = __raw_readl(MXC_CCM_CBCDR);
-	if (parent == &ahb_clk)
-		reg |= MX50_CCM_CBCDR_WEIM_CLK_SEL;
-	else if (parent == &main_bus_clk)
-		reg &= ~MX50_CCM_CBCDR_WEIM_CLK_SEL;
-	else
-		BUG();
-	__raw_writel(reg, MXC_CCM_CBCDR);
-
-	return 0;
-}
-
-static void _clk_weim_recalc(struct clk *clk)
-{
-	u32 reg, div;
-
-	reg = __raw_readl(MXC_CCM_CBCDR);
-	div = ((reg & MXC_CCM_CBCDR_EMI_PODF_MASK) >>
-	       MXC_CCM_CBCDR_EMI_PODF_OFFSET) + 1;
-	clk->rate = clk->parent->rate / div;
-}
-
-static int _clk_weim_set_rate(struct clk *clk, unsigned long rate)
-{
-	u32 reg, div;
-
-	div = clk->parent->rate / rate;
-	if (div == 0)
-		div++;
-	if (((clk->parent->rate / div) != rate) || (div > 8))
-		return -EINVAL;
-	reg = __raw_readl(MXC_CCM_CBCDR);
-	reg &= ~MXC_CCM_CBCDR_EMI_PODF_MASK;
-	reg |= (div - 1) << MXC_CCM_CBCDR_EMI_PODF_OFFSET;
-	__raw_writel(reg, MXC_CCM_CBCDR);
-	if (!WAIT(!(__raw_readl(MXC_CCM_CDHIPR) & MXC_CCM_CDHIPR_EMI_PODF_BUSY),
-		  SPIN_DELAY))
-		panic("_clk_emi_slow_set_rate failed\n");
-	clk->rate = rate;
-
-	return 0;
-}
-
-static unsigned long _clk_weim_round_rate(struct clk *clk,
-					      unsigned long rate)
-{
-	u32 div;
-
-	div = clk->parent->rate / rate;
-	if (div > 8)
-		div = 8;
-	else if (div == 0)
-		div++;
-	return clk->parent->rate / div;
-}
-
-static struct clk weim_clk[] = {
-	{
-	.name = "weim_clk",
-	.parent = &main_bus_clk,
-	.set_parent = _clk_weim_set_parent,
-	.recalc = _clk_weim_recalc,
-	.set_rate = _clk_weim_set_rate,
-	.round_rate = _clk_weim_round_rate,
-	.enable = _clk_enable,
-	.enable_reg = MXC_CCM_CCGR5,
-	.enable_shift = MXC_CCM_CCGR5_CG8_OFFSET,
-	.disable = _clk_disable_inwait,
-	.flags = RATE_PROPAGATES,
-	.secondary = &weim_clk[1],
-	},
-	{
-	.name = "weim_ipg_clk",
-	.parent = &ipg_clk,
-	.secondary = &sys_clk,
-	.enable = _clk_enable,
-	.enable_reg = MXC_CCM_CCGR5,
-	.enable_shift = MXC_CCM_CCGR5_CG9_OFFSET,
-	.disable = _clk_disable_inwait,
-	}
-};
-
 static int _clk_ocram_enable(struct clk *clk)
 {
 	return 0;
@@ -1299,13 +1073,13 @@ static void _clk_ocram_disable(struct clk *clk)
 
 static struct clk ocram_clk = {
 	.name = "ocram_clk",
-	.parent = &sys_clk,
 	.enable_reg = MXC_CCM_CCGR6,
 	.enable_shift = MXC_CCM_CCGR6_CG1_OFFSET,
 	.enable = _clk_ocram_enable,
 	.disable = _clk_ocram_disable,
 };
 
+
 static struct clk aips_tz1_clk = {
 	.name = "aips_tz1_clk",
 	.parent = &ahb_clk,
@@ -1372,7 +1146,6 @@ static struct clk sdma_clk[] = {
 	{
 	 .name = "sdma_ipg_clk",
 	 .parent = &ipg_clk,
-	 .secondary = &ddr_clk,
 	 },
 };
 
@@ -1559,16 +1332,17 @@ static struct clk gpt_clk[] = {
 	 .parent = &ipg_perclk,
 	 .id = 0,
 	 .enable_reg = MXC_CCM_CCGR2,
-	 .enable_shift = MXC_CCM_CCGR2_CG10_OFFSET,
+	 .enable_shift = MXC_CCM_CCGR2_CG9_OFFSET,
 	 .enable = _clk_enable,
 	 .disable = _clk_disable,
+	 .secondary = &gpt_clk[1],
 	 },
 	{
 	 .name = "gpt_ipg_clk",
 	 .id = 0,
 	 .parent = &ipg_clk,
 	 .enable_reg = MXC_CCM_CCGR2,
-	 .enable_shift = MXC_CCM_CCGR2_CG9_OFFSET,
+	 .enable_shift = MXC_CCM_CCGR2_CG10_OFFSET,
 	 .enable = _clk_enable,
 	 .disable = _clk_disable,
 	 },
@@ -2042,12 +1816,10 @@ static struct clk tmax2_clk = {
 static struct clk usb_ahb_clk = {
 	 .name = "usb_ahb_clk",
 	 .parent = &ipg_clk,
-	 .secondary = &ddr_clk,
 	 .enable = _clk_enable,
 	 .enable_reg = MXC_CCM_CCGR2,
 	 .enable_shift = MXC_CCM_CCGR2_CG13_OFFSET,
 	 .disable = _clk_disable,
-	.flags = AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE,
 };
 
 static struct clk usb_phy_clk[] = {
@@ -2074,7 +1846,6 @@ static struct clk usb_phy_clk[] = {
 static struct clk esdhc_dep_clks = {
 	 .name = "sd_dep_clk",
 	 .parent = &spba_clk,
-	 .secondary = &ddr_clk,
 };
 
 static void _clk_esdhc1_recalc(struct clk *clk)
@@ -2097,8 +1868,8 @@ static int _clk_esdhc1_set_parent(struct clk *clk, struct clk *parent)
 	reg = __raw_readl(MXC_CCM_CSCMR1);
 	mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk,
 		       &lp_apm_clk);
-	reg = reg & ~MX50_CCM_CSCMR1_ESDHC1_CLK_SEL_MASK;
-	reg |= mux << MX50_CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET;
+	reg = reg & ~MXC_CCM_CSCMR1_ESDHC1_MSHC2_CLK_SEL_MASK;
+	reg |= mux << MXC_CCM_CSCMR1_ESDHC1_MSHC2_CLK_SEL_OFFSET;
 	__raw_writel(reg, MXC_CCM_CSCMR1);
 
 	return 0;
@@ -2143,7 +1914,6 @@ static struct clk esdhc1_clk[] = {
 	 .enable_shift = MXC_CCM_CCGR3_CG1_OFFSET,
 	 .disable = _clk_disable,
 	 .secondary = &esdhc1_clk[1],
-	.flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
 	 },
 	{
 	 .name = "esdhc_ipg_clk",
@@ -2170,9 +1940,9 @@ static int _clk_esdhc2_set_parent(struct clk *clk, struct clk *parent)
 
 	reg = __raw_readl(MXC_CCM_CSCMR1);
 	if (parent == &esdhc1_clk[0])
-		reg &= ~MX50_CCM_CSCMR1_ESDHC2_CLK_SEL;
+		reg &= ~MXC_CCM_CSCMR1_ESDHC2_CLK_SEL;
 	else if (parent == &esdhc3_clk[0])
-		reg |= MX50_CCM_CSCMR1_ESDHC2_CLK_SEL;
+		reg |= MXC_CCM_CSCMR1_ESDHC2_CLK_SEL;
 	else
 		BUG();
 	__raw_writel(reg, MXC_CCM_CSCMR1);
@@ -2190,7 +1960,6 @@ static struct clk esdhc2_clk[] = {
 	 .enable_shift = MXC_CCM_CCGR3_CG3_OFFSET,
 	 .disable = _clk_disable,
 	 .secondary = &esdhc2_clk[1],
-	.flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
 	 },
 	{
 	 .name = "esdhc_ipg_clk",
@@ -2218,8 +1987,8 @@ static int _clk_esdhc3_set_parent(struct clk *clk, struct clk *parent)
 	mux = _get_mux8(parent, &pll1_sw_clk, &pll2_sw_clk,
 			&pll3_sw_clk, &lp_apm_clk, &pfd0_clk,
 			&pfd1_clk, &pfd4_clk, &osc_clk);
-	reg = reg & ~MX50_CCM_CSCMR1_ESDHC3_CLK_SEL_MASK;
-	reg |= mux << MX50_CCM_CSCMR1_ESDHC3_CLK_SEL_OFFSET;
+	reg = reg & ~MXC_CCM_CSCMR1_ESDHC3_MSHC2_CLK_SEL_MASK;
+	reg |= mux << MXC_CCM_CSCMR1_ESDHC3_MSHC2_CLK_SEL_OFFSET;
 	__raw_writel(reg, MXC_CCM_CSCMR1);
 
 	return 0;
@@ -2277,7 +2046,6 @@ static struct clk esdhc3_clk[] = {
 	 .enable_shift = MXC_CCM_CCGR3_CG5_OFFSET,
 	 .disable = _clk_disable,
 	 .secondary = &esdhc3_clk[1],
-	.flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
 	 },
 	{
 	 .name = "esdhc_ipg_clk",
@@ -2303,9 +2071,9 @@ static int _clk_esdhc4_set_parent(struct clk *clk, struct clk *parent)
 
 	reg = __raw_readl(MXC_CCM_CSCMR1);
 	if (parent == &esdhc1_clk[0])
-		reg &= ~MX50_CCM_CSCMR1_ESDHC4_CLK_SEL;
+		reg &= ~MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
 	else if (parent == &esdhc3_clk[0])
-		reg |= MX50_CCM_CSCMR1_ESDHC4_CLK_SEL;
+		reg |= MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
 	else
 		BUG();
 	__raw_writel(reg, MXC_CCM_CSCMR1);
@@ -2324,7 +2092,6 @@ static struct clk esdhc4_clk[] = {
 	 .enable_shift = MXC_CCM_CCGR3_CG7_OFFSET,
 	 .disable = _clk_disable,
 	 .secondary = &esdhc4_clk[1],
-	.flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
 	 },
 	{
 	 .name = "esdhc_ipg_clk",
@@ -2355,7 +2122,6 @@ static int _clk_ddr_set_parent(struct clk *clk, struct clk *parent)
 		reg &= ~MXC_CCM_CLK_DDR_DDR_PFD_SEL;
 	else
 		return -EINVAL;
-	__raw_writel(reg, MXC_CCM_CLK_DDR);
 	return 0;
 }
 
@@ -2372,37 +2138,12 @@ static void _clk_ddr_recalc(struct clk *clk)
 		clk->rate = 0;
 }
 
-static int _clk_ddr_enable(struct clk *clk)
-{
-	u32 reg;
-
-	_clk_enable(clk);
-	reg = (__raw_readl(databahn + DATABAHN_CTL_REG55)) &
-				DDR_SYNC_MODE;
-	if (reg != DDR_SYNC_MODE) {
-		reg = __raw_readl(MXC_CCM_CLK_DDR);
-		reg |= MXC_CCM_CLK_DDR_DDR_CLKGATE_MASK;
-		__raw_writel(reg, MXC_CCM_CLK_DDR);
-	}
-	return 0;
-}
-
-static void _clk_ddr_disable(struct clk *clk)
-{
-	_clk_disable_inwait(clk);
-}
-
-
 static struct clk ddr_clk = {
 	.name = "ddr_clk",
 	.parent = &pll1_sw_clk,
-	.secondary = &sys_clk,
 	.set_parent = _clk_ddr_set_parent,
 	.recalc = _clk_ddr_recalc,
-	.enable = _clk_ddr_enable,
-	.enable_reg = MXC_CCM_CCGR6,
-	.enable_shift = MXC_CCM_CCGR6_CG15_OFFSET,
-	.disable = _clk_ddr_disable,
+	.flags = RATE_PROPAGATES,
 };
 
 static void _clk_pgc_recalc(struct clk *clk)
@@ -2423,6 +2164,7 @@ static struct clk pgc_clk = {
 };
 
 /*usb OTG clock */
+
 static struct clk usb_clk = {
 	.name = "usb_clk",
 	.rate = 60000000,
@@ -2438,16 +2180,6 @@ static struct clk rtc_clk = {
 	.disable = _clk_disable,
 };
 
-struct clk rng_clk = {
-	.name = "rng_clk",
-	.id = 0,
-	.parent = &ipg_clk,
-	.enable = _clk_enable,
-	.enable_reg = MXC_CCM_CCGR7,
-	.enable_shift = MXC_CCM_CCGR7_CG1_OFFSET,
-	.disable = _clk_disable,
-};
-
 static struct clk owire_clk = {
 	/* 1w driver come from upstream and use owire as clock name*/
 	.name = "owire",
@@ -2458,6 +2190,7 @@ static struct clk owire_clk = {
 	.disable = _clk_disable,
 };
 
+
 static struct clk fec_clk[] = {
 	{
 	.name = "fec_clk",
@@ -2471,106 +2204,21 @@ static struct clk fec_clk[] = {
 	},
 	{
 	 .name = "fec_sec1_clk",
-	 .parent = &aips_tz2_clk,
-	 .secondary = &ddr_clk,
-	},
-};
-
-static int gpmi_clk_enable(struct clk *clk)
-{
-	u32 reg;
-
-	reg = __raw_readl(MXC_CCM_GPMI);
-	reg |= MXC_CCM_GPMI_CLKGATE_MASK;
-	__raw_writel(reg, MXC_CCM_GPMI);
-	_clk_enable(clk);
-	return 0;
-}
-
-static void gpmi_clk_disable(struct clk *clk)
-{
-	u32 reg;
-
-	reg = __raw_readl(MXC_CCM_GPMI);
-	reg &= ~MXC_CCM_GPMI_CLKGATE_MASK;
-	__raw_writel(reg, MXC_CCM_GPMI);
-	_clk_disable(clk);
-}
-
-static int bch_clk_enable(struct clk *clk)
-{
-	u32 reg;
-
-	reg = __raw_readl(MXC_CCM_BCH);
-	reg |= MXC_CCM_BCH_CLKGATE_MASK;
-	__raw_writel(reg, MXC_CCM_BCH);
-	_clk_enable(clk);
-	return 0;
-}
-
-static void bch_clk_disable(struct clk *clk)
-{
-	u32 reg;
-
-	reg = __raw_readl(MXC_CCM_BCH);
-	reg &= ~MXC_CCM_BCH_CLKGATE_MASK;
-	__raw_writel(reg, MXC_CCM_BCH);
-	_clk_disable(clk);
-}
-
-static struct clk gpmi_nfc_clk[] = {
-	{
-	.name = "gpmi-nfc",
-	.parent = &osc_clk,
-	.secondary = &gpmi_nfc_clk[1],
-	.enable = gpmi_clk_enable,
-	.enable_reg = MXC_CCM_CCGR7,
-	.enable_shift = MXC_CCM_CCGR7_CG9_OFFSET,
-	.disable = gpmi_clk_disable,
-	},
-	{
-	.name = "gpmi-apb",
-	.parent = &ahb_clk,
-	.secondary = &gpmi_nfc_clk[2],
-	.enable = _clk_enable,
-	.enable_reg = MXC_CCM_CCGR7,
-	.enable_shift = MXC_CCM_CCGR7_CG8_OFFSET,
-	.disable = _clk_disable,
-	},
-	{
-	.name = "bch",
-	.parent = &osc_clk,
-	.secondary = &gpmi_nfc_clk[3],
-	.enable = bch_clk_enable,
-	.enable_reg = MXC_CCM_CCGR7,
-	.enable_shift = MXC_CCM_CCGR7_CG0_OFFSET,
-	.disable = bch_clk_disable,
+	 .parent = &tmax2_clk,
+	 .secondary = &fec_clk[2],
 	},
 	{
-	.name = "bch-apb",
-	.parent = &ahb_clk,
-	.enable = _clk_enable,
-	.enable_reg = MXC_CCM_CCGR7,
-	.enable_shift = MXC_CCM_CCGR7_CG12_OFFSET,
-	.disable = _clk_disable,
+	 .name = "fec_sec2_clk",
+	 .parent = &aips_tz2_clk,
 	},
 };
 
-static struct clk ocotp_clk = {
-	.name = "ocotp_ctrl_apb",
-	.parent = &ahb_clk,
-	.enable = _clk_enable,
-	.enable_reg = MXC_CCM_CCGR7,
-	.enable_shift = MXC_CCM_CCGR7_CG13_OFFSET,
-	.disable = _clk_disable,
-};
-
 static int _clk_gpu2d_set_parent(struct clk *clk, struct clk *parent)
 {
 	u32 reg, mux;
 
 	reg = __raw_readl(MXC_CCM_CBCMR);
-	mux = _get_mux(parent, &axi_a_clk, &axi_b_clk, &weim_clk[0], &ahb_clk);
+	mux = _get_mux(parent, &axi_a_clk, &axi_b_clk, &weim_clk, &ahb_clk);
 	reg = (reg & ~MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK) |
 	    (mux << MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET);
 	__raw_writel(reg, MXC_CCM_CBCMR);
@@ -2581,7 +2229,6 @@ static int _clk_gpu2d_set_parent(struct clk *clk, struct clk *parent)
 static struct clk gpu2d_clk = {
 	.name = "gpu2d_clk",
 	.parent = &axi_a_clk,
-	.secondary = &ddr_clk,
 	.set_parent = _clk_gpu2d_set_parent,
 	.enable = _clk_enable,
 	.enable_reg = MXC_CCM_CCGR6,
@@ -2592,25 +2239,13 @@ static struct clk gpu2d_clk = {
 
 static struct clk apbh_dma_clk = {
 	.name = "apbh_dma_clk",
-	.parent = &ahb_clk,
-	.secondary = &ddr_clk,
+	.parent = &pll1_sw_clk,
 	.enable = _clk_enable,
-	.disable = _clk_disable_inwait,
+	.disable = _clk_disable,
 	.enable_reg = MXC_CCM_CCGR7,
 	.enable_shift = MXC_CCM_CCGR7_CG10_OFFSET,
 };
 
-struct clk dcp_clk = {
-	.name = "dcp_clk",
-	.id = 0,
-	.parent = &ahb_clk,
-	.secondary = &apbh_dma_clk,
-	.enable = _clk_enable,
-	.enable_reg = MXC_CCM_CCGR7,
-	.enable_shift = MXC_CCM_CCGR7_CG11_OFFSET,
-	.disable = _clk_disable,
-};
-
 static int _clk_display_axi_set_parent(struct clk *clk, struct clk *parent)
 {
 	u32 reg, mux;
@@ -2657,15 +2292,17 @@ static int _clk_display_axi_set_rate(struct clk *clk, unsigned long rate)
 	reg |= new_div << MXC_CCM_DISPLAY_AXI_DIV_OFFSET;
 	__raw_writel(reg, MXC_CCM_DISPLAY_AXI);
 
+#if 0
 	while (__raw_readl(MXC_CCM_CSR2) & MXC_CCM_CSR2_DISPLAY_AXI_BUSY)
 		;
+#endif
+
 	return 0;
 }
 
 static struct clk display_axi_clk = {
 	.name = "display_axi",
 	.parent = &osc_clk,
-	.secondary = &apbh_dma_clk,
 	.set_parent = _clk_display_axi_set_parent,
 	.recalc = _clk_display_axi_recalc,
 	.set_rate = _clk_display_axi_set_rate,
@@ -2674,18 +2311,17 @@ static struct clk display_axi_clk = {
 	.disable = _clk_disable,
 	.enable_reg = MXC_CCM_DISPLAY_AXI,
 	.enable_shift = MXC_CCM_DISPLAY_AXI_CLKGATE_OFFSET,
-	.flags = RATE_PROPAGATES,
 };
 
 /* TODO: check Auto-Slow Mode */
 static struct clk pxp_axi_clk = {
 	.name = "pxp_axi",
 	.parent = &display_axi_clk,
+	.secondary = &apbh_dma_clk,
 	.enable = _clk_enable,
 	.disable = _clk_disable,
 	.enable_reg = MXC_CCM_CCGR6,
 	.enable_shift = MXC_CCM_CCGR6_CG9_OFFSET,
-	.flags = AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE,
 };
 
 static struct clk elcdif_axi_clk = {
@@ -2695,7 +2331,6 @@ static struct clk elcdif_axi_clk = {
 	.disable = _clk_disable,
 	.enable_reg = MXC_CCM_CCGR6,
 	.enable_shift = MXC_CCM_CCGR6_CG10_OFFSET,
-	.flags = AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE,
 };
 
 static int _clk_elcdif_pix_set_parent(struct clk *clk, struct clk *parent)
@@ -2750,40 +2385,17 @@ static int _clk_elcdif_pix_set_rate(struct clk *clk, unsigned long rate)
 	return 0;
 }
 
-static int _clk_elcdif_pix_enable(struct clk *clk)
-{
-	u32 reg;
-
-	_clk_enable(clk);
-	reg = __raw_readl(MXC_CCM_ELCDIFPIX);
-	reg |= 0x3 << MXC_CCM_ELCDIFPIX_CLKGATE_OFFSET;
-	__raw_writel(reg, MXC_CCM_ELCDIFPIX);
-	return 0;
-}
-
-static void _clk_elcdif_pix_disable(struct clk *clk)
-{
-	u32 reg;
-
-	reg = __raw_readl(MXC_CCM_ELCDIFPIX);
-	reg &= ~MXC_CCM_ELCDIFPIX_CLKGATE_MASK;
-	__raw_writel(reg, MXC_CCM_ELCDIFPIX);
-	_clk_disable(clk);
-}
-
 static struct clk elcdif_pix_clk = {
 	.name = "elcdif_pix",
 	.parent = &osc_clk,
-	.secondary = &ddr_clk,
-	.enable = _clk_elcdif_pix_enable,
-	.disable = _clk_elcdif_pix_disable,
+	.enable = _clk_enable,
+	.disable = _clk_disable,
 	.enable_reg = MXC_CCM_CCGR6,
 	.enable_shift = MXC_CCM_CCGR6_CG6_OFFSET,
 	.set_parent = _clk_elcdif_pix_set_parent,
 	.recalc = _clk_elcdif_pix_recalc,
 	.round_rate = _clk_elcdif_pix_round_rate,
 	.set_rate = _clk_elcdif_pix_set_rate,
-	.flags = AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE,
 };
 
 static int _clk_epdc_axi_set_parent(struct clk *clk, struct clk *parent)
@@ -2857,7 +2469,10 @@ static int _clk_epdc_axi_enable(struct clk *clk)
 {
 	u32 reg;
 
-	_clk_enable(clk);
+	reg = __raw_readl(MXC_CCM_CCGR6);
+	reg |= MXC_CCM_CCGR6_CG8_MASK;
+	__raw_writel(reg, MXC_CCM_CCGR6);
+
 	reg = __raw_readl(MXC_CCM_EPDC_AXI);
 	reg |= MXC_CCM_EPDC_AXI_CLKGATE_MASK;
 	__raw_writel(reg, MXC_CCM_EPDC_AXI);
@@ -2869,26 +2484,25 @@ static void _clk_epdc_axi_disable(struct clk *clk)
 {
 	u32 reg;
 
+	reg = __raw_readl(MXC_CCM_CCGR6);
+	reg &= ~MXC_CCM_CCGR6_CG8_MASK;
+	__raw_writel(reg, MXC_CCM_CCGR6);
+
 	reg = __raw_readl(MXC_CCM_EPDC_AXI);
 	reg &= ~MXC_CCM_EPDC_AXI_CLKGATE_MASK;
 	__raw_writel(reg, MXC_CCM_EPDC_AXI);
-	_clk_disable(clk);
 }
 
 /* TODO: check Auto-Slow Mode */
 static struct clk epdc_axi_clk = {
 	.name = "epdc_axi",
-	.parent = &osc_clk,
-	.secondary = &apbh_dma_clk,
-	.enable_reg = MXC_CCM_CCGR6,
-	.enable_shift = MXC_CCM_CCGR6_CG8_OFFSET,
+	.parent = &apbh_dma_clk,
 	.set_parent = _clk_epdc_axi_set_parent,
 	.recalc = _clk_epdc_axi_recalc,
 	.set_rate = _clk_epdc_axi_set_rate,
 	.round_rate = _clk_epdc_axi_round_rate,
 	.enable = _clk_epdc_axi_enable,
 	.disable = _clk_epdc_axi_disable,
-	.flags = AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE,
 };
 
 
@@ -2951,7 +2565,10 @@ static int _clk_epdc_pix_enable(struct clk *clk)
 {
 	u32 reg;
 
-	_clk_enable(clk);
+	reg = __raw_readl(MXC_CCM_CCGR6);
+	reg |= MXC_CCM_CCGR6_CG5_MASK;
+	__raw_writel(reg, MXC_CCM_CCGR6);
+
 	reg = __raw_readl(MXC_CCM_EPDCPIX);
 	reg |= MXC_CCM_EPDC_PIX_CLKGATE_MASK;
 	__raw_writel(reg, MXC_CCM_EPDCPIX);
@@ -2963,26 +2580,25 @@ static void _clk_epdc_pix_disable(struct clk *clk)
 {
 	u32 reg;
 
+	reg = __raw_readl(MXC_CCM_CCGR6);
+	reg &= ~MXC_CCM_CCGR6_CG5_MASK;
+	__raw_writel(reg, MXC_CCM_CCGR6);
+
 	reg = __raw_readl(MXC_CCM_EPDCPIX);
 	reg &= ~MXC_CCM_EPDC_PIX_CLKGATE_MASK;
 	__raw_writel(reg, MXC_CCM_EPDCPIX);
-	_clk_disable(clk);
 }
 
 /* TODO: check Auto-Slow Mode */
 static struct clk epdc_pix_clk = {
 	.name = "epdc_pix",
 	.parent = &osc_clk,
-	.secondary = &apbh_dma_clk,
-	.enable_reg = MXC_CCM_CCGR6,
-	.enable_shift = MXC_CCM_CCGR6_CG5_OFFSET,
 	.set_parent = _clk_epdc_pix_set_parent,
 	.recalc = _clk_epdc_pix_recalc,
 	.set_rate = _clk_epdc_pix_set_rate,
 	.round_rate = _clk_epdc_pix_round_rate,
 	.enable = _clk_epdc_pix_enable,
 	.disable = _clk_epdc_pix_disable,
-	.flags = AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE,
 };
 
 static void cko1_recalc(struct clk *clk)
@@ -3078,7 +2694,7 @@ static int cko1_set_parent(struct clk *clk, struct clk *parent)
 	} else if (parent == &pfd6_clk) {
 		sel = 7;
 		fast = 0;
-	} else if (parent == &weim_clk[0]) {
+	} else if (parent == &weim_clk) {
 		sel = 10;
 		fast = 0;
 	} else if (parent == &ahb_clk) {
@@ -3106,7 +2722,6 @@ static int cko1_set_parent(struct clk *clk, struct clk *parent)
 	__raw_writel(reg, MXC_CCM_CCOSR);
 	return 0;
 }
-
 static struct clk cko1_clk = {
 	.name = "cko1_clk",
 	.parent = &pll1_sw_clk,
@@ -3127,15 +2742,6 @@ static struct clk *mxc_clks[] = {
 	&pll1_sw_clk,
 	&pll2_sw_clk,
 	&pll3_sw_clk,
-	&apll_clk,
-	&pfd0_clk,
-	&pfd1_clk,
-	&pfd2_clk,
-	&pfd3_clk,
-	&pfd4_clk,
-	&pfd5_clk,
-	&pfd6_clk,
-	&pfd7_clk,
 	&ipmux1_clk,
 	&ipmux2_clk,
 	&gpc_dvfs_clk,
@@ -3200,16 +2806,14 @@ static struct clk *mxc_clks[] = {
 	&esdhc4_clk[0],
 	&esdhc4_clk[1],
 	&esdhc_dep_clks,
-	&weim_clk[0],
-	&weim_clk[1],
+	&weim_clk,
 	&ddr_clk,
 	&pgc_clk,
 	&rtc_clk,
-	&rng_clk,
-	&dcp_clk,
 	&owire_clk,
 	&fec_clk[0],
 	&fec_clk[1],
+	&fec_clk[2],
 	&gpu2d_clk,
 	&cko1_clk,
 	&display_axi_clk,
@@ -3218,11 +2822,6 @@ static struct clk *mxc_clks[] = {
 	&epdc_axi_clk,
 	&epdc_pix_clk,
 	&elcdif_pix_clk,
-	&gpmi_nfc_clk[0],
-	&gpmi_nfc_clk[1],
-	&gpmi_nfc_clk[2],
-	&gpmi_nfc_clk[3],
-	&ocotp_clk,
 };
 
 static void clk_tree_init(void)
@@ -3252,10 +2851,10 @@ static void clk_tree_init(void)
 	pll3_sw_clk.parent = &osc_clk;
 
 	/* set weim_clk parent */
-	weim_clk[0].parent = &main_bus_clk;
+	weim_clk.parent = &main_bus_clk;
 	reg = __raw_readl(MXC_CCM_CBCDR);
 	if ((reg & MX50_CCM_CBCDR_WEIM_CLK_SEL) != 0)
-		weim_clk[0].parent = &ahb_clk;
+		weim_clk.parent = &ahb_clk;
 
 	/* set ipg_perclk parent */
 	ipg_perclk.parent = &lp_apm_clk;
@@ -3278,12 +2877,11 @@ int __init mx50_clocks_init(unsigned long ckil, unsigned long osc, unsigned long
 	pll1_base = ioremap(MX53_BASE_ADDR(PLL1_BASE_ADDR), SZ_4K);
 	pll2_base = ioremap(MX53_BASE_ADDR(PLL2_BASE_ADDR), SZ_4K);
 	pll3_base = ioremap(MX53_BASE_ADDR(PLL3_BASE_ADDR), SZ_4K);
-	apll_base = ioremap(ANATOP_BASE_ADDR, SZ_4K);
 
 	/* Turn off all possible clocks */
 	if (mxc_jtag_enabled) {
 		__raw_writel(1 << MXC_CCM_CCGR0_CG0_OFFSET |
-			      3 << MXC_CCM_CCGR0_CG2_OFFSET |
+			      1 << MXC_CCM_CCGR0_CG2_OFFSET |
 			      3 << MXC_CCM_CCGR0_CG3_OFFSET |
 			      3 << MXC_CCM_CCGR0_CG4_OFFSET |
 			      3 << MXC_CCM_CCGR0_CG8_OFFSET |
@@ -3304,14 +2902,17 @@ int __init mx50_clocks_init(unsigned long ckil, unsigned long osc, unsigned long
 	__raw_writel(0, MXC_CCM_CCGR3);
 	__raw_writel(0, MXC_CCM_CCGR4);
 
-	__raw_writel(3 << MXC_CCM_CCGR5_CG6_OFFSET |
+	__raw_writel(1 << MXC_CCM_CCGR5_CG6_OFFSET |
 		     1 << MXC_CCM_CCGR5_CG8_OFFSET |
 		     3 << MXC_CCM_CCGR5_CG9_OFFSET, MXC_CCM_CCGR5);
 
 	__raw_writel(3 << MXC_CCM_CCGR6_CG0_OFFSET |
 				3 << MXC_CCM_CCGR6_CG1_OFFSET |
-				2 << MXC_CCM_CCGR6_CG14_OFFSET |
-				3 << MXC_CCM_CCGR6_CG15_OFFSET, MXC_CCM_CCGR6);
+				3 << MXC_CCM_CCGR6_CG4_OFFSET |
+				3 << MXC_CCM_CCGR6_CG8_OFFSET |
+				3 << MXC_CCM_CCGR6_CG9_OFFSET |
+				3 << MXC_CCM_CCGR6_CG12_OFFSET |
+				3 << MXC_CCM_CCGR6_CG13_OFFSET , MXC_CCM_CCGR6);
 
 	__raw_writel(0, MXC_CCM_CCGR7);
 
@@ -3334,8 +2935,6 @@ int __init mx50_clocks_init(unsigned long ckil, unsigned long osc, unsigned long
 	clk_register(&i2c_clk[2]);
 	clk_register(&usb_phy_clk[1]);
 	clk_register(&ocram_clk);
-	clk_register(&apbh_dma_clk);
-	clk_register(&sys_clk);
 
 	/* set DDR clock parent */
 	reg = __raw_readl(MXC_CCM_CLK_DDR) &
@@ -3350,6 +2949,22 @@ int __init mx50_clocks_init(unsigned long ckil, unsigned long osc, unsigned long
 	clk_set_parent(&esdhc2_clk[0], &esdhc1_clk[0]);
 	clk_set_parent(&esdhc3_clk[0], &pll2_sw_clk);
 
+	clk_register(&apbh_dma_clk);
+
+	clk_set_parent(&epdc_axi_clk, &pll1_sw_clk);
+	/* Set EPDC AXI to 200MHz */
+	/*
+	clk_set_rate(&epdc_axi_clk, 200000000);
+	*/
+	__raw_writel(0xC0000008, MXC_CCM_EPDC_AXI);
+	clk_set_parent(&epdc_pix_clk, &pll1_sw_clk);
+
+	reg = __raw_readl(MXC_CCM_ELCDIFPIX);
+	reg &= ~MXC_CCM_ELCDIFPIX_CLKGATE_MASK;
+	reg = 0x3 << MXC_CCM_ELCDIFPIX_CLKGATE_OFFSET;
+	__raw_writel(reg, MXC_CCM_ELCDIFPIX);
+	clk_set_parent(&elcdif_pix_clk, &pll1_sw_clk);
+
 	/* This will propagate to all children and init all the clock rates */
 	propagate_rate(&osc_clk);
 	propagate_rate(&ckih_clk);
@@ -3357,15 +2972,12 @@ int __init mx50_clocks_init(unsigned long ckil, unsigned long osc, unsigned long
 	propagate_rate(&pll1_sw_clk);
 	propagate_rate(&pll2_sw_clk);
 	propagate_rate(&pll3_sw_clk);
-	propagate_rate(&apll_clk);
 
 	clk_enable(&cpu_clk);
 
 	clk_enable(&main_bus_clk);
 
-	clk_enable(&ocotp_clk);
-
-	databahn = ioremap(MX50_DATABAHN_BASE_ADDR, SZ_16K);
+	clk_enable(&apbh_dma_clk);
 
 	/* Initialise the parents to be axi_b, parents are set to
 	 * axi_a when the clocks are enabled.
@@ -3377,35 +2989,9 @@ int __init mx50_clocks_init(unsigned long ckil, unsigned long osc, unsigned long
 	clk_set_parent(&cspi_main_clk, &lp_apm_clk);
 	clk_set_rate(&cspi_main_clk, 12000000);
 
-	/*
-	 * Set DISPLAY_AXI to 200Mhz
-	 * For Display AXI, source clocks must be
-	 * enabled before dividers can be changed
-	 */
-	clk_enable(&display_axi_clk);
-	clk_enable(&elcdif_axi_clk);
-	clk_enable(&pxp_axi_clk);
-	clk_set_parent(&display_axi_clk, &pfd2_clk);
+	/* set DISPLAY_AXI to 200Mhz */
+	clk_set_parent(&display_axi_clk, &pll1_sw_clk);
 	clk_set_rate(&display_axi_clk, 200000000);
-	clk_disable(&display_axi_clk);
-	clk_disable(&pxp_axi_clk);
-	clk_disable(&elcdif_axi_clk);
-
-	clk_enable(&elcdif_pix_clk);
-	clk_set_parent(&elcdif_pix_clk, &pll1_sw_clk);
-	clk_disable(&elcdif_pix_clk);
-
-	/*
-	 * Enable and set EPDC AXI to 200MHz
-	 * For EPDC AXI, source clocks must be
-	 * enabled before dividers can be changed
-	 */
-	clk_enable(&epdc_axi_clk);
-	clk_set_parent(&epdc_axi_clk, &pfd3_clk);
-	clk_set_rate(&epdc_axi_clk, 200000000);
-	clk_disable(&epdc_axi_clk);
-
-	clk_set_parent(&epdc_pix_clk, &pfd5_clk);
 
 	/* Move SSI clocks to SSI_LP_APM clock */
 	clk_set_parent(&ssi_lp_apm_clk, &lp_apm_clk);
@@ -3425,17 +3011,17 @@ int __init mx50_clocks_init(unsigned long ckil, unsigned long osc, unsigned long
 	reg |= 1 << MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET;
 	__raw_writel(reg, MXC_CCM_CS2CDR);
 
-	/* Change the SSI_EXT1_CLK to be sourced from SSI1_CLK_ROOT */
-	clk_set_parent(&ssi_ext1_clk, &ssi1_clk[0]);
+	/* Change the SSI_EXT1_CLK to be sourced from PLL2 for camera */
+	clk_disable(&ssi_ext1_clk);
+	clk_set_parent(&ssi_ext1_clk, &pll2_sw_clk);
+	clk_set_rate(&ssi_ext1_clk, 24000000);
+	clk_enable(&ssi_ext1_clk);
 	clk_set_parent(&ssi_ext2_clk, &ssi2_clk[0]);
 
 	/* move usb_phy_clk to 24MHz */
 	clk_set_parent(&usb_phy_clk[0], &osc_clk);
 	clk_set_parent(&usb_phy_clk[1], &osc_clk);
 
-	/* move gpmi-nfc to 24MHz */
-	clk_set_parent(&gpmi_nfc_clk[0], &osc_clk);
-
 	/* set SDHC root clock as 200MHZ*/
 	clk_set_rate(&esdhc1_clk[0], 200000000);
 	clk_set_rate(&esdhc3_clk[0], 200000000);
@@ -3510,12 +3096,8 @@ int __init mx50_clocks_init(unsigned long ckil, unsigned long osc, unsigned long
 	clk_set_parent(&uart_main_clk, &lp_apm_clk);
 	clk_set_parent(&gpu2d_clk, &axi_b_clk);
 
-	clk_set_parent(&weim_clk[0], &ahb_clk);
-	clk_set_rate(&weim_clk[0], clk_round_rate(&weim_clk[0], 130000000));
-
-	/* Do the following just to disable the PLL since its not used */
-	clk_enable(&pll3_sw_clk);
-	clk_disable(&pll3_sw_clk);
+	clk_set_parent(&weim_clk, &ahb_clk);
+	clk_set_rate(&weim_clk, clk_round_rate(&weim_clk, 130000000));
 
 	base = ioremap(MX53_BASE_ADDR(GPT1_BASE_ADDR), SZ_4K);
 	mxc_timer_init(&gpt_clk[0], base, MXC_INT_GPT);
diff --git a/arch/arm/mach-mx5/cpu.c b/arch/arm/mach-mx5/cpu.c
index 44440569f041..5abba44d25ad 100644
--- a/arch/arm/mach-mx5/cpu.c
+++ b/arch/arm/mach-mx5/cpu.c
@@ -19,7 +19,6 @@
  * @ingroup MSL_MX51
  */
 
-#include <linux/proc_fs.h>
 #include <linux/types.h>
 #include <linux/err.h>
 #include <linux/kernel.h>
@@ -29,7 +28,6 @@
 #include <linux/clk.h>
 #include <mach/common.h>
 #include <mach/hardware.h>
-#include <asm/mach/map.h>
 
 #define CORTEXA8_PLAT_AMC	0x18
 #define SRPG_NEON_PUPSCR	0x284
@@ -43,12 +41,6 @@
 
 void __iomem *arm_plat_base;
 void __iomem *gpc_base;
-void __iomem *ccm_base;
-void __iomem *databahn_base;
-void *wait_in_iram_base;
-void (*wait_in_iram)(void *ccm_addr, void *databahn_addr);
-
-extern void mx50_wait(u32 ccm_base, u32 databahn_addr);
 
 struct cpu_wp *(*get_cpu_wp)(int *wp);
 void (*set_num_cpu_wp)(int num);
@@ -138,8 +130,6 @@ static int __init post_cpu_init(void)
 	}
 
 	gpc_base = ioremap(MX53_BASE_ADDR(GPC_BASE_ADDR), SZ_4K);
-	ccm_base = ioremap(MX53_BASE_ADDR(CCM_BASE_ADDR), SZ_4K);
-
 	clk_enable(gpcclk);
 
 	/* Setup the number of clock cycles to wait for SRPG
@@ -192,42 +182,6 @@ static int __init post_cpu_init(void)
 		iounmap(base);
 	}
 
-	databahn_base = ioremap(MX50_DATABAHN_BASE_ADDR, SZ_16K);
-
-	if (cpu_is_mx50()) {
-		struct clk *ddr_clk = clk_get(NULL, "ddr_clk");
-		unsigned long iram_paddr;
-
-		iram_alloc(SZ_4K, &iram_paddr);
-		/* Need to remap the area here since we want the memory region
-			 to be executable. */
-		wait_in_iram_base = __arm_ioremap(iram_paddr,
-							SZ_4K, MT_HIGH_VECTORS);
-		memcpy(wait_in_iram_base, mx50_wait, SZ_4K);
-		wait_in_iram = (void *)wait_in_iram_base;
-
-		clk_enable(ddr_clk);
-
-		/* Set the DDR to enter automatic self-refresh. */
-		/* Set the DDR to automatically enter lower power mode 4. */
-		reg = __raw_readl(databahn_base + DATABAHN_CTL_REG22);
-		reg &= ~LOWPOWER_AUTOENABLE_MASK;
-		reg |= 1 << 1;
-		__raw_writel(reg, databahn_base + DATABAHN_CTL_REG22);
-
-		/* set the counter for entering mode 4. */
-		reg = __raw_readl(databahn_base + DATABAHN_CTL_REG21);
-		reg &= ~LOWPOWER_EXTERNAL_CNT_MASK;
-		reg = 128 << LOWPOWER_EXTERNAL_CNT_OFFSET;
-		__raw_writel(reg, databahn_base + DATABAHN_CTL_REG21);
-
-		/* Enable low power mode 4 */
-		reg = __raw_readl(databahn_base + DATABAHN_CTL_REG20);
-		reg &= ~LOWPOWER_CONTROL_MASK;
-		reg |= 1 << 1;
-		__raw_writel(reg, databahn_base + DATABAHN_CTL_REG20);
-		clk_disable(ddr_clk);
-	}
 	return 0;
 }
 
diff --git a/arch/arm/mach-mx5/crm_regs.h b/arch/arm/mach-mx5/crm_regs.h
index b2660a34c0e9..a1444786b72e 100644
--- a/arch/arm/mach-mx5/crm_regs.h
+++ b/arch/arm/mach-mx5/crm_regs.h
@@ -70,56 +70,6 @@
 #define MXC_PLL_DP_DESTAT_TOG_SEL	(1 << 31)
 #define MXC_PLL_DP_DESTAT_MFN		0x07FFFFFF
 
-/* Register addresses of apll and pfd*/
-#define MXC_ANADIG_FRAC0		0x10
-#define MXC_ANADIG_FRAC0_SET		0x14
-#define MXC_ANADIG_FRAC0_CLR		0x18
-#define MXC_ANADIG_FRAC1		0x20
-#define MXC_ANADIG_FRAC1_SET		0x24
-#define MXC_ANADIG_FRAC1_CLR		0x28
-#define MXC_ANADIG_MISC			0x60
-#define MXC_ANADIG_MISC_SET		0x64
-#define MXC_ANADIG_MISC_CLR		0x68
-#define MXC_ANADIG_PLLCTRL		0x70
-#define MXC_ANADIG_PLLCTRL_SET		0x74
-#define MXC_ANADIG_PLLCTRL_CLR		0x78
-
-/* apll and pfd Register Bit definitions */
-
-#define MXC_ANADIG_PFD3_CLKGATE		(1 << 31)
-#define MXC_ANADIG_PFD3_STABLE		(1 << 30)
-#define MXC_ANADIG_PFD3_FRAC_OFFSET	24
-#define MXC_ANADIG_PFD_FRAC_MASK	0x3F
-#define MXC_ANADIG_PFD2_CLKGATE		(1 << 23)
-#define MXC_ANADIG_PFD2_STABLE		(1 << 22)
-#define MXC_ANADIG_PFD2_FRAC_OFFSET	16
-#define MXC_ANADIG_PFD1_CLKGATE		(1 << 15)
-#define MXC_ANADIG_PFD1_STABLE		(1 << 14)
-#define MXC_ANADIG_PFD1_FRAC_OFFSET	8
-#define MXC_ANADIG_PFD0_CLKGATE		(1 << 7)
-#define MXC_ANADIG_PFD0_STABLE		(1 << 6)
-#define MXC_ANADIG_PFD0_FRAC_OFFSET	0
-
-#define MXC_ANADIG_PFD7_CLKGATE		(1 << 31)
-#define MXC_ANADIG_PFD7_STABLE		(1 << 30)
-#define MXC_ANADIG_PFD7_FRAC_OFFSET	24
-#define MXC_ANADIG_PFD6_CLKGATE		(1 << 23)
-#define MXC_ANADIG_PFD6_STABLE		(1 << 22)
-#define MXC_ANADIG_PFD6_FRAC_OFFSET	16
-#define MXC_ANADIG_PFD5_CLKGATE		(1 << 15)
-#define MXC_ANADIG_PFD5_STABLE		(1 << 14)
-#define MXC_ANADIG_PFD5_FRAC_OFFSET	8
-#define MXC_ANADIG_PFD4_CLKGATE		(1 << 7)
-#define MXC_ANADIG_PFD4_STABLE		(1 << 6)
-#define MXC_ANADIG_PFD4_FRAC_OFFSET	0
-
-#define MXC_ANADIG_APLL_LOCK		(1 << 31)
-#define MXC_ANADIG_APLL_FORCE_LOCK	(1 << 30)
-#define MXC_ANADIG_PFD_DIS_OFFSET	16
-#define MXC_ANADIG_PFD_DIS_MASK		0xff
-#define MXC_ANADIG_APLL_LOCK_CNT_OFFSET	0
-#define MXC_ANADIG_APLL_LOCK_CNT_MASK	0xffff
-
 /* Register addresses of CCM*/
 #define MXC_CCM_CCR		(MXC_CCM_BASE + 0x00)
 #define MXC_CCM_CCDR		(MXC_CCM_BASE + 0x04)
@@ -168,11 +118,6 @@
 #define MXC_CCM_BCH		(MXC_CCM_BASE + 0xB0)
 #define MXC_CCM_MSHC_XMSCKI	(MXC_CCM_BASE + 0xB4)
 
-/* CCM Register Offsets. */
-#define MXC_CCM_CDCR_OFFSET		0x4C
-#define MXC_CCM_CACRR_OFFSET		0x10
-#define MXC_CCM_CDHIPR_OFFSET	0x48
-
 /* Define the bits in register CCR */
 #define MXC_CCM_CCR_COSC_EN		(1 << 12)
 #define MXC_CCM_CCR_FPM_MULT_MASK	(1 << 11)
@@ -234,9 +179,7 @@
 #define MXC_CCM_CBCDR_DDR_HF_SEL_OFFSET		(30)
 #define MXC_CCM_CBCDR_DDR_HF_SEL			(0x1 << 30)
 #define MXC_CCM_CBCDR_DDR_PODF_OFFSET		(27)
-#define MXC_CCM_CBCDR_DDR_PODF_MASK		(0x7 << 27)
-#define MX50_CCM_CBCDR_WEIM_PODF_OFFSET	(22)
-#define MX50_CCM_CBCDR_WEIM_PODF_MASK		(0x7 << 22)
+#define MXC_CCM_CBCDR_DDR_PODF_MASK			(0x7 << 27)
 #define MXC_CCM_CBCDR_EMI_PODF_OFFSET		(22)
 #define MXC_CCM_CBCDR_EMI_PODF_MASK			(0x7 << 22)
 #define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET		(19)
@@ -298,8 +241,6 @@
 #define MX50_CCM_CSCMR1_ESDHC1_CLK_SEL_MASK	(0x3 << 21)
 #define MX50_CCM_CSCMR1_ESDHC2_CLK_SEL			(0x1 << 20)
 #define MX50_CCM_CSCMR1_ESDHC4_CLK_SEL			(0x1 << 19)
-#define MX50_CCM_CSCMR1_ESDHC3_CLK_SEL_OFFSET	(16)
-#define MX50_CCM_CSCMR1_ESDHC3_CLK_SEL_MASK		(0x7 << 16)
 #define MXC_CCM_CSCMR1_ESDHC3_MSHC2_CLK_SEL_OFFSET	(16)
 #define MXC_CCM_CSCMR1_ESDHC3_MSHC2_CLK_SEL_MASK		(0x3 << 16)
 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET			(14)
@@ -832,17 +773,6 @@
 #define MXC_CCM_CLKSEQ_BYPASS_BYPASS_DISPLAY_AXI_CLK_SEL_MASK	(0x3 << 2)
 
 
-/* Define the bits in registers CLK_SYS */
-#define MXC_CCM_CLK_SYS_SYS_XTAL_CLKGATE_OFFSET	(30)
-#define MXC_CCM_CLK_SYS_SYS_XTAL_CLKGATE_MASK	(0x3 << 30)
-#define MXC_CCM_CLK_SYS_SYS_PLL_CLKGATE_OFFSET		(28)
-#define MXC_CCM_CLK_SYS_SYS_PLL_CLKGATE_MASK	(0x3 << 28)
-#define MXC_CCM_CLK_SYS_DIV_XTAL_OFFSET			(6)
-#define MXC_CCM_CLK_SYS_DIV_XTAL_MASK			(0xF << 6)
-#define MXC_CCM_CLK_SYS_DIV_PLL_OFFSET			(0)
-#define MXC_CCM_CLK_SYS_DIV_PLL_MASK				(0x3F)
-
-
 /* Define the bits in registers CLK_DDR */
 #define MXC_CCM_CLK_DDR_DDR_CLKGATE_OFFSET	(30)
 #define MXC_CCM_CLK_DDR_DDR_CLKGATE_MASK	(0x3 << 30)
@@ -878,19 +808,6 @@
 #define MXC_CCM_ELCDIFPIX_CLK_PODF_OFFSET	(0)
 #define MXC_CCM_ELCDIFPIX_CLK_PODF_MASK		(0xFFF)
 
-
-/* Define the bits in register GPMI */
-#define MXC_CCM_GPMI_CLKGATE_OFFSET		(30)
-#define MXC_CCM_GPMI_CLKGATE_MASK		(0x3 << 30)
-#define MXC_CCM_GPMI_CLK_DIV_OFFSET		(0)
-#define MXC_CCM_GPMI_CLK_DIV_MASK		(0x3F)
-
-/* Define the bits in register BCH */
-#define MXC_CCM_BCH_CLKGATE_OFFSET		(30)
-#define MXC_CCM_BCH_CLKGATE_MASK		(0x3 << 30)
-#define MXC_CCM_BCH_CLK_DIV_OFFSET		(0)
-#define MXC_CCM_BCH_CLK_DIV_MASK		(0x3F)
-
 #define MXC_GPC_BASE		(IO_ADDRESS(GPC_BASE_ADDR))
 #define MXC_DPTC_LP_BASE	(MXC_GPC_BASE + 0x80)
 #define MXC_DPTC_GP_BASE	(MXC_GPC_BASE + 0x100)
@@ -949,12 +866,11 @@ extern void __iomem *arm_plat_base;
 #define MXC_DVFSPER_PMCR1	(MXC_DVFS_PER_BASE + 0x1C)
 
 /* GPC */
-#define MXC_GPC_CNTR				(MXC_GPC_BASE  + 0x0)
-#define MXC_GPC_PGR				(MXC_GPC_BASE  + 0x4)
-#define MXC_GPC_VCR				(MXC_GPC_BASE  + 0x8)
-#define MXC_GPC_CNTR_OFFSET		0x0
-#define MXC_GPC_PGR_OFFSET		0x4
-#define MXC_GPC_VCR_OFFSET		0x8
+#define MXC_GPC_CNTR		(MXC_GPC_BASE + 0x0)
+#define MXC_GPC_PGR		(MXC_GPC_BASE + 0x4)
+#define MXC_GPC_VCR		(MXC_GPC_BASE + 0x8)
+#define MXC_GPC_ALL_PU		(MXC_GPC_BASE + 0xC)
+#define MXC_GPC_NEON		(MXC_GPC_BASE + 0x10)
 
 /* PGC */
 #define MXC_PGC_IPU_PGCR	(MXC_PGC_IPU_BASE + 0x0)
diff --git a/arch/arm/mach-mx5/devices.c b/arch/arm/mach-mx5/devices.c
index 09188c771c9d..fe842ea8e23d 100644
--- a/arch/arm/mach-mx5/devices.c
+++ b/arch/arm/mach-mx5/devices.c
@@ -23,14 +23,12 @@
 #include <linux/uio_driver.h>
 #include <linux/mxc_scc2_driver.h>
 #include <linux/iram_alloc.h>
-#include <linux/gpmi-nfc.h>
 #include <mach/common.h>
 #include <mach/hardware.h>
 #include <mach/gpio.h>
 #include <mach/sdma.h>
 #include "mx51_pins.h"
 #include "devices.h"
-#include "dma-apbh.h"
 
 /* Flag used to indicate when IRAM has been initialized */
 int iram_ready;
@@ -98,11 +96,6 @@ struct platform_device mxc_keypad_device = {
 	.resource = mxc_kpp_resources,
 };
 
-struct platform_device mxc_powerkey_device = {
-	.name = "mxcpwrkey",
-	.id = 0,
-};
-
 static struct resource rtc_resources[] = {
 	{
 		.start = SRTC_BASE_ADDR,
@@ -149,55 +142,6 @@ struct platform_device mxc_nandv2_mtd_device = {
 	.num_resources = ARRAY_SIZE(mxc_nand_resources),
 };
 
-static struct resource gpmi_nfc_resources[] = {
-	{
-	 .name  = GPMI_NFC_GPMI_REGS_ADDR_RES_NAME,
-	 .flags = IORESOURCE_MEM,
-	 .start = GPMI_BASE_ADDR,
-	 .end   = GPMI_BASE_ADDR + SZ_8K - 1,
-	 },
-	{
-	 .name  = GPMI_NFC_GPMI_INTERRUPT_RES_NAME,
-	 .flags = IORESOURCE_IRQ,
-	 .start = MXC_INT_RAWNAND_GPMI,
-	 .end   = MXC_INT_RAWNAND_GPMI,
-	},
-	{
-	 .name  = GPMI_NFC_BCH_REGS_ADDR_RES_NAME,
-	 .flags = IORESOURCE_MEM,
-	 .start = BCH_BASE_ADDR,
-	 .end   = BCH_BASE_ADDR + SZ_8K - 1,
-	 },
-	{
-	 .name  = GPMI_NFC_BCH_INTERRUPT_RES_NAME,
-	 .flags = IORESOURCE_IRQ,
-	 .start = MXC_INT_RAWNAND_BCH,
-	 .end   = MXC_INT_RAWNAND_BCH,
-	 },
-	{
-	 .name  = GPMI_NFC_DMA_CHANNELS_RES_NAME,
-	 .flags = IORESOURCE_DMA,
-	 .start	= MXS_DMA_CHANNEL_AHB_APBH_GPMI0,
-	 .end	= MXS_DMA_CHANNEL_AHB_APBH_GPMI7,
-	 },
-	{
-	 .name  = GPMI_NFC_DMA_INTERRUPT_RES_NAME,
-	 .flags = IORESOURCE_IRQ,
-	 .start = MXC_INT_APBHDMA_CHAN0,
-	 .end   = MXC_INT_APBHDMA_CHAN7,
-	},
-};
-
-struct platform_device gpmi_nfc_device = {
-	.name = GPMI_NFC_DRIVER_NAME,
-	.id = 0,
-	.dev = {
-		.coherent_dma_mask = DMA_BIT_MASK(32),
-		},
-	.resource = gpmi_nfc_resources,
-	.num_resources = ARRAY_SIZE(gpmi_nfc_resources),
-};
-
 static struct resource imx_nfc_resources[] = {
 	{
 		.flags = IORESOURCE_MEM,
@@ -498,53 +442,6 @@ struct platform_device mxcscc_device = {
 	.resource = scc_resources,
 };
 
-static struct resource dcp_resources[] = {
-
-	{
-		.flags = IORESOURCE_MEM,
-		.start = DCP_BASE_ADDR,
-		.end   = DCP_BASE_ADDR + 0x2000 - 1,
-	}, {
-		.flags = IORESOURCE_IRQ,
-		.start = MXC_INT_DCP_CHAN0,
-		.end = MXC_INT_DCP_CHAN0,
-	}, {
-		.flags = IORESOURCE_IRQ,
-		.start = MXC_INT_DCP_CHAN1_3,
-		.end = MXC_INT_DCP_CHAN1_3,
-	},
-};
-
-struct platform_device dcp_device = {
-	.name = "dcp",
-	.id = 0,
-	.num_resources = ARRAY_SIZE(dcp_resources),
-	.resource = dcp_resources,
-	.dev = {
-		.coherent_dma_mask = DMA_BIT_MASK(32),
-	},
-};
-
-
-static struct resource rngb_resources[] = {
-	{
-		.start = RNGB_BASE_ADDR,
-		.end = RNGB_BASE_ADDR + SZ_4K - 1,
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.start = MXC_INT_RNGB_BLOCK,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-/* the RNGC driver applies for MX50's RNGB hw */
-struct platform_device mxc_rngb_device = {
-	.name = "fsl_rngc",
-	.id = 0,
-	.num_resources = ARRAY_SIZE(rngb_resources),
-	.resource = rngb_resources,
-};
 
 static struct resource mxc_fec_resources[] = {
 	{
@@ -1063,20 +960,6 @@ struct platform_device pata_fsl_device = {
 	},
 };
 
-/* On-Chip OTP device and resource */
-static struct resource otp_resource = {
-	.start	= OCOTP_CTRL_BASE_ADDR,
-	.end 	= OCOTP_CTRL_BASE_ADDR + SZ_8K - 1,
-	.flags 	= IORESOURCE_MEM,
-};
-
-struct platform_device fsl_otp_device = {
-	.name	= "ocotp",
-	.id	= -1,
-	.resource      = &otp_resource,
-	.num_resources = 1,
-};
-
 static struct resource ahci_fsl_resources[] = {
 	{
 		.start = MX53_SATA_BASE_ADDR,
@@ -1102,19 +985,7 @@ struct platform_device ahci_fsl_device = {
 
 static u64 usb_dma_mask = DMA_BIT_MASK(32);
 
-static struct resource usbotg_host_resources[] = {
-	{
-		.start = OTG_BASE_ADDR,
-		.end = OTG_BASE_ADDR + 0x1ff,
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.start = MXC_INT_USB_OTG,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-static struct resource usbotg_udc_resources[] = {
+static struct resource usbotg_resources[] = {
 	{
 		.start = OTG_BASE_ADDR,
 		.end = OTG_BASE_ADDR + 0x1ff,
@@ -1145,8 +1016,8 @@ struct platform_device mxc_usbdr_udc_device = {
 		.dma_mask = &usb_dma_mask,
 		.coherent_dma_mask = DMA_BIT_MASK(32),
 	},
-	.resource      = usbotg_udc_resources,
-	.num_resources = ARRAY_SIZE(usbotg_udc_resources),
+	.resource      = usbotg_resources,
+	.num_resources = ARRAY_SIZE(usbotg_resources),
 };
 
 struct platform_device mxc_usbdr_otg_device = {
@@ -1163,8 +1034,8 @@ struct platform_device mxc_usbdr_otg_device = {
 struct platform_device mxc_usbdr_host_device = {
 	.name = "fsl-ehci",
 	.id = 0,
-	.num_resources = ARRAY_SIZE(usbotg_host_resources),
-	.resource = usbotg_host_resources,
+	.num_resources = ARRAY_SIZE(usbotg_resources),
+	.resource = usbotg_resources,
 	.dev = {
 		.dma_mask = &usb_dma_mask,
 		.coherent_dma_mask = DMA_BIT_MASK(32),
@@ -1405,74 +1276,6 @@ struct platform_device mxc_pxp_client_device = {
 	.id = -1,
 };
 
-static u64 pxp_dma_mask = DMA_BIT_MASK(32);
-struct platform_device mxc_pxp_v4l2 = {
-	.name = "pxp-v4l2",
-	.id = -1,
-	.dev		= {
-		.dma_mask		= &pxp_dma_mask,
-		.coherent_dma_mask	= DMA_BIT_MASK(32),
-	},
-};
-
-struct platform_device mxc_v4l2_device = {
-	.name = "mxc_v4l2_capture",
-	.id = 0,
-};
-
-struct platform_device mxc_v4l2out_device = {
-	.name = "mxc_v4l2_output",
-	.id = 0,
-};
-
-struct resource viim_resources[] = {
-	[0] = {
-		.start  = (GPT1_BASE_ADDR - 0x20000000),
-		.end    = (GPT1_BASE_ADDR - 0x20000000) + PAGE_SIZE - 1,
-		.flags  = IORESOURCE_MEM,
-	},
-	[1] = {
-		.start  = OCOTP_CTRL_BASE_ADDR,
-		.end    = OCOTP_CTRL_BASE_ADDR + PAGE_SIZE - 1,
-		.flags  = IORESOURCE_MEM,
-	},
-};
-struct platform_device mxs_viim = {
-	.name   = "mxs_viim",
-	.id     = -1,
-	.num_resources = ARRAY_SIZE(viim_resources),
-	.resource = viim_resources,
-};
-
-static struct resource dma_apbh_resources[] = {
-	{
-		.start = APBHDMA_BASE_ADDR,
-		.end = APBHDMA_BASE_ADDR + 0x2000 - 1,
-		.flags = IORESOURCE_MEM,
-	},
-};
-
-struct platform_device mxs_dma_apbh_device = {
-	.name = "mxs-dma-apbh",
-	.num_resources = ARRAY_SIZE(dma_apbh_resources),
-	.resource = dma_apbh_resources,
-};
-
-struct platform_device mxc_android_pmem_device = {
-	.name = "android_pmem",
-	.id = 0,
-};
-
-struct platform_device mxc_android_pmem_gpu_device = {
-	.name = "android_pmem",
-	.id = 1,
-};
-
-struct platform_device android_usb_device = {
-	.name   = "android_usb",
-	.id     = -1,
-};
-
 void __init mx5_init_irq(void)
 {
 	unsigned long tzic_addr;
@@ -1731,8 +1534,6 @@ int __init mxc_init_devices(void)
 		scc_resources[0].end -= MX53_OFFSET;
 		scc_resources[1].start = MX53_SCC_RAM_BASE_ADDR;
 		scc_resources[1].end = MX53_SCC_RAM_BASE_ADDR + SZ_16K - 1;
-		rngb_resources[0].start -= MX53_OFFSET;
-		rngb_resources[0].end -= MX53_OFFSET;
 		mxcspi1_resources[0].start -= MX53_OFFSET;
 		mxcspi1_resources[0].end -= MX53_OFFSET;
 		mxcspi2_resources[0].start -= MX53_OFFSET;
@@ -1773,10 +1574,8 @@ int __init mxc_init_devices(void)
 		mxcsdhc2_resources[0].end -= MX53_OFFSET;
 		mxcsdhc3_resources[0].start -= MX53_OFFSET;
 		mxcsdhc3_resources[0].end -= MX53_OFFSET;
-		usbotg_host_resources[0].start -= MX53_OFFSET;
-		usbotg_host_resources[0].end -= MX53_OFFSET;
-		usbotg_udc_resources[0].start -= MX53_OFFSET;
-		usbotg_udc_resources[0].end -= MX53_OFFSET;
+		usbotg_resources[0].start -= MX53_OFFSET;
+		usbotg_resources[0].end -= MX53_OFFSET;
 		usbotg_xcvr_resources[0].start -= MX53_OFFSET;
 		usbotg_xcvr_resources[0].end -= MX53_OFFSET;
 		usbh1_resources[0].start -= MX53_OFFSET;
@@ -1785,20 +1584,10 @@ int __init mxc_init_devices(void)
 		usbh2_resources[0].end -= MX53_OFFSET;
 		mxc_gpu_resources[2].start = MX53_GPU2D_BASE_ADDR;
 		mxc_gpu_resources[2].end = MX53_GPU2D_BASE_ADDR + SZ_4K - 1;
+		mxc_gpu_resources[4].start = MX53_GPU_GMEM_BASE_ADDR;
+		mxc_gpu_resources[4].end = MX53_GPU_GMEM_BASE_ADDR + SZ_256K - 1;
 		mxc_gpu2d_resources[0].start = MX53_GPU2D_BASE_ADDR;
 		mxc_gpu2d_resources[0].end = MX53_GPU2D_BASE_ADDR + SZ_4K - 1;
-		if (cpu_is_mx53()) {
-			mxc_gpu_resources[4].start = MX53_GPU_GMEM_BASE_ADDR;
-			mxc_gpu_resources[4].end = MX53_GPU_GMEM_BASE_ADDR
-						+ SZ_256K - 1;
-		} else {
-			mxc_gpu_resources[1].start = 0;
-			mxc_gpu_resources[1].end = 0;
-			mxc_gpu_resources[3].start = 0;
-			mxc_gpu_resources[3].end = 0;
-			mxc_gpu_resources[4].start = 0;
-			mxc_gpu_resources[4].end = 0;
-		}
 		ipu_resources[0].start = MX53_IPU_CTRL_BASE_ADDR;
 		ipu_resources[0].end = MX53_IPU_CTRL_BASE_ADDR + SZ_128M - 1;
 		mlb_resources[0].start -= MX53_OFFSET;
diff --git a/arch/arm/mach-mx5/devices.h b/arch/arm/mach-mx5/devices.h
index da6c6ac96428..8aaa128c561d 100644
--- a/arch/arm/mach-mx5/devices.h
+++ b/arch/arm/mach-mx5/devices.h
@@ -57,7 +57,6 @@ extern struct platform_device mxcsdhc2_device;
 extern struct platform_device mxcsdhc3_device;
 extern struct platform_device ahci_fsl_device;
 extern struct platform_device pata_fsl_device;
-extern struct platform_device fsl_otp_device;
 extern struct platform_device gpu_device;
 extern struct platform_device mxc_fec_device;
 extern struct platform_device mxc_usbdr_udc_device;
@@ -72,18 +71,5 @@ extern void __init ccwmx51_init_devices ( void );
 extern struct platform_device mxc_nandv2_mtd_device;
 extern struct platform_device mxc_pxp_device;
 extern struct platform_device mxc_pxp_client_device;
-extern struct platform_device mxc_pxp_v4l2;
 extern struct platform_device epdc_device;
 extern struct platform_device elcdif_device;
-extern struct platform_device mxc_v4l2_device;
-extern struct platform_device mxc_v4l2out_device;
-extern struct platform_device mxs_viim;
-extern struct platform_device mxs_dma_apbh_device;
-extern struct platform_device gpmi_nfc_device;
-extern struct platform_device mxc_rngb_device;
-extern struct platform_device dcp_device;
-extern struct platform_device mxc_android_pmem_device;
-extern struct platform_device mxc_android_pmem_gpu_device;
-extern struct platform_device android_usb_device;
-extern struct platform_device mxc_powerkey_device;
-extern struct platform_device ccwmx51js_keys_gpio;
diff --git a/arch/arm/mach-mx5/devices_ccwmx51.c b/arch/arm/mach-mx5/devices_ccwmx51.c
index 27eb3dc32064..bd96da04bc62 100644
--- a/arch/arm/mach-mx5/devices_ccwmx51.c
+++ b/arch/arm/mach-mx5/devices_ccwmx51.c
@@ -55,8 +55,6 @@
 #include "mx51_pins.h"
 #include "displays/displays.h"
 #include <linux/smc911x.h>
-#include <linux/fec.h>
-#include <linux/gpio_keys.h>
 
 #if defined(CONFIG_MTD) || defined(CONFIG_MTD_MODULE)
 #include <linux/mtd/mtd.h>
@@ -523,11 +521,11 @@ struct mxc_dvfs_platform_data dvfs_core_data = {
 	.reg_id = "SW1",
 	.clk1_id = "cpu_clk",
 	.clk2_id = "gpc_dvfs_clk",
-	.gpc_cntr_offset = MXC_GPC_CNTR_OFFSET,
-	.gpc_vcr_offset = MXC_GPC_VCR_OFFSET,
-	.ccm_cdcr_offset = MXC_CCM_CDCR_OFFSET,
-	.ccm_cacrr_offset = MXC_CCM_CACRR_OFFSET,
-	.ccm_cdhipr_offset = MXC_CCM_CDHIPR_OFFSET,
+	.gpc_cntr_reg_addr = MXC_GPC_CNTR,
+	.gpc_vcr_reg_addr = MXC_GPC_VCR,
+	.ccm_cdcr_reg_addr = MXC_CCM_CDCR,
+	.ccm_cacrr_reg_addr = MXC_CCM_CACRR,
+	.ccm_cdhipr_reg_addr = MXC_CCM_CDHIPR,
 	.prediv_mask = 0x1F800,
 	.prediv_offset = 11,
 	.prediv_val = 3,
@@ -561,11 +559,6 @@ struct mxc_dvfsper_data dvfs_per_data = {
 	.lp_low = 1200000,
 };
 
-struct fec_platform_data fec_data = {
-	.phy = PHY_INTERFACE_MODE_MII,
-	.phy_mask = ~1UL,
-};
-
 struct platform_pwm_backlight_data mxc_pwm_backlight_data = {
 	.pwm_id = 0,
 	.max_brightness = 255,
@@ -593,49 +586,6 @@ struct mxc_fb_platform_data mx51_fb_data[2] = {
 	}
 };
 
-#if defined(CONFIG_KEYBOARD_GPIO)
-
-#define GPIO_BUTTON(gpio_num, ev_type, ev_code, act_low, descr)	\
-{								\
-	.gpio		= gpio_num,				\
-	.type		= ev_type,				\
-	.code		= ev_code,				\
-	.active_low	= act_low,				\
-	.desc		= "btn " descr,				\
-}
-
-#define GPIO_BUTTON_LOW(gpio_num, event_code, description)	\
-	GPIO_BUTTON(gpio_num, EV_KEY, event_code, 1, description)
-
-// user key 1
-#if defined(CONFIG_JSCCWMX51_V2)
-#define USER_KEY2_GPIO_NR 70
-#else
-#define USER_KEY2_GPIO_NR 8
-#endif
-// user key 2
-#define USER_KEY1_GPIO_NR 1
-
-static struct gpio_keys_button ccwmx51js_gpio_keys[] = {
-		GPIO_BUTTON_LOW(USER_KEY1_GPIO_NR,	KEY_MENU,	"menu"),
-		GPIO_BUTTON_LOW(USER_KEY2_GPIO_NR,	KEY_HOME,	"home"),
-};
-
-
-struct gpio_keys_platform_data ccwmx51js_gpio_key_info = {
-	.buttons	= ccwmx51js_gpio_keys,
-	.nbuttons	= ARRAY_SIZE(ccwmx51js_gpio_keys),
-};
-
-struct platform_device ccwmx51js_keys_gpio = {
-	.name	= "gpio-keys",
-	.id	= -1,
-	.dev	= {
-		.platform_data	= &ccwmx51js_gpio_key_info,
-	},
-};
-#endif // KEYBOARD_GPIO
-
 #if defined(CONFIG_FB_MXC_SYNC_PANEL) || defined(CONFIG_FB_MXC_SYNC_PANEL_MODULE)
 struct ccwmx51_lcd_pdata plcd_platform_data[2];
 
diff --git a/arch/arm/mach-mx5/devices_ccwmx51.h b/arch/arm/mach-mx5/devices_ccwmx51.h
index 6e53be44a5f5..672bee19a123 100644
--- a/arch/arm/mach-mx5/devices_ccwmx51.h
+++ b/arch/arm/mach-mx5/devices_ccwmx51.h
@@ -28,7 +28,6 @@ extern struct mxc_w1_config mxc_w1_data;
 extern struct mxc_spdif_platform_data mxc_spdif_data;
 extern struct tve_platform_data tve_data;
 extern struct mxc_dvfs_platform_data dvfs_core_data;
-extern struct fec_platform_data fec_data;
 extern struct mxc_dvfsper_data dvfs_per_data;
 extern struct platform_pwm_backlight_data mxc_pwm_backlight_data;
 extern struct mxc_audio_platform_data wm8753_data;
@@ -48,9 +47,5 @@ extern void ccwmx51_set_mod_sn(u32 sn);
 extern void ccwmx51_register_sdio(int interface);
 extern void ccwmx51_init_devices(void);
 extern int ccwmx51_create_sysfs_entries(void);
-extern struct gpio_keys_platform_data ccwmx51js_gpio_key_info;
-extern void ccwmx51_init_devices(void);
-extern int ccwmx51_create_sysfs_entries(void);
-
 
 #endif /* DEVICES_CCWMX51_H_ */
diff --git a/arch/arm/mach-mx5/displays/hdmi_ad9389.h b/arch/arm/mach-mx5/displays/hdmi_ad9389.h
index 2a29cd783b48..b800fca3e9ff 100644
--- a/arch/arm/mach-mx5/displays/hdmi_ad9389.h
+++ b/arch/arm/mach-mx5/displays/hdmi_ad9389.h
@@ -24,6 +24,7 @@ static struct fb_videomode ad9389_1280x720x24 = {
 	.lower_margin	= 3,
 	.hsync_len	= 32,
 	.vsync_len	= 6,
+	.sync		= FB_SYNC_CLK_LAT_FALL,
 };
 
 static struct fb_videomode ad9389_1360x768x24 = {
@@ -38,6 +39,7 @@ static struct fb_videomode ad9389_1360x768x24 = {
 	.lower_margin	= 18,
 	.hsync_len	= 76,
 	.vsync_len	= 6,
+	.sync		= FB_SYNC_CLK_LAT_FALL,
 };
 
 
@@ -53,6 +55,7 @@ static struct fb_videomode ad9389_1366x768x24 = {
 	.lower_margin	= 18,
 	.hsync_len	= 76,
 	.vsync_len	= 6,
+	.sync		= FB_SYNC_CLK_LAT_FALL,
 };
 
 static struct fb_videomode ad9389_1920x1080x24 = {
@@ -67,6 +70,7 @@ static struct fb_videomode ad9389_1920x1080x24 = {
 	.lower_margin 	= 4,
 	.hsync_len 	= 44,
 	.vsync_len 	= 5,
+	.sync		= 0,
 };
 
 static struct fb_videomode ad9389_1024x768x24 = {
diff --git a/arch/arm/mach-mx5/mm.c b/arch/arm/mach-mx5/mm.c
index 21d654298b54..575c49830989 100644
--- a/arch/arm/mach-mx5/mm.c
+++ b/arch/arm/mach-mx5/mm.c
@@ -16,7 +16,6 @@
 #include <mach/hardware.h>
 #include <asm/pgtable.h>
 #include <asm/mach/map.h>
-#include <mach/iomux-v3.h>
 
 /*!
  * @file mach-mx51/mm.c
@@ -61,7 +60,6 @@ void __init mx5_map_io(void)
 {
 	int i;
 
-	mxc_iomux_v3_init(IO_ADDRESS(IOMUXC_BASE_ADDR));
 	/* Fixup the mappings for MX53 */
 	if (cpu_is_mx53() || cpu_is_mx50()) {
 		for (i = 0; i < ARRAY_SIZE(mx5_io_desc); i++)
diff --git a/arch/arm/mach-mx5/mx50_arm2.c b/arch/arm/mach-mx5/mx50_arm2.c
index 13de0971ace4..3a4e8dc3e923 100644
--- a/arch/arm/mach-mx5/mx50_arm2.c
+++ b/arch/arm/mach-mx5/mx50_arm2.c
@@ -44,9 +44,6 @@
 #include <linux/videodev2.h>
 #include <linux/mxcfb.h>
 #include <linux/fec.h>
-#include <linux/gpmi-nfc.h>
-#include <linux/android_pmem.h>
-#include <linux/usb/android.h>
 #include <asm/irq.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
@@ -59,248 +56,29 @@
 #include <mach/gpio.h>
 #include <mach/mmc.h>
 #include <mach/mxc_dvfs.h>
-#include <mach/iomux-mx50.h>
-
+#include "iomux.h"
+#include "mx50_pins.h"
 #include "devices.h"
-#include "crm_regs.h"
 #include "usb.h"
-#include "dma-apbh.h"
-
-#define SD1_WP	(3*32 + 19)	/*GPIO_4_19 */
-#define SD1_CD	(0*32 + 27)	/*GPIO_1_27 */
-#define SD2_WP	(4*32 + 16)	/*GPIO_5_16 */
-#define SD2_CD	(4*32 + 17) /*GPIO_5_17 */
-#define SD3_WP	(4*32 + 28) /*GPIO_5_28 */
-#define SD3_CD	(3*32 + 4) /*GPIO_4_4 */
-#define HP_DETECT	(3*32 + 15)	/*GPIO_4_15 */
-#define PWR_INT		(3*32 + 18)	/*GPIO_4_18 */
-
-#define EPDC_D0		(2*32 + 1)	/*GPIO_3_0 */
-#define EPDC_D1		(2*32 + 2)	/*GPIO_3_1 */
-#define EPDC_D2		(2*32 + 3)	/*GPIO_3_2 */
-#define EPDC_D3		(2*32 + 4)	/*GPIO_3_3 */
-#define EPDC_D4		(2*32 + 5)	/*GPIO_3_4 */
-#define EPDC_D5		(2*32 + 6)	/*GPIO_3_5 */
-#define EPDC_D6		(2*32 + 7)	/*GPIO_3_6 */
-#define EPDC_D7		(2*32 + 8)	/*GPIO_3_7 */
-#define EPDC_GDCLK	(2*32 + 16)	/*GPIO_3_16 */
-#define EPDC_GDSP	(2*32 + 17)	/*GPIO_3_17 */
-#define EPDC_GDOE	(2*32 + 18)	/*GPIO_3_18 */
-#define EPDC_GDRL	(2*32 + 19)	/*GPIO_3_19 */
-#define EPDC_SDCLK	(2*32 + 20)	/*GPIO_3_20 */
-#define EPDC_SDOE	(2*32 + 23)	/*GPIO_3_23 */
-#define EPDC_SDLE	(2*32 + 24)	/*GPIO_3_24 */
-#define EPDC_SDSHR	(2*32 + 26)	/*GPIO_3_26 */
-#define EPDC_BDR0	(3*32 + 23)	/*GPIO_4_23 */
-#define EPDC_SDCE0	(3*32 + 25)	/*GPIO_4_25 */
-#define EPDC_SDCE1	(3*32 + 26)	/*GPIO_4_26 */
-#define EPDC_SDCE2	(3*32 + 27)	/*GPIO_4_27 */
-
-#define EPDC_PMIC_WAKE		(5*32 + 16)	/*GPIO_6_16 */
-#define EPDC_PMIC_INT		(5*32 + 17)	/*GPIO_6_17 */
-#define EPDC_VCOM	(3*32 + 21)	/*GPIO_4_21 */
-#define EPDC_PWRSTAT	(2*32 + 28)	/*GPIO_3_28 */
-#define EPDC_ELCDIF_BACKLIGHT	(1*32 + 18)	/*GPIO_2_18 */
-#define CSPI_CS1	(3*32 + 13)	/*GPIO_4_13 */
-#define CSPI_CS2	(3*32 + 11) /*GPIO_4_11*/
 
+extern void __init mx50_arm2_io_init(void);
 extern int __init mx50_arm2_init_mc13892(void);
 extern struct cpu_wp *(*get_cpu_wp)(int *wp);
 extern void (*set_num_cpu_wp)(int num);
-static int num_cpu_wp = 2;
-
-static struct pad_desc  mx50_armadillo2[] = {
-	/* SD1 */
-	MX50_PAD_ECSPI2_SS0__GPIO_4_19,
-	MX50_PAD_EIM_CRE__GPIO_1_27,
-	MX50_PAD_SD1_CMD__SD1_CMD,
-
-	MX50_PAD_SD1_CLK__SD1_CLK,
-	MX50_PAD_SD1_D0__SD1_D0,
-	MX50_PAD_SD1_D1__SD1_D1,
-	MX50_PAD_SD1_D2__SD1_D2,
-	MX50_PAD_SD1_D3__SD1_D3,
-
-	/* SD2 */
-	MX50_PAD_SD2_CD__GPIO_5_17,
-	MX50_PAD_SD2_WP__GPIO_5_16,
-	MX50_PAD_SD2_CMD__SD2_CMD,
-	MX50_PAD_SD2_CLK__SD2_CLK,
-	MX50_PAD_SD2_D0__SD2_D0,
-	MX50_PAD_SD2_D1__SD2_D1,
-	MX50_PAD_SD2_D2__SD2_D2,
-	MX50_PAD_SD2_D3__SD2_D3,
-	MX50_PAD_SD2_D4__SD2_D4,
-	MX50_PAD_SD2_D5__SD2_D5,
-	MX50_PAD_SD2_D6__SD2_D6,
-	MX50_PAD_SD2_D7__SD2_D7,
-
-	/* SD3 */
-	MX50_PAD_SD3_WP__GPIO_5_28,
-	MX50_PAD_KEY_COL2__GPIO_4_4,
-	MX50_PAD_SD3_CMD__SD3_CMD,
-	MX50_PAD_SD3_CLK__SD3_CLK,
-	MX50_PAD_SD3_D0__SD3_D0,
-	MX50_PAD_SD3_D1__SD3_D1,
-	MX50_PAD_SD3_D2__SD3_D2,
-	MX50_PAD_SD3_D3__SD3_D3,
-	MX50_PAD_SD3_D4__SD3_D4,
-	MX50_PAD_SD3_D5__SD3_D5,
-	MX50_PAD_SD3_D6__SD3_D6,
-	MX50_PAD_SD3_D7__SD3_D7,
-
-	MX50_PAD_SSI_RXD__SSI_RXD,
-	MX50_PAD_SSI_TXD__SSI_TXD,
-	MX50_PAD_SSI_TXC__SSI_TXC,
-	MX50_PAD_SSI_TXFS__SSI_TXFS,
-
-	/* LINE1_DETECT (headphone detect) */
-	MX50_PAD_ECSPI1_SS0__GPIO_4_15,
-
-	/* PWR_INT */
-	MX50_PAD_ECSPI2_MISO__GPIO_4_18,
-
-	/* UART pad setting */
-	MX50_PAD_UART1_TXD__UART1_TXD,
-	MX50_PAD_UART1_RXD__UART1_RXD,
-	MX50_PAD_UART1_CTS__UART1_CTS,
-	MX50_PAD_UART1_RTS__UART1_RTS,
-	MX50_PAD_UART2_TXD__UART2_TXD,
-	MX50_PAD_UART2_RXD__UART2_RXD,
-	MX50_PAD_UART2_CTS__UART2_CTS,
-	MX50_PAD_UART2_RTS__UART2_RTS,
-
-	MX50_PAD_I2C1_SCL__I2C1_SCL,
-	MX50_PAD_I2C1_SDA__I2C1_SDA,
-	MX50_PAD_I2C2_SCL__I2C2_SCL,
-	MX50_PAD_I2C2_SDA__I2C2_SDA,
-	MX50_PAD_I2C3_SCL__I2C3_SCL,
-	MX50_PAD_I2C3_SDA__I2C3_SDA,
-
-	/* EPDC pins */
-	MX50_PAD_EPDC_D0__EPDC_D0,
-	MX50_PAD_EPDC_D1__EPDC_D1,
-	MX50_PAD_EPDC_D2__EPDC_D2,
-	MX50_PAD_EPDC_D3__EPDC_D3,
-	MX50_PAD_EPDC_D4__EPDC_D4,
-	MX50_PAD_EPDC_D5__EPDC_D5,
-	MX50_PAD_EPDC_D6__EPDC_D6,
-	MX50_PAD_EPDC_D7__EPDC_D7,
-	MX50_PAD_EPDC_GDCLK__EPDC_GDCLK,
-	MX50_PAD_EPDC_GDSP__EPDC_GDSP,
-	MX50_PAD_EPDC_GDOE__EPDC_GDOE	,
-	MX50_PAD_EPDC_GDRL__EPDC_GDRL,
-	MX50_PAD_EPDC_SDCLK__EPDC_SDCLK,
-	MX50_PAD_EPDC_SDOE__EPDC_SDOE,
-	MX50_PAD_EPDC_SDLE__EPDC_SDLE,
-	MX50_PAD_EPDC_SDSHR__EPDC_SDSHR,
-	MX50_PAD_EPDC_BDR0__EPDC_BDR0,
-	MX50_PAD_EPDC_SDCE0__EPDC_SDCE0,
-	MX50_PAD_EPDC_SDCE1__EPDC_SDCE1,
-	MX50_PAD_EPDC_SDCE2__EPDC_SDCE2,
-
-	MX50_PAD_EPDC_PWRSTAT__GPIO_3_28,
-	MX50_PAD_EPDC_VCOM0__GPIO_4_21,
-
-	MX50_PAD_DISP_D8__DISP_D8,
-	MX50_PAD_DISP_D9__DISP_D9,
-	MX50_PAD_DISP_D10__DISP_D10,
-	MX50_PAD_DISP_D11__DISP_D11,
-	MX50_PAD_DISP_D12__DISP_D12,
-	MX50_PAD_DISP_D13__DISP_D13,
-	MX50_PAD_DISP_D14__DISP_D14,
-	MX50_PAD_DISP_D15__DISP_D15,
-	MX50_PAD_DISP_RS__ELCDIF_VSYNC,
-
-	/* ELCDIF contrast */
-	MX50_PAD_DISP_BUSY__GPIO_2_18,
-
-	MX50_PAD_DISP_CS__ELCDIF_HSYNC,
-	MX50_PAD_DISP_RD__ELCDIF_EN,
-	MX50_PAD_DISP_WR__ELCDIF_PIXCLK,
-
-	/* EPD PMIC WAKEUP */
-	MX50_PAD_UART4_TXD__GPIO_6_16,
-
-	/* EPD PMIC intr */
-	MX50_PAD_UART4_RXD__GPIO_6_17,
-
-	MX50_PAD_EPITO__USBH1_PWR,
-	/* Need to comment below line if
-	 * one needs to debug owire.
-	 */
-	MX50_PAD_OWIRE__USBH1_OC,
-	MX50_PAD_PWM2__USBOTG_PWR,
-	MX50_PAD_PWM1__USBOTG_OC,
-
-	MX50_PAD_SSI_RXC__FEC_MDIO,
-	MX50_PAD_SSI_RXC__FEC_MDIO,
-	MX50_PAD_DISP_D0__FEC_TXCLK,
-	MX50_PAD_DISP_D1__FEC_RX_ER,
-	MX50_PAD_DISP_D2__FEC_RX_DV,
-	MX50_PAD_DISP_D3__FEC_RXD1,
-	MX50_PAD_DISP_D4__FEC_RXD0,
-	MX50_PAD_DISP_D5__FEC_TX_EN,
-	MX50_PAD_DISP_D6__FEC_TXD1,
-	MX50_PAD_DISP_D7__FEC_TXD0,
-	MX50_PAD_SSI_RXFS__FEC_MDC,
-
-	MX50_PAD_CSPI_SS0__CSPI_SS0,
-	MX50_PAD_ECSPI1_MOSI__CSPI_SS1,
-	MX50_PAD_CSPI_MOSI__CSPI_MOSI,
-	MX50_PAD_CSPI_MISO__CSPI_MISO,
-};
-
-static struct pad_desc  mx50_gpmi_nand[] = {
-	MX50_PIN_EIM_DA8__NANDF_CLE,
-	MX50_PIN_EIM_DA9__NANDF_ALE,
-	MX50_PIN_EIM_DA10__NANDF_CE0,
-	MX50_PIN_EIM_DA11__NANDF_CE1,
-	MX50_PIN_EIM_DA12__NANDF_CE2,
-	MX50_PIN_EIM_DA13__NANDF_CE3,
-	MX50_PIN_EIM_DA14__NANDF_READY,
-	MX50_PIN_EIM_DA15__NANDF_DQS,
-	MX50_PIN_SD3_D4__NANDF_D0,
-	MX50_PIN_SD3_D5__NANDF_D1,
-	MX50_PIN_SD3_D6__NANDF_D2,
-	MX50_PIN_SD3_D7__NANDF_D3,
-	MX50_PIN_SD3_D0__NANDF_D4,
-	MX50_PIN_SD3_D1__NANDF_D5,
-	MX50_PIN_SD3_D2__NANDF_D6,
-	MX50_PIN_SD3_D3__NANDF_D7,
-	MX50_PIN_SD3_CLK__NANDF_RDN,
-	MX50_PIN_SD3_CMD__NANDF_WRN,
-	MX50_PIN_SD3_WP__NANDF_RESETN,
-};
-
-static struct mxc_dvfs_platform_data dvfs_core_data = {
-	.reg_id = "SW1",
-	.clk1_id = "cpu_clk",
-	.clk2_id = "gpc_dvfs_clk",
-	.gpc_cntr_offset = MXC_GPC_CNTR_OFFSET,
-	.gpc_vcr_offset = MXC_GPC_VCR_OFFSET,
-	.ccm_cdcr_offset = MXC_CCM_CDCR_OFFSET,
-	.ccm_cacrr_offset = MXC_CCM_CACRR_OFFSET,
-	.ccm_cdhipr_offset = MXC_CCM_CDHIPR_OFFSET,
-	.prediv_mask = 0x1F800,
-	.prediv_offset = 11,
-	.prediv_val = 3,
-	.div3ck_mask = 0xE0000000,
-	.div3ck_offset = 29,
-	.div3ck_val = 2,
-	.emac_val = 0x08,
-	.upthr_val = 25,
-	.dnthr_val = 9,
-	.pncthr_val = 33,
-	.upcnt_val = 10,
-	.dncnt_val = 10,
-	.delay_time = 30,
-	.num_wp = 2,
-};
+static int num_cpu_wp = 3;
 
 /* working point(wp): 0 - 800MHz; 1 - 166.25MHz; */
 static struct cpu_wp cpu_wp_auto[] = {
 	{
+	 .pll_rate = 1000000000,
+	 .cpu_rate = 1000000000,
+	 .pdf = 0,
+	 .mfi = 10,
+	 .mfd = 11,
+	 .mfn = 5,
+	 .cpu_podf = 0,
+	 .cpu_voltage = 1175000,},
+	{
 	 .pll_rate = 800000000,
 	 .cpu_rate = 800000000,
 	 .pdf = 0,
@@ -308,10 +86,10 @@ static struct cpu_wp cpu_wp_auto[] = {
 	 .mfd = 2,
 	 .mfn = 1,
 	 .cpu_podf = 0,
-	 .cpu_voltage = 1050000,},
+	 .cpu_voltage = 1100000,},
 	{
 	 .pll_rate = 800000000,
-	 .cpu_rate = 160000000,
+	 .cpu_rate = 166250000,
 	 .pdf = 4,
 	 .mfi = 8,
 	 .mfd = 2,
@@ -338,83 +116,12 @@ static struct mxc_w1_config mxc_w1_data = {
 
 static struct fec_platform_data fec_data = {
 	.phy = PHY_INTERFACE_MODE_RMII,
-	.phy_mask = ~1UL,
 };
 
-/* workaround for cspi chipselect pin may not keep correct level when idle */
-static void mx50_arm2_gpio_spi_chipselect_active(int cspi_mode, int status,
-					     int chipselect)
-{
-	switch (cspi_mode) {
-	case 1:
-		break;
-	case 2:
-		break;
-	case 3:
-		switch (chipselect) {
-		case 0x1:
-			{
-			struct pad_desc cspi_ss0 = MX50_PAD_CSPI_SS0__CSPI_SS0;
-			struct pad_desc cspi_cs1 = MX50_PAD_ECSPI1_MOSI__GPIO_4_13;
-
-			/* pull up/down deassert it */
-			mxc_iomux_v3_setup_pad(&cspi_ss0);
-			mxc_iomux_v3_setup_pad(&cspi_cs1);
-
-			gpio_request(CSPI_CS1, "cspi-cs1");
-			gpio_direction_input(CSPI_CS1);
-			}
-			break;
-		case 0x2:
-			{
-			struct pad_desc cspi_ss1 = MX50_PAD_ECSPI1_MOSI__CSPI_SS1;
-			struct pad_desc cspi_ss0 = MX50_PAD_CSPI_SS0__GPIO_4_11;
-
-			/*disable other ss */
-			mxc_iomux_v3_setup_pad(&cspi_ss1);
-			mxc_iomux_v3_setup_pad(&cspi_ss0);
-
-			/* pull up/down deassert it */
-			gpio_request(CSPI_CS2, "cspi-cs2");
-			gpio_direction_input(CSPI_CS2);
-			}
-			break;
-		default:
-			break;
-		}
-		break;
-
-	default:
-		break;
-	}
-}
-
-static void mx50_arm2_gpio_spi_chipselect_inactive(int cspi_mode, int status,
-					       int chipselect)
-{
-	switch (cspi_mode) {
-	case 1:
-		break;
-	case 2:
-		break;
-	case 3:
-		switch (chipselect) {
-		case 0x1:
-			gpio_free(CSPI_CS1);
-			break;
-		case 0x2:
-			gpio_free(CSPI_CS2);
-			break;
-		default:
-			break;
-		}
-		break;
-	default:
-		break;
-	}
-
-}
-
+extern void mx50_arm2_gpio_spi_chipselect_active(int cspi_mode, int status,
+						    int chipselect);
+extern void mx50_arm2_gpio_spi_chipselect_inactive(int cspi_mode, int status,
+						      int chipselect);
 static struct mxc_spi_master mxcspi1_data = {
 	.maxchipselect = 4,
 	.spi_version = 23,
@@ -437,8 +144,6 @@ static struct mxc_srtc_platform_data srtc_data = {
 	.srtc_sec_mode_addr = OCOTP_CTRL_BASE_ADDR + 0x80,
 };
 
-static int z160_version = 1;
-
 #define mV_to_uV(mV) (mV * 1000)
 #define uV_to_mV(uV) (uV / 1000)
 #define V_to_uV(V) (mV_to_uV(V * 1000))
@@ -495,246 +200,7 @@ static struct regulator_init_data max17135_init_data[] __initdata = {
 	},
 };
 
-static void epdc_get_pins(void)
-{
-	/* Claim GPIOs for EPDC pins - used during power up/down */
-	gpio_request(EPDC_D0, "epdc_d0");
-	gpio_request(EPDC_D1, "epdc_d1");
-	gpio_request(EPDC_D2, "epdc_d2");
-	gpio_request(EPDC_D3, "epdc_d3");
-	gpio_request(EPDC_D4, "epdc_d4");
-	gpio_request(EPDC_D5, "epdc_d5");
-	gpio_request(EPDC_D6, "epdc_d6");
-	gpio_request(EPDC_D7, "epdc_d7");
-	gpio_request(EPDC_GDCLK, "epdc_gdclk");
-	gpio_request(EPDC_GDSP, "epdc_gdsp");
-	gpio_request(EPDC_GDOE, "epdc_gdoe");
-	gpio_request(EPDC_GDRL, "epdc_gdrl");
-	gpio_request(EPDC_SDCLK, "epdc_sdclk");
-	gpio_request(EPDC_SDOE, "epdc_sdoe");
-	gpio_request(EPDC_SDLE, "epdc_sdle");
-	gpio_request(EPDC_SDSHR, "epdc_sdshr");
-	gpio_request(EPDC_BDR0, "epdc_bdr0");
-	gpio_request(EPDC_SDCE0, "epdc_sdce0");
-	gpio_request(EPDC_SDCE1, "epdc_sdce1");
-	gpio_request(EPDC_SDCE2, "epdc_sdce2");
-}
-
-static void epdc_put_pins(void)
-{
-	gpio_free(EPDC_D0);
-	gpio_free(EPDC_D1);
-	gpio_free(EPDC_D2);
-	gpio_free(EPDC_D3);
-	gpio_free(EPDC_D4);
-	gpio_free(EPDC_D5);
-	gpio_free(EPDC_D6);
-	gpio_free(EPDC_D7);
-	gpio_free(EPDC_GDCLK);
-	gpio_free(EPDC_GDSP);
-	gpio_free(EPDC_GDOE);
-	gpio_free(EPDC_GDRL);
-	gpio_free(EPDC_SDCLK);
-	gpio_free(EPDC_SDOE);
-	gpio_free(EPDC_SDLE);
-	gpio_free(EPDC_SDSHR);
-	gpio_free(EPDC_BDR0);
-	gpio_free(EPDC_SDCE0);
-	gpio_free(EPDC_SDCE1);
-	gpio_free(EPDC_SDCE2);
-}
-
-static void epdc_enable_pins(void)
-{
-	struct pad_desc epdc_d0 = MX50_PAD_EPDC_D0__EPDC_D0;
-	struct pad_desc epdc_d1 = MX50_PAD_EPDC_D1__EPDC_D1;
-	struct pad_desc epdc_d2 = MX50_PAD_EPDC_D2__EPDC_D2;
-	struct pad_desc epdc_d3 = MX50_PAD_EPDC_D3__EPDC_D3;
-	struct pad_desc epdc_d4 = MX50_PAD_EPDC_D4__EPDC_D4;
-	struct pad_desc epdc_d5 = MX50_PAD_EPDC_D5__EPDC_D5;
-	struct pad_desc epdc_d6 = MX50_PAD_EPDC_D6__EPDC_D6;
-	struct pad_desc epdc_d7 = MX50_PAD_EPDC_D7__EPDC_D7;
-	struct pad_desc epdc_gdclk = MX50_PAD_EPDC_GDCLK__EPDC_GDCLK;
-	struct pad_desc epdc_gdsp = MX50_PAD_EPDC_GDSP__EPDC_GDSP;
-	struct pad_desc epdc_gdoe = MX50_PAD_EPDC_GDOE__EPDC_GDOE;
-	struct pad_desc epdc_gdrl = MX50_PAD_EPDC_GDRL__EPDC_GDRL;
-	struct pad_desc epdc_sdclk = MX50_PAD_EPDC_SDCLK__EPDC_SDCLK;
-	struct pad_desc epdc_sdoe = MX50_PAD_EPDC_SDOE__EPDC_SDOE;
-	struct pad_desc epdc_sdle = MX50_PAD_EPDC_SDLE__EPDC_SDLE;
-	struct pad_desc epdc_sdshr = MX50_PAD_EPDC_SDSHR__EPDC_SDSHR;
-	struct pad_desc epdc_bdr0 = MX50_PAD_EPDC_BDR0__EPDC_BDR0;
-	struct pad_desc epdc_sdce0 = MX50_PAD_EPDC_SDCE0__EPDC_SDCE0;
-	struct pad_desc epdc_sdce1 = MX50_PAD_EPDC_SDCE1__EPDC_SDCE1;
-	struct pad_desc epdc_sdce2 = MX50_PAD_EPDC_SDCE2__EPDC_SDCE2;
-
-	/* Configure MUX settings to enable EPDC use */
-	mxc_iomux_v3_setup_pad(&epdc_d0);
-	mxc_iomux_v3_setup_pad(&epdc_d1);
-	mxc_iomux_v3_setup_pad(&epdc_d2);
-	mxc_iomux_v3_setup_pad(&epdc_d3);
-	mxc_iomux_v3_setup_pad(&epdc_d4);
-	mxc_iomux_v3_setup_pad(&epdc_d5);
-	mxc_iomux_v3_setup_pad(&epdc_d6);
-	mxc_iomux_v3_setup_pad(&epdc_d7);
-	mxc_iomux_v3_setup_pad(&epdc_gdclk);
-	mxc_iomux_v3_setup_pad(&epdc_gdsp);
-	mxc_iomux_v3_setup_pad(&epdc_gdoe);
-	mxc_iomux_v3_setup_pad(&epdc_gdrl);
-	mxc_iomux_v3_setup_pad(&epdc_sdclk);
-	mxc_iomux_v3_setup_pad(&epdc_sdoe);
-	mxc_iomux_v3_setup_pad(&epdc_sdle);
-	mxc_iomux_v3_setup_pad(&epdc_sdshr);
-	mxc_iomux_v3_setup_pad(&epdc_bdr0);
-	mxc_iomux_v3_setup_pad(&epdc_sdce0);
-	mxc_iomux_v3_setup_pad(&epdc_sdce1);
-	mxc_iomux_v3_setup_pad(&epdc_sdce2);
-
-	gpio_direction_input(EPDC_D0);
-	gpio_direction_input(EPDC_D1);
-	gpio_direction_input(EPDC_D2);
-	gpio_direction_input(EPDC_D3);
-	gpio_direction_input(EPDC_D4);
-	gpio_direction_input(EPDC_D5);
-	gpio_direction_input(EPDC_D6);
-	gpio_direction_input(EPDC_D7);
-	gpio_direction_input(EPDC_GDCLK);
-	gpio_direction_input(EPDC_GDSP);
-	gpio_direction_input(EPDC_GDOE);
-	gpio_direction_input(EPDC_GDRL);
-	gpio_direction_input(EPDC_SDCLK);
-	gpio_direction_input(EPDC_SDOE);
-	gpio_direction_input(EPDC_SDLE);
-	gpio_direction_input(EPDC_SDSHR);
-	gpio_direction_input(EPDC_BDR0);
-	gpio_direction_input(EPDC_SDCE0);
-	gpio_direction_input(EPDC_SDCE1);
-	gpio_direction_input(EPDC_SDCE2);
-}
-
-static void epdc_disable_pins(void)
-{
-	struct pad_desc epdc_d0 = MX50_PAD_EPDC_D0__GPIO_3_0;
-	struct pad_desc epdc_d1 = MX50_PAD_EPDC_D1__GPIO_3_1;
-	struct pad_desc epdc_d2 = MX50_PAD_EPDC_D2__GPIO_3_2;
-	struct pad_desc epdc_d3 = MX50_PAD_EPDC_D3__GPIO_3_3;
-	struct pad_desc epdc_d4 = MX50_PAD_EPDC_D4__GPIO_3_4;
-	struct pad_desc epdc_d5 = MX50_PAD_EPDC_D5__GPIO_3_5;
-	struct pad_desc epdc_d6 = MX50_PAD_EPDC_D6__GPIO_3_6;
-	struct pad_desc epdc_d7 = MX50_PAD_EPDC_D7__GPIO_3_7;
-	struct pad_desc epdc_gdclk = MX50_PAD_EPDC_GDCLK__GPIO_3_16;
-	struct pad_desc epdc_gdsp = MX50_PAD_EPDC_GDSP__GPIO_3_17;
-	struct pad_desc epdc_gdoe = MX50_PAD_EPDC_GDOE__GPIO_3_18;
-	struct pad_desc epdc_gdrl = MX50_PAD_EPDC_GDRL__GPIO_3_19;
-	struct pad_desc epdc_sdclk = MX50_PAD_EPDC_SDCLK__GPIO_3_20;
-	struct pad_desc epdc_sdoe = MX50_PAD_EPDC_SDOE__GPIO_3_23;
-	struct pad_desc epdc_sdle = MX50_PAD_EPDC_SDLE__GPIO_3_24;
-	struct pad_desc epdc_sdshr = MX50_PAD_EPDC_SDSHR__GPIO_3_26;
-	struct pad_desc epdc_bdr0 = MX50_PAD_EPDC_BDR0__GPIO_4_23;
-	struct pad_desc epdc_sdce0 = MX50_PAD_EPDC_SDCE0__GPIO_4_25;
-	struct pad_desc epdc_sdce1 = MX50_PAD_EPDC_SDCE1__GPIO_4_26;
-	struct pad_desc epdc_sdce2 = MX50_PAD_EPDC_SDCE2__GPIO_4_27;
-
-	/* Configure MUX settings for EPDC pins to
-	 * GPIO and drive to 0. */
-	mxc_iomux_v3_setup_pad(&epdc_d0);
-	mxc_iomux_v3_setup_pad(&epdc_d1);
-	mxc_iomux_v3_setup_pad(&epdc_d2);
-	mxc_iomux_v3_setup_pad(&epdc_d3);
-	mxc_iomux_v3_setup_pad(&epdc_d4);
-	mxc_iomux_v3_setup_pad(&epdc_d5);
-	mxc_iomux_v3_setup_pad(&epdc_d6);
-	mxc_iomux_v3_setup_pad(&epdc_d7);
-	mxc_iomux_v3_setup_pad(&epdc_gdclk);
-	mxc_iomux_v3_setup_pad(&epdc_gdsp);
-	mxc_iomux_v3_setup_pad(&epdc_gdoe);
-	mxc_iomux_v3_setup_pad(&epdc_gdrl);
-	mxc_iomux_v3_setup_pad(&epdc_sdclk);
-	mxc_iomux_v3_setup_pad(&epdc_sdoe);
-	mxc_iomux_v3_setup_pad(&epdc_sdle);
-	mxc_iomux_v3_setup_pad(&epdc_sdshr);
-	mxc_iomux_v3_setup_pad(&epdc_bdr0);
-	mxc_iomux_v3_setup_pad(&epdc_sdce0);
-	mxc_iomux_v3_setup_pad(&epdc_sdce1);
-	mxc_iomux_v3_setup_pad(&epdc_sdce2);
-
-	gpio_direction_output(EPDC_D0, 0);
-	gpio_direction_output(EPDC_D1, 0);
-	gpio_direction_output(EPDC_D2, 0);
-	gpio_direction_output(EPDC_D3, 0);
-	gpio_direction_output(EPDC_D4, 0);
-	gpio_direction_output(EPDC_D5, 0);
-	gpio_direction_output(EPDC_D6, 0);
-	gpio_direction_output(EPDC_D7, 0);
-	gpio_direction_output(EPDC_GDCLK, 0);
-	gpio_direction_output(EPDC_GDSP, 0);
-	gpio_direction_output(EPDC_GDOE, 0);
-	gpio_direction_output(EPDC_GDRL, 0);
-	gpio_direction_output(EPDC_SDCLK, 0);
-	gpio_direction_output(EPDC_SDOE, 0);
-	gpio_direction_output(EPDC_SDLE, 0);
-	gpio_direction_output(EPDC_SDSHR, 0);
-	gpio_direction_output(EPDC_BDR0, 0);
-	gpio_direction_output(EPDC_SDCE0, 0);
-	gpio_direction_output(EPDC_SDCE1, 0);
-	gpio_direction_output(EPDC_SDCE2, 0);
-}
-
-static struct fb_videomode e60_mode = {
-	.name = "E60",
-	.refresh = 50,
-	.xres = 800,
-	.yres = 600,
-	.pixclock = 20000000,
-	.left_margin = 10,
-	.right_margin = 217,
-	.upper_margin = 4,
-	.lower_margin = 10,
-	.hsync_len = 20,
-	.vsync_len = 4,
-	.sync = 0,
-	.vmode = FB_VMODE_NONINTERLACED,
-	.flag = 0,
-};
-
-static struct fb_videomode e97_mode = {
-	.name = "E97",
-	.refresh = 50,
-	.xres = 1200,
-	.yres = 825,
-	.pixclock = 32000000,
-	.left_margin = 8,
-	.right_margin = 125,
-	.upper_margin = 4,
-	.lower_margin = 17,
-	.hsync_len = 20,
-	.vsync_len = 4,
-	.sync = 0,
-	.vmode = FB_VMODE_NONINTERLACED,
-	.flag = 0,
-};
-
-static struct mxc_epdc_fb_mode panel_modes[] = {
-	{
-		&e60_mode,
-		4, 10, 20, 10, 20, 480, 20, 0, 1, 1,
-	},
-	{
-		&e97_mode,
-		8, 10, 20, 10, 20, 580, 20, 0, 1, 3,
-	},
-};
-
-static struct mxc_epdc_fb_platform_data epdc_data = {
-	.epdc_mode = panel_modes,
-	.num_modes = ARRAY_SIZE(panel_modes),
-	.get_pins = epdc_get_pins,
-	.put_pins = epdc_put_pins,
-	.enable_pins = epdc_enable_pins,
-	.disable_pins = epdc_disable_pins,
-};
-
-
-static struct max17135_platform_data max17135_pdata __initdata = {
+static struct max17135_platform_data max17135_pdata = {
 	.vneg_pwrup = 1,
 	.gvee_pwrup = 1,
 	.vpos_pwrup = 2,
@@ -743,43 +209,13 @@ static struct max17135_platform_data max17135_pdata __initdata = {
 	.vpos_pwrdn = 2,
 	.gvee_pwrdn = 1,
 	.vneg_pwrdn = 1,
-	.gpio_pmic_pwrgood = EPDC_PWRSTAT,
-	.gpio_pmic_vcom_ctrl = EPDC_VCOM,
-	.gpio_pmic_wakeup = EPDC_PMIC_WAKE,
-	.gpio_pmic_intr = EPDC_PMIC_INT,
+	.gpio_pmic_pwrgood = IOMUX_TO_GPIO(MX50_PIN_EPDC_PWRSTAT),
+	.gpio_pmic_vcom_ctrl = IOMUX_TO_GPIO(MX50_PIN_EPDC_VCOM0),
+	.gpio_pmic_wakeup = IOMUX_TO_GPIO(MX50_PIN_UART4_TXD),
+	.gpio_pmic_intr = IOMUX_TO_GPIO(MX50_PIN_UART4_RXD),
 	.regulator_init = max17135_init_data,
 };
 
-static int __initdata max17135_pass_num = { 1 };
-static int __initdata max17135_vcom = { -1250000 };
-/*
- * Parse user specified options (`max17135:')
- * example:
- * 	max17135:pass=2,vcom=-1250000
- */
-static int __init max17135_setup(char *options)
-{
-	char *opt;
-	while ((opt = strsep(&options, ",")) != NULL) {
-		if (!*opt)
-			continue;
-		if (!strncmp(opt, "pass=", 5))
-			max17135_pass_num =
-				simple_strtoul(opt + 5, NULL, 0);
-		if (!strncmp(opt, "vcom=", 5)) {
-			int offs = 5;
-			if (opt[5] == '-')
-				offs = 6;
-			max17135_vcom =
-				simple_strtoul(opt + offs, NULL, 0);
-			max17135_vcom = -max17135_vcom;
-		}
-	}
-	return 1;
-}
-
-__setup("max17135:", max17135_setup);
-
 static struct i2c_board_info mxc_i2c1_board_info[] __initdata = {
 	{
 	 .type = "sgtl5000-i2c",
@@ -836,24 +272,24 @@ static int sdhc_write_protect(struct device *dev)
 	unsigned short rc = 0;
 
 	if (to_platform_device(dev)->id == 0)
-		rc = gpio_get_value(SD1_WP);
+		rc = gpio_get_value(IOMUX_TO_GPIO(MX50_PIN_ECSPI2_SS0));
 	else if (to_platform_device(dev)->id == 1)
-		rc = gpio_get_value(SD2_WP);
+		rc = gpio_get_value(IOMUX_TO_GPIO(MX50_PIN_SD2_WP));
 	else if (to_platform_device(dev)->id == 2)
-		rc = gpio_get_value(SD3_WP);
+		rc = gpio_get_value(IOMUX_TO_GPIO(MX50_PIN_SD3_WP));
 
 	return rc;
 }
 
 static unsigned int sdhc_get_card_det_status(struct device *dev)
 {
-	int ret = 0;
+	int ret;
 	if (to_platform_device(dev)->id == 0)
-		ret = gpio_get_value(SD1_CD);
+		ret = gpio_get_value(IOMUX_TO_GPIO(MX50_PIN_EIM_CRE));
 	else if (to_platform_device(dev)->id == 1)
-		ret = gpio_get_value(SD2_CD);
+		ret = gpio_get_value(IOMUX_TO_GPIO(MX50_PIN_SD2_CD));
 	else if (to_platform_device(dev)->id == 2)
-		ret = gpio_get_value(SD3_CD);
+		ret = gpio_get_value(IOMUX_TO_GPIO(MX50_PIN_KEY_COL2));
 
 	return ret;
 }
@@ -886,16 +322,13 @@ static struct mxc_mmc_platform_data mmc2_data = {
 static struct mxc_mmc_platform_data mmc3_data = {
 	.ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30
 		| MMC_VDD_31_32,
-	.caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA | MMC_CAP_DATA_DDR,
+	.caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
 	.min_clk = 400000,
-	.max_clk = 40000000,
-	.dll_override_en = 1,
-	.dll_delay_cells = 0xc,
+	.max_clk = 50000000,
 	.card_inserted_state = 0,
 	.status = sdhc_get_card_det_status,
 	.wp_status = sdhc_write_protect,
 	.clock_mmc = "esdhc_clk",
-	.clk_always_on = 1,
 };
 
 static int mxc_sgtl5000_amp_enable(int enable)
@@ -906,14 +339,14 @@ static int mxc_sgtl5000_amp_enable(int enable)
 
 static int headphone_det_status(void)
 {
-	return (gpio_get_value(HP_DETECT) != 0);
+	return (gpio_get_value(IOMUX_TO_GPIO(MX50_PIN_ECSPI1_SS0)) != 0);
 }
 
 static struct mxc_audio_platform_data sgtl5000_data = {
 	.ssi_num = 1,
 	.src_port = 2,
 	.ext_port = 3,
-	.hp_irq = IOMUX_TO_IRQ_V3(HP_DETECT),
+	.hp_irq = IOMUX_TO_IRQ(MX50_PIN_ECSPI1_SS0),
 	.hp_status = headphone_det_status,
 	.amp_enable = mxc_sgtl5000_amp_enable,
 	.sysclk = 12288000,
@@ -923,21 +356,64 @@ static struct platform_device mxc_sgtl5000_device = {
 	.name = "imx-3stack-sgtl5000",
 };
 
-static struct pad_desc armadillo2_wvga_pads[] = {
-	MX50_PAD_DISP_D0__DISP_D0,
-	MX50_PAD_DISP_D1__DISP_D1,
-	MX50_PAD_DISP_D2__DISP_D2,
-	MX50_PAD_DISP_D3__DISP_D3,
-	MX50_PAD_DISP_D4__DISP_D4,
-	MX50_PAD_DISP_D5__DISP_D5,
-	MX50_PAD_DISP_D6__DISP_D6,
-	MX50_PAD_DISP_D7__DISP_D7,
-};
-
 static void wvga_reset(void)
 {
-	mxc_iomux_v3_setup_multiple_pads(armadillo2_wvga_pads, \
-				ARRAY_SIZE(armadillo2_wvga_pads));
+	/* ELCDIF D0 */
+	mxc_free_iomux(MX50_PIN_DISP_D0, IOMUX_CONFIG_ALT2);
+	mxc_request_iomux(MX50_PIN_DISP_D0, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX50_PIN_DISP_D0, PAD_CTL_PKE_ENABLE |
+			  PAD_CTL_PUE_KEEPER |
+			  PAD_CTL_ODE_OPENDRAIN_NONE |
+			  PAD_CTL_DRV_HIGH);
+	/* ELCDIF D1 */
+	mxc_free_iomux(MX50_PIN_DISP_D1, IOMUX_CONFIG_ALT2);
+	mxc_request_iomux(MX50_PIN_DISP_D1, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX50_PIN_DISP_D1, PAD_CTL_PKE_ENABLE |
+			  PAD_CTL_PUE_KEEPER |
+			  PAD_CTL_ODE_OPENDRAIN_NONE |
+			  PAD_CTL_DRV_HIGH);
+	/* ELCDIF D2 */
+	mxc_free_iomux(MX50_PIN_DISP_D2, IOMUX_CONFIG_ALT2);
+	mxc_request_iomux(MX50_PIN_DISP_D2, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX50_PIN_DISP_D2, PAD_CTL_PKE_ENABLE |
+			  PAD_CTL_PUE_KEEPER |
+			  PAD_CTL_ODE_OPENDRAIN_NONE |
+			  PAD_CTL_DRV_HIGH);
+	/* ELCDIF D3 */
+	mxc_free_iomux(MX50_PIN_DISP_D3, IOMUX_CONFIG_ALT2);
+	mxc_request_iomux(MX50_PIN_DISP_D3, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX50_PIN_DISP_D3, PAD_CTL_PKE_ENABLE |
+			  PAD_CTL_PUE_KEEPER |
+			  PAD_CTL_ODE_OPENDRAIN_NONE |
+			  PAD_CTL_DRV_HIGH);
+	/* ELCDIF D4 */
+	mxc_free_iomux(MX50_PIN_DISP_D4, IOMUX_CONFIG_ALT2);
+	mxc_request_iomux(MX50_PIN_DISP_D4, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX50_PIN_DISP_D4, PAD_CTL_PKE_ENABLE |
+			  PAD_CTL_PUE_KEEPER |
+			  PAD_CTL_ODE_OPENDRAIN_NONE |
+			  PAD_CTL_DRV_HIGH);
+	/* ELCDIF D5 */
+	mxc_free_iomux(MX50_PIN_DISP_D5, IOMUX_CONFIG_ALT2);
+	mxc_request_iomux(MX50_PIN_DISP_D5, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX50_PIN_DISP_D5, PAD_CTL_PKE_ENABLE |
+			  PAD_CTL_PUE_KEEPER |
+			  PAD_CTL_ODE_OPENDRAIN_NONE |
+			  PAD_CTL_DRV_HIGH);
+	/* ELCDIF D6 */
+	mxc_free_iomux(MX50_PIN_DISP_D6, IOMUX_CONFIG_ALT2);
+	mxc_request_iomux(MX50_PIN_DISP_D6, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX50_PIN_DISP_D6, PAD_CTL_PKE_ENABLE |
+			  PAD_CTL_PUE_KEEPER |
+			  PAD_CTL_ODE_OPENDRAIN_NONE |
+			  PAD_CTL_DRV_HIGH);
+	/* ELCDIF D7 */
+	mxc_free_iomux(MX50_PIN_DISP_D7, IOMUX_CONFIG_ALT2);
+	mxc_request_iomux(MX50_PIN_DISP_D7, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX50_PIN_DISP_D7, PAD_CTL_PKE_ENABLE |
+			  PAD_CTL_PUE_KEEPER |
+			  PAD_CTL_ODE_OPENDRAIN_NONE |
+			  PAD_CTL_DRV_HIGH);
 	return;
 }
 
@@ -970,107 +446,6 @@ static struct mxc_fb_platform_data fb_data[] = {
 	 },
 };
 
-static int __initdata enable_w1 = { 0 };
-static int __init w1_setup(char *__unused)
-{
-	enable_w1 = 1;
-	return cpu_is_mx50();
-}
-
-__setup("w1", w1_setup);
-
-int enable_gpmi_nand = { 0 };
-static int __init gpmi_nand_setup(char *__unused)
-{
-	enable_gpmi_nand = 1;
-	return 1;
-}
-
-__setup("gpmi:nand", gpmi_nand_setup);
-
-static struct mxs_dma_plat_data dma_apbh_data = {
-	.chan_base = MXS_DMA_CHANNEL_AHB_APBH,
-	.chan_num = MXS_MAX_DMA_CHANNELS,
-};
-
-static int gpmi_nfc_platform_init(unsigned int max_chip_count)
-{
-	return !enable_gpmi_nand;
-}
-
-static void gpmi_nfc_platform_exit(unsigned int max_chip_count)
-{
-}
-
-static const char *gpmi_nfc_partition_source_types[] = { "cmdlinepart", 0 };
-
-static struct gpmi_nfc_platform_data  gpmi_nfc_platform_data = {
-	.nfc_version             = 2,
-	.boot_rom_version        = 1,
-	.clock_name              = "gpmi-nfc",
-	.platform_init           = gpmi_nfc_platform_init,
-	.platform_exit           = gpmi_nfc_platform_exit,
-	.min_prop_delay_in_ns    = 5,
-	.max_prop_delay_in_ns    = 9,
-	.max_chip_count          = 2,
-	.boot_area_size_in_bytes = 20 * SZ_1M,
-	.partition_source_types  = gpmi_nfc_partition_source_types,
-	.partitions              = 0,
-	.partition_count         = 0,
-};
-
-static struct android_pmem_platform_data android_pmem_pdata = {
-	.name = "pmem_adsp",
-	.start = 0,
-	.size = SZ_4M,
-	.no_allocator = 0,
-	.cached = PMEM_NONCACHE_NORMAL,
-};
-
-static struct android_pmem_platform_data android_pmem_gpu_pdata = {
-	.name = "pmem_gpu",
-	.start = 0,
-	.size = SZ_32M,
-	.no_allocator = 0,
-	.cached = PMEM_CACHE_ENABLE,
-};
-
-static struct android_usb_platform_data android_usb_pdata = {
-	.vendor_id      = 0x0bb4,
-	.product_id     = 0x0c01,
-	.adb_product_id = 0x0c02,
-	.version        = 0x0100,
-	.product_name   = "Android Phone",
-	.manufacturer_name = "Freescale",
-	.nluns = 3,
-};
-
-/* OTP data */
-/* Building up eight registers's names of a bank */
-#define BANK(a, b, c, d, e, f, g, h)	\
-	{\
-	("HW_OCOTP_"#a), ("HW_OCOTP_"#b), ("HW_OCOTP_"#c), ("HW_OCOTP_"#d), \
-	("HW_OCOTP_"#e), ("HW_OCOTP_"#f), ("HW_OCOTP_"#g), ("HW_OCOTP_"#h) \
-	}
-
-#define BANKS		(5)
-#define BANK_ITEMS	(8)
-static const char *bank_reg_desc[BANKS][BANK_ITEMS] = {
-	BANK(LOCK, CFG0, CFG1, CFG2, CFG3, CFG4, CFG5, CFG6),
-	BANK(MEM0, MEM1, MEM2, MEM3, MEM4, MEM5, GP0, GP1),
-	BANK(SCC0, SCC1, SCC2, SCC3, SCC4, SCC5, SCC6, SCC7),
-	BANK(SRK0, SRK1, SRK2, SRK3, SRK4, SRK5, SRK6, SRK7),
-	BANK(SJC0, SJC1, MAC0, MAC1, HWCAP0, HWCAP1, HWCAP2, SWCAP),
-};
-
-static struct fsl_otp_data otp_data = {
-	.fuse_name	= (char **)bank_reg_desc,
-	.fuse_num	= BANKS * BANK_ITEMS,
-};
-#undef BANK
-#undef BANKS
-#undef BANK_ITEMS
-
 /*!
  * Board specific fixup function. It is called by \b setup_arch() in
  * setup.c file very early on during kernel starts. It allows the user to
@@ -1085,89 +460,10 @@ static struct fsl_otp_data otp_data = {
 static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags,
 				   char **cmdline, struct meminfo *mi)
 {
-	struct tag *t;
-	int size;
-
 	mxc_set_cpu_type(MXC_CPU_MX50);
 
 	get_cpu_wp = mx50_arm2_get_cpu_wp;
 	set_num_cpu_wp = mx50_arm2_set_num_cpu_wp;
-
-	for_each_tag(t, tags) {
-		if (t->hdr.tag != ATAG_MEM)
-			continue;
-		size = t->u.mem.size;
-
-		android_pmem_pdata.start =
-				PHYS_OFFSET + size - android_pmem_pdata.size;
-		android_pmem_gpu_pdata.start =
-				android_pmem_pdata.start - android_pmem_gpu_pdata.size;
-#if 0
-		gpu_device.resource[5].start =
-				android_pmem_gpu_pdata.start - SZ_16M;
-		gpu_device.resource[5].end =
-				gpu_device.resource[5].start + SZ_16M - 1;
-#endif
-		size -= android_pmem_pdata.size;
-		size -= android_pmem_gpu_pdata.size;
-		//size -= SZ_16M;
-		t->u.mem.size = size;
-	}
-}
-
-static void __init mx50_arm2_io_init(void)
-{
-	mxc_iomux_v3_setup_multiple_pads(mx50_armadillo2, \
-			ARRAY_SIZE(mx50_armadillo2));
-
-	gpio_request(SD1_WP, "sdhc1-wp");
-	gpio_direction_input(SD1_WP);
-
-	gpio_request(SD1_CD, "sdhc1-cd");
-	gpio_direction_input(SD1_CD);
-
-	gpio_request(SD2_WP, "sdhc2-wp");
-	gpio_direction_input(SD2_WP);
-
-	gpio_request(SD2_CD, "sdhc2-cd");
-	gpio_direction_input(SD2_CD);
-
-	gpio_request(SD3_WP, "sdhc3-wp");
-	gpio_direction_input(SD3_WP);
-
-	gpio_request(SD3_CD, "sdhc3-cd");
-	gpio_direction_input(SD3_CD);
-
-	gpio_request(HP_DETECT, "hp-det");
-	gpio_direction_input(HP_DETECT);
-
-	gpio_request(PWR_INT, "pwr-int");
-	gpio_direction_input(PWR_INT);
-
-	gpio_request(EPDC_PMIC_WAKE, "epdc-pmic-wake");
-	gpio_direction_output(EPDC_PMIC_WAKE, 0);
-
-	gpio_request(EPDC_VCOM, "epdc-vcom");
-	gpio_direction_output(EPDC_VCOM, 0);
-
-	gpio_request(EPDC_PMIC_INT, "epdc-pmic-int");
-	gpio_direction_input(EPDC_PMIC_INT);
-
-	gpio_request(EPDC_PWRSTAT, "epdc-pwrstat");
-	gpio_direction_input(EPDC_PWRSTAT);
-
-	/* ELCDIF backlight */
-	gpio_request(EPDC_ELCDIF_BACKLIGHT, "elcdif-backlight");
-	gpio_direction_output(EPDC_ELCDIF_BACKLIGHT, 1);
-
-	if (enable_w1) {
-		struct pad_desc one_wire = MX50_PAD_OWIRE__OWIRE;
-		mxc_iomux_v3_setup_pad(&one_wire);
-	}
-
-	if (enable_gpmi_nand)
-		mxc_iomux_v3_setup_multiple_pads(mx50_gpmi_nand, \
-					ARRAY_SIZE(mx50_gpmi_nand));
 }
 
 /*!
@@ -1176,19 +472,18 @@ static void __init mx50_arm2_io_init(void)
 static void __init mxc_board_init(void)
 {
 	/* SD card detect irqs */
-	mxcsdhc1_device.resource[2].start = IOMUX_TO_IRQ_V3(SD1_CD);
-	mxcsdhc1_device.resource[2].end = IOMUX_TO_IRQ_V3(SD1_CD);
-	mxcsdhc2_device.resource[2].start = IOMUX_TO_IRQ_V3(SD2_CD);
-	mxcsdhc2_device.resource[2].end = IOMUX_TO_IRQ_V3(SD2_CD);
-	mxcsdhc3_device.resource[2].start = IOMUX_TO_IRQ_V3(SD3_CD);
-	mxcsdhc3_device.resource[2].end = IOMUX_TO_IRQ_V3(SD3_CD);
+	mxcsdhc1_device.resource[2].start = IOMUX_TO_IRQ(MX50_PIN_EIM_CRE);
+	mxcsdhc1_device.resource[2].end = IOMUX_TO_IRQ(MX50_PIN_EIM_CRE);
+	mxcsdhc2_device.resource[2].start = IOMUX_TO_IRQ(MX50_PIN_SD2_CD);
+	mxcsdhc2_device.resource[2].end = IOMUX_TO_IRQ(MX50_PIN_SD2_CD);
+	mxcsdhc3_device.resource[2].start = IOMUX_TO_IRQ(MX50_PIN_KEY_COL2);
+	mxcsdhc3_device.resource[2].end = IOMUX_TO_IRQ(MX50_PIN_KEY_COL2);
 
 	mxc_cpu_common_init();
 	mxc_register_gpios();
 	mx50_arm2_io_init();
 
 	mxc_register_device(&mxc_dma_device, NULL);
-	//mxc_register_device(&mxs_dma_apbh_device, &dma_apbh_data);
 	mxc_register_device(&mxc_wdt_device, NULL);
 	mxc_register_device(&mxcspi1_device, &mxcspi1_data);
 	mxc_register_device(&mxcspi3_device, &mxcspi3_data);
@@ -1198,15 +493,13 @@ static void __init mxc_board_init(void)
 
 	mxc_register_device(&mxc_rtc_device, &srtc_data);
 	mxc_register_device(&mxc_w1_master_device, &mxc_w1_data);
-	mxc_register_device(&gpu_device, &z160_version);
+	mxc_register_device(&gpu_device, NULL);
 	mxc_register_device(&mxc_pxp_device, NULL);
 	mxc_register_device(&mxc_pxp_client_device, NULL);
-	mxc_register_device(&mxc_pxp_v4l2, NULL);
-	mxc_register_device(&mxc_dvfs_core_device, &dvfs_core_data);
-	mxc_register_device(&busfreq_device, NULL);
-
 	/*
 	mxc_register_device(&mx53_lpmode_device, NULL);
+	mxc_register_device(&busfreq_device, NULL);
+	mxc_register_device(&mxc_dvfs_core_device, &dvfs_core_data);
 	mxc_register_device(&mxc_dvfs_per_device, &dvfs_per_data);
 	*/
 
@@ -1222,32 +515,20 @@ static void __init mxc_board_init(void)
 				ARRAY_SIZE(mxc_dataflash_device));
 	i2c_register_board_info(1, mxc_i2c1_board_info,
 				ARRAY_SIZE(mxc_i2c1_board_info));
-	max17135_pdata.pass_num = max17135_pass_num;
-	max17135_pdata.vcom_uV = max17135_vcom;
 	i2c_register_board_info(2, mxc_i2c2_board_info,
 				ARRAY_SIZE(mxc_i2c2_board_info));
 
-	mxc_register_device(&epdc_device, &epdc_data);
+	mxc_register_device(&epdc_device, NULL);
 	mxc_register_device(&lcd_wvga_device, &lcd_wvga_data);
 	mxc_register_device(&elcdif_device, &fb_data[0]);
-	mxc_register_device(&mxs_viim, NULL);
-
-	mxc_register_device(&mxc_android_pmem_device, &android_pmem_pdata);
-	mxc_register_device(&mxc_android_pmem_gpu_device, &android_pmem_gpu_pdata);
-	mxc_register_device(&android_usb_device, &android_usb_pdata);
 
 	mx50_arm2_init_mc13892();
 /*
 	pm_power_off = mxc_power_off;
 	*/
 	mxc_register_device(&mxc_sgtl5000_device, &sgtl5000_data);
-	mxc_register_device(&gpmi_nfc_device, &gpmi_nfc_platform_data);
 	mx5_usb_dr_init();
 	mx5_usbh1_init();
-
-	mxc_register_device(&mxc_rngb_device, NULL);
-	mxc_register_device(&dcp_device, NULL);
-	mxc_register_device(&fsl_otp_device, &otp_data);
 }
 
 static void __init mx50_arm2_timer_init(void)
diff --git a/arch/arm/mach-mx5/mx50_arm2_gpio.c b/arch/arm/mach-mx5/mx50_arm2_gpio.c
new file mode 100644
index 000000000000..8b37784ef9b5
--- /dev/null
+++ b/arch/arm/mach-mx5/mx50_arm2_gpio.c
@@ -0,0 +1,658 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <linux/errno.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <mach/hardware.h>
+#include <mach/gpio.h>
+
+#include "iomux.h"
+#include "mx50_pins.h"
+
+/*!
+ * @file mach-mx5/mx50_arm2_gpio.c
+ *
+ * @brief This file contains all the GPIO setup functions for the board.
+ *
+ * @ingroup GPIO
+ */
+
+static struct mxc_iomux_pin_cfg __initdata mxc_iomux_pins[] = {
+	{		/* SD1 WP */
+	 MX50_PIN_ECSPI2_SS0, IOMUX_CONFIG_GPIO,
+	 },
+	{		/* SD1 CD */
+	 MX50_PIN_EIM_CRE, IOMUX_CONFIG_GPIO,
+	 },
+	{		/* SD1 CMD */
+	 MX50_PIN_SD1_CMD, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION,
+	 (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST),
+	 },
+	{		/* SD1 CLK */
+	 MX50_PIN_SD1_CLK, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION,
+	 (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST),
+	 },
+	{		/* SD1 D0 */
+	 MX50_PIN_SD1_D0, IOMUX_CONFIG_ALT0,
+	 (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST),
+	 },
+	{		/* SD1 D1 */
+	 MX50_PIN_SD1_D1, IOMUX_CONFIG_ALT0,
+	 (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST),
+	 },
+	{		/* SD1 D2 */
+	 MX50_PIN_SD1_D2, IOMUX_CONFIG_ALT0,
+	 (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST),
+	 },
+	{		/* SD1 D3 */
+	 MX50_PIN_SD1_D3, IOMUX_CONFIG_ALT0,
+	 (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST),
+	 },
+	{		/* SD2 CD */
+	 MX50_PIN_SD2_CD, IOMUX_CONFIG_GPIO,
+	 (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST),
+	 },
+	{		/* SD2 WP */
+	 MX50_PIN_SD2_WP, IOMUX_CONFIG_GPIO,
+	 },
+	{		/* SD2 CMD */
+	 MX50_PIN_SD2_CMD, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION,
+	 (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST),
+	 },
+	{		/* SD2 CLK */
+	 MX50_PIN_SD2_CLK, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION,
+	 (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST),
+	 },
+	{		/* SD2 D0 */
+	 MX50_PIN_SD2_D0, IOMUX_CONFIG_ALT0,
+	 (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST),
+	 },
+	{		/* SD2 D1 */
+	 MX50_PIN_SD2_D1, IOMUX_CONFIG_ALT0,
+	 (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST),
+	 },
+	{		/* SD2 D2 */
+	 MX50_PIN_SD2_D2, IOMUX_CONFIG_ALT0,
+	 (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST),
+	 },
+	{		/* SD2 D3 */
+	 MX50_PIN_SD2_D3, IOMUX_CONFIG_ALT0,
+	 (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST),
+	 },
+	{		/* SD2 D4 */
+	 MX50_PIN_SD2_D4, IOMUX_CONFIG_ALT0,
+	 (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST),
+	 },
+	{		/* SD2 D5 */
+	 MX50_PIN_SD2_D5, IOMUX_CONFIG_ALT0,
+	 (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST),
+	 },
+	{		/* SD2 D6 */
+	 MX50_PIN_SD2_D6, IOMUX_CONFIG_ALT0,
+	 (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST),
+	 },
+	{		/* SD2 D7 */
+	 MX50_PIN_SD2_D7, IOMUX_CONFIG_ALT0,
+	 (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST),
+	 },
+	{		/* SD3 CD */
+	 MX50_PIN_KEY_COL2, IOMUX_CONFIG_GPIO,
+	 (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST),
+	 },
+	{		/* SD3 WP */
+	 MX50_PIN_SD3_WP, IOMUX_CONFIG_GPIO,
+	 },
+	{		/* SD3 CMD */
+	 MX50_PIN_SD3_CMD, IOMUX_CONFIG_ALT0,
+	 (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
+	 PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH),
+	 },
+	{		/* SD3 CLK */
+	 MX50_PIN_SD3_CLK, IOMUX_CONFIG_ALT0,
+	 (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | PAD_CTL_47K_PU |
+	 PAD_CTL_DRV_HIGH),
+	 },
+	{		/* SD3 D0 */
+	 MX50_PIN_SD3_D0, IOMUX_CONFIG_ALT0,
+	 (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
+	 PAD_CTL_47K_PU | PAD_CTL_DRV_HIGH),
+	 },
+	{		/* SD3 D1 */
+	 MX50_PIN_SD3_D1, IOMUX_CONFIG_ALT0,
+	 (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
+	 PAD_CTL_47K_PU | PAD_CTL_DRV_HIGH),
+	 },
+	{		/* SD3 D2 */
+	 MX50_PIN_SD3_D2, IOMUX_CONFIG_ALT0,
+	 (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
+	 PAD_CTL_47K_PU | PAD_CTL_DRV_HIGH),
+	 },
+	{		/* SD3 D3 */
+	 MX50_PIN_SD3_D3, IOMUX_CONFIG_ALT0,
+	 (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
+	 PAD_CTL_47K_PU | PAD_CTL_DRV_HIGH),
+	 },
+	{		/* SD3 D4 */
+	 MX50_PIN_SD3_D4, IOMUX_CONFIG_ALT0,
+	 (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
+	 PAD_CTL_47K_PU | PAD_CTL_DRV_HIGH),
+	 },
+	{		/* SD3 D5 */
+	 MX50_PIN_SD3_D5, IOMUX_CONFIG_ALT0,
+	 (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
+	 PAD_CTL_47K_PU | PAD_CTL_DRV_HIGH),
+	 },
+	{		/* SD3 D6 */
+	 MX50_PIN_SD3_D6, IOMUX_CONFIG_ALT0,
+	 (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
+	 PAD_CTL_47K_PU | PAD_CTL_DRV_HIGH),
+	 },
+	{		/* SD3 D7 */
+	 MX50_PIN_SD3_D7, IOMUX_CONFIG_ALT0,
+	 (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
+	 PAD_CTL_47K_PU | PAD_CTL_DRV_HIGH),
+	 },
+
+	{
+	 MX50_PIN_SSI_TXD, IOMUX_CONFIG_ALT0,
+	 },
+	{
+	 MX50_PIN_SSI_RXD, IOMUX_CONFIG_ALT0,
+	 },
+	{
+	 MX50_PIN_SSI_TXC, IOMUX_CONFIG_ALT0,
+	 },
+	{
+	 MX50_PIN_SSI_TXFS, IOMUX_CONFIG_ALT0,
+	 },
+	/* LINE1_DETECT (headphone detect) */
+	{
+	 MX50_PIN_ECSPI1_SS0, IOMUX_CONFIG_GPIO, PAD_CTL_100K_PU,
+	 },
+	{
+	 MX50_PIN_ECSPI2_MISO, IOMUX_CONFIG_GPIO, PAD_CTL_100K_PU,
+	 },
+	 /* UART pad setting */
+	{
+	 MX50_PIN_UART1_TXD, IOMUX_CONFIG_ALT0,
+	 (PAD_CTL_DRV_HIGH | PAD_CTL_PUE_KEEPER |
+	 PAD_CTL_PKE_ENABLE | PAD_CTL_ODE_OPENDRAIN_NONE),
+	 },
+	{
+	 MX50_PIN_UART1_RXD, IOMUX_CONFIG_ALT0,
+	 (PAD_CTL_DRV_HIGH | PAD_CTL_PUE_KEEPER |
+	 PAD_CTL_PKE_ENABLE | PAD_CTL_ODE_OPENDRAIN_NONE),
+	 MUX_IN_UART1_IPP_UART_RXD_MUX_SELECT_INPUT,
+	 INPUT_CTL_PATH1,
+	},
+	{
+	 MX50_PIN_UART1_CTS, IOMUX_CONFIG_ALT0,
+	 (PAD_CTL_DRV_HIGH | PAD_CTL_PUE_KEEPER |
+	 PAD_CTL_PKE_ENABLE | PAD_CTL_ODE_OPENDRAIN_NONE),
+	 },
+	{
+	 MX50_PIN_UART1_RTS, IOMUX_CONFIG_ALT0,
+	 (PAD_CTL_DRV_HIGH | PAD_CTL_PUE_KEEPER |
+	 PAD_CTL_PKE_ENABLE | PAD_CTL_ODE_OPENDRAIN_NONE),
+	  MUX_IN_UART1_IPP_UART_RTS_B_SELECT_INPUT,
+	 INPUT_CTL_PATH1,
+	},
+	{
+	 MX50_PIN_UART2_TXD, IOMUX_CONFIG_ALT0,
+	 (PAD_CTL_DRV_HIGH | PAD_CTL_PUE_KEEPER |
+	 PAD_CTL_PKE_ENABLE | PAD_CTL_ODE_OPENDRAIN_NONE),
+	 },
+	{
+	 MX50_PIN_UART2_RXD, IOMUX_CONFIG_ALT0,
+	 (PAD_CTL_DRV_HIGH | PAD_CTL_PUE_KEEPER |
+	 PAD_CTL_PKE_ENABLE | PAD_CTL_ODE_OPENDRAIN_NONE),
+	 MUX_IN_UART2_IPP_UART_RXD_MUX_SELECT_INPUT,
+	 INPUT_CTL_PATH1,
+	},
+	{
+	 MX50_PIN_UART2_CTS, IOMUX_CONFIG_ALT0,
+	 (PAD_CTL_DRV_HIGH | PAD_CTL_PUE_KEEPER |
+	 PAD_CTL_PKE_ENABLE | PAD_CTL_ODE_OPENDRAIN_NONE),
+	 },
+	{
+	 MX50_PIN_UART2_RTS, IOMUX_CONFIG_ALT0,
+	 (PAD_CTL_DRV_HIGH | PAD_CTL_PUE_KEEPER |
+	 PAD_CTL_PKE_ENABLE | PAD_CTL_ODE_OPENDRAIN_NONE),
+	 MUX_IN_UART2_IPP_UART_RTS_B_SELECT_INPUT,
+	 INPUT_CTL_PATH1,
+	},
+	{ /* I2C1 SDA */
+	 MX50_PIN_I2C1_SDA, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION,
+	 (PAD_CTL_SRE_FAST | PAD_CTL_ODE_OPENDRAIN_ENABLE |
+	 PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
+	 PAD_CTL_HYS_ENABLE),
+	 },
+	{ /* I2C1 SCL */
+	 MX50_PIN_I2C1_SCL, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION,
+	 (PAD_CTL_SRE_FAST | PAD_CTL_ODE_OPENDRAIN_ENABLE |
+	 PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
+	 PAD_CTL_HYS_ENABLE),
+	 },
+	{ /* I2C2 SDA */
+	 MX50_PIN_I2C2_SDA, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION,
+	 (PAD_CTL_SRE_FAST | PAD_CTL_ODE_OPENDRAIN_ENABLE |
+	 PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
+	 PAD_CTL_HYS_ENABLE),
+	 },
+	{ /* I2C2 SCL */
+	 MX50_PIN_I2C2_SCL, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION,
+	 (PAD_CTL_SRE_FAST | PAD_CTL_ODE_OPENDRAIN_ENABLE |
+	 PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
+	 PAD_CTL_HYS_ENABLE),
+	 },
+	{ /* I2C3 SDA */
+	 MX50_PIN_I2C3_SDA, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION,
+	 (PAD_CTL_SRE_FAST | PAD_CTL_ODE_OPENDRAIN_ENABLE |
+	 PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
+	 PAD_CTL_HYS_ENABLE),
+	 },
+	{ /* I2C3 SCL */
+	 MX50_PIN_I2C3_SCL, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION,
+	 (PAD_CTL_SRE_FAST | PAD_CTL_ODE_OPENDRAIN_ENABLE |
+	 PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
+	 PAD_CTL_HYS_ENABLE),
+	 },
+	 /* EPDC pins */
+	{ /* EPDC D0 */
+	 MX50_PIN_EPDC_D0, IOMUX_CONFIG_ALT0,
+	 },
+	{ /* EPDC D1 */
+	 MX50_PIN_EPDC_D1, IOMUX_CONFIG_ALT0,
+	 },
+	{ /* EPDC D2 */
+	 MX50_PIN_EPDC_D2, IOMUX_CONFIG_ALT0,
+	 },
+	{ /* EPDC D3 */
+	 MX50_PIN_EPDC_D3, IOMUX_CONFIG_ALT0,
+	 },
+	{ /* EPDC D4 */
+	 MX50_PIN_EPDC_D4, IOMUX_CONFIG_ALT0,
+	 },
+	{ /* EPDC D5 */
+	 MX50_PIN_EPDC_D5, IOMUX_CONFIG_ALT0,
+	 },
+	{ /* EPDC D6 */
+	 MX50_PIN_EPDC_D6, IOMUX_CONFIG_ALT0,
+	 },
+	{ /* EPDC D7 */
+	 MX50_PIN_EPDC_D7, IOMUX_CONFIG_ALT0,
+	 },
+	{ /* EPDC GDCLK */
+	 MX50_PIN_EPDC_GDCLK, IOMUX_CONFIG_ALT0,
+	 },
+	{ /* EPDC GDSP */
+	 MX50_PIN_EPDC_GDSP, IOMUX_CONFIG_ALT0,
+	 },
+	{ /* EPDC GDOE */
+	 MX50_PIN_EPDC_GDOE, IOMUX_CONFIG_ALT0,
+	 },
+	{ /* EPDC GDRL */
+	 MX50_PIN_EPDC_GDRL, IOMUX_CONFIG_ALT0,
+	 },
+	{ /* EPDC SDCLK */
+	 MX50_PIN_EPDC_SDCLK, IOMUX_CONFIG_ALT0,
+	 },
+	{ /* EPDC SDOE */
+	 MX50_PIN_EPDC_SDOE, IOMUX_CONFIG_ALT0,
+	 },
+	{ /* EPDC SDLE */
+	 MX50_PIN_EPDC_SDLE, IOMUX_CONFIG_ALT0,
+	 },
+	{ /* EPDC SDSHR */
+	 MX50_PIN_EPDC_SDSHR, IOMUX_CONFIG_ALT0,
+	 },
+	{ /* EPDC BDR0 */
+	 MX50_PIN_EPDC_BDR0, IOMUX_CONFIG_ALT0,
+	 },
+	{ /* EPDC SDCE0 */
+	 MX50_PIN_EPDC_SDCE0, IOMUX_CONFIG_ALT0,
+	 },
+	{ /* EPDC SDCE1 */
+	 MX50_PIN_EPDC_SDCE1, IOMUX_CONFIG_ALT0,
+	 },
+	{ /* EPDC SDCE2 */
+	 MX50_PIN_EPDC_SDCE2, IOMUX_CONFIG_ALT0,
+	 },
+	 /* EPD PMIC pins */
+	{ /* EPDC PWRSTAT - GPIO3[28] for PWR_GOOD status */
+	 MX50_PIN_EPDC_PWRSTAT, IOMUX_CONFIG_ALT1,
+	 },
+	{ /* EPDC VCOM0 - GPIO4[21] for VCOM control */
+	 MX50_PIN_EPDC_VCOM0, IOMUX_CONFIG_ALT1,
+	 },
+	{ /* ELCDIF D8 */
+	 MX50_PIN_DISP_D8, IOMUX_CONFIG_ALT0,
+	 (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+	  PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_DRV_HIGH),
+	 },
+	{ /* ELCDIF D9 */
+	 MX50_PIN_DISP_D9, IOMUX_CONFIG_ALT0,
+	 (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+	  PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_DRV_HIGH),
+	 },
+	{ /* ELCDIF D10 */
+	 MX50_PIN_DISP_D10, IOMUX_CONFIG_ALT0,
+	 (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+	  PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_DRV_HIGH),
+	 },
+	{ /* ELCDIF D11 */
+	 MX50_PIN_DISP_D11, IOMUX_CONFIG_ALT0,
+	 (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+	  PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_DRV_HIGH),
+	 },
+	{ /* ELCDIF D12 */
+	 MX50_PIN_DISP_D12, IOMUX_CONFIG_ALT0,
+	 (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+	  PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_DRV_HIGH),
+	 },
+	{ /* ELCDIF D13 */
+	 MX50_PIN_DISP_D13, IOMUX_CONFIG_ALT0,
+	 (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+	  PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_DRV_HIGH),
+	 },
+	{ /* ELCDIF D14 */
+	 MX50_PIN_DISP_D14, IOMUX_CONFIG_ALT0,
+	 (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+	  PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_DRV_HIGH),
+	 },
+	{ /* ELCDIF D15 */
+	 MX50_PIN_DISP_D15, IOMUX_CONFIG_ALT0,
+	 (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+	  PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_DRV_HIGH),
+	 },
+	{ /* ELCDIF VSYNC */
+	 MX50_PIN_DISP_RS, IOMUX_CONFIG_ALT2,
+	 (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+	  PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_DRV_HIGH),
+	 },
+	{ /* ELCDIF contrast */
+	 MX50_PIN_DISP_BUSY, IOMUX_CONFIG_ALT1,
+	 (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+	  PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_DRV_HIGH),
+	 },
+	{ /* ELCDIF HSYNC */
+	 MX50_PIN_DISP_CS, IOMUX_CONFIG_ALT2,
+	 (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+	  PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_DRV_HIGH),
+	 },
+	{ /* ELCDIF DRDY */
+	 MX50_PIN_DISP_RD, IOMUX_CONFIG_ALT2,
+	 (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+	  PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_DRV_HIGH),
+	 },
+	{ /* ELCDIF PIXCLK */
+	 MX50_PIN_DISP_WR, IOMUX_CONFIG_ALT2,
+	 (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+	  PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_DRV_HIGH),
+	 },
+	{ /* UART4 TXD - GPIO6[16] for EPD PMIC WAKEUP */
+	 MX50_PIN_UART4_TXD, IOMUX_CONFIG_ALT1,
+	 },
+	{ /* UART4 RXD - GPIO6[17] for EPD PMIC intr */
+	 MX50_PIN_UART4_RXD, IOMUX_CONFIG_ALT1,
+	 },
+	/* USB_H1_PWR */
+	{
+	 MX50_PIN_EPITO, IOMUX_CONFIG_ALT2,
+	 PAD_CTL_PKE_ENABLE | PAD_CTL_DRV_HIGH,
+	},
+	/* FIXME: USB_H1_OC, need to comment below line if
+	 * one needs to debug owire.
+	 */
+	{
+	 MX50_PIN_OWIRE, IOMUX_CONFIG_ALT2,
+	 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU,
+	},
+	/* USB_OTG_PWR */
+	{
+	 MX50_PIN_PWM2, IOMUX_CONFIG_ALT2,
+	 PAD_CTL_PKE_ENABLE | PAD_CTL_DRV_HIGH,
+	},
+	/*
+	 * Set USB_OTG_OC, the pad value is the default value
+	 * according to IC suggestion.
+	 */
+	{
+	 MX50_PIN_PWM1, IOMUX_CONFIG_ALT2,
+	 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU,
+	 MUX_IN_USBOH1_IPP_IND_OTG_OC_SELECT_INPUT, INPUT_CTL_PATH1,
+	},
+	{ /* FEC_MDIO */
+	 MX50_PIN_SSI_RXC, IOMUX_CONFIG_ALT6,
+	 (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
+	  PAD_CTL_22K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE | PAD_CTL_DRV_HIGH),
+	 MUX_IN_FEC_FEC_MDI_SELECT_INPUT,
+	 INPUT_CTL_PATH1,
+	 },
+	{ /* FEC_TX_CLK */
+	 MX50_PIN_DISP_D0, IOMUX_CONFIG_ALT2,
+	 (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE),
+	 },
+	{ /* FEC_RX_ER */
+	 MX50_PIN_DISP_D1, IOMUX_CONFIG_ALT2,
+	 (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE),
+	 MUX_IN_FEC_FEC_RX_ER_SELECT_INPUT,
+	 INPUT_CTL_PATH0,
+	 },
+	{ /* FEC_CRS_DV */
+	 MX50_PIN_DISP_D2, IOMUX_CONFIG_ALT2,
+	 (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE),
+	 MUX_IN_FEC_FEC_RX_DV_SELECT_INPUT,
+	 INPUT_CTL_PATH0,
+	 },
+	{ /* FEC_RXD1 */
+	 MX50_PIN_DISP_D3, IOMUX_CONFIG_ALT2,
+	 (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE),
+	 MUX_IN_FEC_FEC_RDATA_1_SELECT_INPUT,
+	 INPUT_CTL_PATH0,
+	 },
+	{ /* FEC_RXD0 */
+	 MX50_PIN_DISP_D4, IOMUX_CONFIG_ALT2,
+	(PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE),
+	 MUX_IN_FEC_FEC_RDATA_0_SELECT_INPUT,
+	 INPUT_CTL_PATH0,
+	 },
+	{ /* FEC_TX_EN */
+	 MX50_PIN_DISP_D5, IOMUX_CONFIG_ALT2,
+	 PAD_CTL_DRV_HIGH,
+	 },
+	{ /* FEC_TXD1 */
+	 MX50_PIN_DISP_D6, IOMUX_CONFIG_ALT2,
+	 PAD_CTL_DRV_HIGH,
+	 },
+	{ /* FEC_TXD0 */
+	 MX50_PIN_DISP_D7, IOMUX_CONFIG_ALT2,
+	 PAD_CTL_DRV_HIGH,
+	 },
+	{ /* FEC_MDC */
+	 MX50_PIN_SSI_RXFS, IOMUX_CONFIG_ALT6,
+	 PAD_CTL_DRV_HIGH,
+	 },
+	{ /* CSPI SS0 */
+	 MX50_PIN_CSPI_SS0, IOMUX_CONFIG_ALT0,
+	 (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH),
+	 },
+	{ /* CSPI SS1 */
+	 MX50_PIN_ECSPI1_MOSI, IOMUX_CONFIG_ALT2,
+	 (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
+	  PAD_CTL_22K_PU | PAD_CTL_DRV_HIGH),
+	 },
+	{
+	 MX50_PIN_CSPI_MOSI, IOMUX_CONFIG_ALT0,
+	 },
+	{
+	 MX50_PIN_CSPI_MISO, IOMUX_CONFIG_ALT0,
+	 },
+	{
+	 MX50_PIN_CSPI_SCLK, IOMUX_CONFIG_ALT0,
+	 },
+};
+
+static int __initdata enable_w1 = { 0 };
+static int __init w1_setup(char *__unused)
+{
+	enable_w1 = 1;
+	return cpu_is_mx50();
+}
+
+__setup("w1", w1_setup);
+
+void __init mx50_arm2_io_init(void)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(mxc_iomux_pins); i++) {
+		mxc_request_iomux(mxc_iomux_pins[i].pin,
+				  mxc_iomux_pins[i].mux_mode);
+		if (mxc_iomux_pins[i].pad_cfg)
+			mxc_iomux_set_pad(mxc_iomux_pins[i].pin,
+					  mxc_iomux_pins[i].pad_cfg);
+		if (mxc_iomux_pins[i].in_select)
+			mxc_iomux_set_input(mxc_iomux_pins[i].in_select,
+					    mxc_iomux_pins[i].in_mode);
+	}
+
+	/* SD1 WP */
+	gpio_request(IOMUX_TO_GPIO(MX50_PIN_ECSPI2_SS0), "ecspi2_ss0");
+	gpio_direction_input(IOMUX_TO_GPIO(MX50_PIN_ECSPI2_SS0));
+
+	/* SD1 CD */
+	gpio_request(IOMUX_TO_GPIO(MX50_PIN_EIM_CRE), "eim_cre");
+	gpio_direction_input(IOMUX_TO_GPIO(MX50_PIN_EIM_CRE));
+
+	/* SD2 WP */
+	gpio_request(IOMUX_TO_GPIO(MX50_PIN_SD2_WP), "sd2_wp");
+	gpio_direction_input(IOMUX_TO_GPIO(MX50_PIN_SD2_WP));
+
+	/* SD2 CD */
+	gpio_request(IOMUX_TO_GPIO(MX50_PIN_SD2_CD), "sd2_cd");
+	gpio_direction_input(IOMUX_TO_GPIO(MX50_PIN_SD2_CD));
+
+	/* SD3 WP */
+	gpio_request(IOMUX_TO_GPIO(MX50_PIN_SD3_WP), "sd3_wp");
+	gpio_direction_input(IOMUX_TO_GPIO(MX50_PIN_SD2_WP));
+
+	/* SD3 CD */
+	gpio_request(IOMUX_TO_GPIO(MX50_PIN_KEY_COL2), "key_col2");
+	gpio_direction_input(IOMUX_TO_GPIO(MX50_PIN_KEY_COL2));
+
+	/* LINE1_DETECT (headphone detect) */
+	gpio_direction_input(IOMUX_TO_GPIO(MX50_PIN_ECSPI1_SS0));
+
+	gpio_direction_input(IOMUX_TO_GPIO(MX50_PIN_ECSPI2_MISO));
+
+	/* EPDC PMIC */
+	gpio_request(IOMUX_TO_GPIO(MX50_PIN_UART4_TXD), "uart4_txd");
+	gpio_direction_output(IOMUX_TO_GPIO(MX50_PIN_UART4_TXD), 0);
+
+	gpio_request(IOMUX_TO_GPIO(MX50_PIN_EPDC_VCOM0), "epdc_vcom");
+	gpio_direction_output(IOMUX_TO_GPIO(MX50_PIN_EPDC_VCOM0), 0);
+
+	gpio_request(IOMUX_TO_GPIO(MX50_PIN_UART4_RXD), "uart4_rxd");
+	gpio_direction_input(IOMUX_TO_GPIO(MX50_PIN_UART4_RXD));
+
+	gpio_request(IOMUX_TO_GPIO(MX50_PIN_EPDC_PWRSTAT), "epdc_pwrstat");
+	gpio_direction_input(IOMUX_TO_GPIO(MX50_PIN_EPDC_PWRSTAT));
+
+	/* ELCDIF backlight */
+	gpio_request(IOMUX_TO_GPIO(MX50_PIN_DISP_BUSY), "gp2_18");
+	gpio_direction_output(IOMUX_TO_GPIO(MX50_PIN_DISP_BUSY), 1);
+
+	if (enable_w1) {
+		/* OneWire */
+		mxc_request_iomux(MX50_PIN_OWIRE, IOMUX_CONFIG_ALT0);
+		mxc_iomux_set_pad(MX50_PIN_OWIRE, PAD_CTL_HYS_ENABLE |
+						  PAD_CTL_PKE_ENABLE |
+						  PAD_CTL_ODE_OPENDRAIN_ENABLE |
+						  PAD_CTL_DRV_HIGH |
+						  PAD_CTL_SRE_FAST |
+						  PAD_CTL_100K_PU |
+						  PAD_CTL_PUE_PULL);
+	}
+}
+
+/* workaround for cspi chipselect pin may not keep correct level when idle */
+void mx50_arm2_gpio_spi_chipselect_active(int cspi_mode, int status,
+					     int chipselect)
+{
+	switch (cspi_mode) {
+	case 1:
+		break;
+	case 2:
+		break;
+	case 3:
+		switch (chipselect) {
+		case 0x1:
+			/* enable ss0 */
+			mxc_request_iomux(MX50_PIN_CSPI_SS0, IOMUX_CONFIG_ALT0);
+			/*disable other ss */
+			mxc_request_iomux(MX50_PIN_ECSPI1_MOSI, IOMUX_CONFIG_GPIO);
+			/* pull up/down deassert it */
+			gpio_direction_input(IOMUX_TO_GPIO(MX50_PIN_ECSPI1_MOSI));
+			break;
+		case 0x2:
+			/* enable ss1 */
+			mxc_request_iomux(MX50_PIN_ECSPI1_MOSI, IOMUX_CONFIG_ALT2);
+			/*disable other ss */
+			mxc_request_iomux(MX50_PIN_CSPI_SS0, IOMUX_CONFIG_GPIO);
+			/* pull up/down deassert it */
+			gpio_direction_input(IOMUX_TO_GPIO(MX50_PIN_CSPI_SS0));
+			break;
+		default:
+			break;
+		}
+		break;
+
+	default:
+		break;
+	}
+}
+
+void mx50_arm2_gpio_spi_chipselect_inactive(int cspi_mode, int status,
+					       int chipselect)
+{
+	switch (cspi_mode) {
+	case 1:
+		break;
+	case 2:
+		break;
+	case 3:
+		switch (chipselect) {
+		case 0x1:
+			mxc_free_iomux(MX50_PIN_ECSPI1_MOSI, IOMUX_CONFIG_GPIO);
+			break;
+		case 0x2:
+			mxc_free_iomux(MX50_PIN_CSPI_SS0, IOMUX_CONFIG_GPIO);
+			break;
+		default:
+			break;
+		}
+		break;
+	default:
+		break;
+	}
+
+}
diff --git a/arch/arm/mach-mx5/mx50_arm2_pmic_mc13892.c b/arch/arm/mach-mx5/mx50_arm2_pmic_mc13892.c
index 05b8462ade40..d852fb0e016b 100644
--- a/arch/arm/mach-mx5/mx50_arm2_pmic_mc13892.c
+++ b/arch/arm/mach-mx5/mx50_arm2_pmic_mc13892.c
@@ -27,8 +27,8 @@
 #include <linux/regulator/machine.h>
 #include <linux/mfd/mc13892/core.h>
 #include <mach/irqs.h>
-
-#include <mach/iomux-mx50.h>
+#include "iomux.h"
+#include "mx50_pins.h"
 
 /*
  * Convenience conversion.
@@ -74,7 +74,11 @@
 #define AUDIO_STBY_MASK		(1 << 16)
 #define SD_STBY_MASK		(1 << 19)
 
-#define REG_MODE_0_ALL_MASK	(DIG_STBY_MASK | GEN1_STBY_MASK)
+/* 0x92412 */
+#define REG_MODE_0_ALL_MASK	(GEN1_STBY_MASK |\
+				DIG_STBY_MASK | GEN2_STBY_MASK |\
+				PLL_STBY_MASK)
+/* 0x92082 */
 #define REG_MODE_1_ALL_MASK	(CAM_STBY_MASK | VIDEO_STBY_MASK |\
 				AUDIO_STBY_MASK | SD_STBY_MASK)
 
@@ -149,17 +153,11 @@ static struct regulator_init_data sw2_init = {
 static struct regulator_init_data sw3_init = {
 	.constraints = {
 		.name = "SW3",
-		.min_uV = mV_to_uV(900),
+		.min_uV = mV_to_uV(1100),
 		.max_uV = mV_to_uV(1850),
 		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
 		.always_on = 1,
 		.boot_on = 1,
-		.initial_state = PM_SUSPEND_MEM,
-		.state_mem = {
-			.uV = 950000,
-			.mode = REGULATOR_MODE_NORMAL,
-			.enabled = 1,
-		},
 	}
 };
 
@@ -330,6 +328,8 @@ static int mc13892_regulator_init(struct mc13892 *mc13892)
 {
 	unsigned int value, register_mask;
 	printk("Initializing regulators for mx50 arm2.\n");
+	sw2_init.constraints.state_mem.uV = 1200000;
+	sw1_init.constraints.state_mem.uV = 1000000;
 
 	/* enable standby controll for all regulators */
 	pmic_read_reg(REG_MODE_0, &value, 0xffffff);
@@ -360,6 +360,7 @@ static int mc13892_regulator_init(struct mc13892 *mc13892)
 			(SWMODE_AUTO << SW4MODE_LSB);
 		pmic_write_reg(REG_SW_5, value, 0xffffff);
 	}
+
 	/* Enable coin cell charger */
 	value = BITFVAL(COINCHEN, 1) | BITFVAL(VCOIN, VCOIN_3_0V);
 	register_mask = BITFMASK(COINCHEN) | BITFMASK(VCOIN);
@@ -404,7 +405,7 @@ static struct mc13892_platform_data mc13892_plat = {
 
 static struct spi_board_info __initdata mc13892_spi_device = {
 	.modalias = "pmic_spi",
-	.irq = IOMUX_TO_IRQ_V3(114),
+	.irq = IOMUX_TO_IRQ(MX50_PIN_ECSPI2_MISO),
 	.max_speed_hz = 6000000,	/* max spi SCK clock speed in HZ */
 	.bus_num = 3,
 	.chip_select = 0,
diff --git a/arch/arm/mach-mx5/mx50_pins.h b/arch/arm/mach-mx5/mx50_pins.h
new file mode 100644
index 000000000000..75d654442429
--- /dev/null
+++ b/arch/arm/mach-mx5/mx50_pins.h
@@ -0,0 +1,340 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+#ifndef __ASM_ARCH_MXC_MX50_PINS_H__
+#define __ASM_ARCH_MXC_MX50_PINS_H__
+#include "iomux.h"
+
+/*!
+ * @file mach-mx5/mx50_pins.h
+ *
+ * @brief MX50 I/O Pin List
+ *
+ * @ingroup GPIO_MX50
+ */
+
+#ifndef __ASSEMBLY__
+
+#define PAD_I_START_MX50		0x2CC
+
+#define _MXC_BUILD_PIN_MX50(gp, gi, ga, mi, pi) \
+	(((gp) << MUX_IO_P) | ((gi) << MUX_IO_I) | \
+	((mi) << MUX_I) | \
+	((pi - PAD_I_START_MX50) << PAD_I) | \
+	((ga) << GPIO_I))
+
+#define _MXC_BUILD_GPIO_PIN_MX50(gp, gi, ga, mi, pi) \
+    _MXC_BUILD_PIN_MX50(gp, gi, ga, mi, pi)
+
+#define _MXC_BUILD_NON_GPIO_PIN_MX50(mi, pi) \
+    _MXC_BUILD_PIN_MX50(NON_GPIO_PORT, 0, 0, mi, pi)
+/*!
+ * This enumeration is constructed based on the Section
+ * "sw_pad_ctl & sw_mux_ctl details" of the MX50 IC Spec. Each enumerated
+ * value is constructed based on the rules described above.
+ */
+enum iomux_pins {
+	MX50_PIN_KEY_COL0 = _MXC_BUILD_GPIO_PIN_MX50(3, 0, 1, 0x20, 0x2CC),
+	MX50_PIN_KEY_ROW0 = _MXC_BUILD_GPIO_PIN_MX50(3, 1, 1, 0x24, 0x2D0),
+	MX50_PIN_KEY_COL1 = _MXC_BUILD_GPIO_PIN_MX50(3, 2, 1, 0x28, 0x2D4),
+	MX50_PIN_KEY_ROW1 = _MXC_BUILD_GPIO_PIN_MX50(3, 3, 1, 0x2C, 0x2D8),
+	MX50_PIN_KEY_COL2 = _MXC_BUILD_GPIO_PIN_MX50(3, 4, 1, 0x30, 0x2DC),
+	MX50_PIN_KEY_ROW2 = _MXC_BUILD_GPIO_PIN_MX50(3, 5, 1, 0x34, 0x2E0),
+	MX50_PIN_KEY_COL3 = _MXC_BUILD_GPIO_PIN_MX50(3, 6, 1, 0x38, 0x2E4),
+	MX50_PIN_KEY_ROW3 = _MXC_BUILD_GPIO_PIN_MX50(3, 7, 1, 0x3C, 0x2E8),
+	MX50_PIN_I2C1_SCL = _MXC_BUILD_GPIO_PIN_MX50(5, 18, 1, 0x40, 0x2EC),
+	MX50_PIN_I2C1_SDA = _MXC_BUILD_GPIO_PIN_MX50(5, 19, 1, 0x44, 0x2F0),
+	MX50_PIN_I2C2_SCL = _MXC_BUILD_GPIO_PIN_MX50(5, 20, 1, 0x48, 0x2F4),
+	MX50_PIN_I2C2_SDA = _MXC_BUILD_GPIO_PIN_MX50(5, 21, 1, 0x4C, 0x2F8),
+	MX50_PIN_I2C3_SCL = _MXC_BUILD_GPIO_PIN_MX50(5, 22, 1, 0x50, 0x2FC),
+	MX50_PIN_I2C3_SDA = _MXC_BUILD_GPIO_PIN_MX50(5, 23, 1, 0x54, 0x300),
+	MX50_PIN_PWM1 = _MXC_BUILD_GPIO_PIN_MX50(5, 24, 1, 0x58, 0x304),
+	MX50_PIN_PWM2 = _MXC_BUILD_GPIO_PIN_MX50(5, 25, 1, 0x5C, 0x308),
+	MX50_PIN_OWIRE = _MXC_BUILD_GPIO_PIN_MX50(5, 26, 1, 0x60, 0x30C),
+	MX50_PIN_EPITO = _MXC_BUILD_GPIO_PIN_MX50(5, 27, 1, 0x64, 0x310),
+	MX50_PIN_WDOG = _MXC_BUILD_GPIO_PIN_MX50(5, 28, 1, 0x68, 0x314),
+	MX50_PIN_SSI_TXFS = _MXC_BUILD_GPIO_PIN_MX50(5, 0, 1, 0x6C, 0x318),
+	MX50_PIN_SSI_TXC = _MXC_BUILD_GPIO_PIN_MX50(5, 1, 1, 0x70, 0x31C),
+	MX50_PIN_SSI_TXD = _MXC_BUILD_GPIO_PIN_MX50(5, 2, 1, 0x74, 0x320),
+	MX50_PIN_SSI_RXD = _MXC_BUILD_GPIO_PIN_MX50(5, 3, 1, 0x78, 0x324),
+	MX50_PIN_SSI_RXFS = _MXC_BUILD_GPIO_PIN_MX50(5, 4, 1, 0x7C, 0x328),
+	MX50_PIN_SSI_RXC = _MXC_BUILD_GPIO_PIN_MX50(5, 5, 1, 0x80, 0x32C),
+	MX50_PIN_UART1_TXD = _MXC_BUILD_GPIO_PIN_MX50(5, 6, 1, 0x84, 0x330),
+	MX50_PIN_UART1_RXD = _MXC_BUILD_GPIO_PIN_MX50(5, 7, 1, 0x88, 0x334),
+	MX50_PIN_UART1_CTS = _MXC_BUILD_GPIO_PIN_MX50(5, 8, 1, 0x8C, 0x338),
+	MX50_PIN_UART1_RTS = _MXC_BUILD_GPIO_PIN_MX50(5, 9, 1, 0x90, 0x33C),
+	MX50_PIN_UART2_TXD = _MXC_BUILD_GPIO_PIN_MX50(5, 10, 1, 0x94, 0x340),
+	MX50_PIN_UART2_RXD = _MXC_BUILD_GPIO_PIN_MX50(5, 11, 1, 0x98, 0x344),
+	MX50_PIN_UART2_CTS = _MXC_BUILD_GPIO_PIN_MX50(5, 12, 1, 0x9C, 0x348),
+	MX50_PIN_UART2_RTS = _MXC_BUILD_GPIO_PIN_MX50(5, 13, 1, 0xA0, 0x34C),
+	MX50_PIN_UART3_TXD = _MXC_BUILD_GPIO_PIN_MX50(5, 14, 1, 0xA4, 0x350),
+	MX50_PIN_UART3_RXD = _MXC_BUILD_GPIO_PIN_MX50(5, 15, 1, 0xA8, 0x354),
+	MX50_PIN_UART4_TXD = _MXC_BUILD_GPIO_PIN_MX50(5, 16, 1, 0xAC, 0x358),
+	MX50_PIN_UART4_RXD = _MXC_BUILD_GPIO_PIN_MX50(5, 17, 1, 0xB0, 0x35C),
+	MX50_PIN_CSPI_SCLK = _MXC_BUILD_GPIO_PIN_MX50(3, 8, 1, 0xB4, 0x360),
+	MX50_PIN_CSPI_MOSI = _MXC_BUILD_GPIO_PIN_MX50(3, 9, 1, 0xB8, 0x364),
+	MX50_PIN_CSPI_MISO = _MXC_BUILD_GPIO_PIN_MX50(3, 10, 1, 0xBC, 0x368),
+	MX50_PIN_CSPI_SS0 = _MXC_BUILD_GPIO_PIN_MX50(3, 11, 1, 0xC0, 0x36C),
+	MX50_PIN_ECSPI1_SCLK = _MXC_BUILD_GPIO_PIN_MX50(3, 12, 1, 0xC4, 0x370),
+	MX50_PIN_ECSPI1_MOSI = _MXC_BUILD_GPIO_PIN_MX50(3, 13, 1, 0xC8, 0x374),
+	MX50_PIN_ECSPI1_MISO = _MXC_BUILD_GPIO_PIN_MX50(3, 14, 1, 0xCC, 0x378),
+	MX50_PIN_ECSPI1_SS0 = _MXC_BUILD_GPIO_PIN_MX50(3, 15, 1, 0xD0, 0x37C),
+	MX50_PIN_ECSPI2_SCLK = _MXC_BUILD_GPIO_PIN_MX50(3, 16, 1, 0xD4, 0x380),
+	MX50_PIN_ECSPI2_MOSI = _MXC_BUILD_GPIO_PIN_MX50(3, 17, 1, 0xD8, 0x384),
+	MX50_PIN_ECSPI2_MISO = _MXC_BUILD_GPIO_PIN_MX50(3, 18, 1, 0xDC, 0x388),
+	MX50_PIN_ECSPI2_SS0 = _MXC_BUILD_GPIO_PIN_MX50(3, 19, 1, 0xE0, 0x38C),
+	MX50_PIN_SD1_CLK = _MXC_BUILD_GPIO_PIN_MX50(4, 0, 1, 0xE4, 0x390),
+	MX50_PIN_SD1_CMD = _MXC_BUILD_GPIO_PIN_MX50(4, 1, 1, 0xE8, 0x394),
+	MX50_PIN_SD1_D0 = _MXC_BUILD_GPIO_PIN_MX50(4, 2, 1, 0xEC, 0x398),
+	MX50_PIN_SD1_D1 = _MXC_BUILD_GPIO_PIN_MX50(4, 3, 1, 0xF0, 0x39C),
+	MX50_PIN_SD1_D2 = _MXC_BUILD_GPIO_PIN_MX50(4, 4, 1, 0xF4, 0x3A0),
+	MX50_PIN_SD1_D3 = _MXC_BUILD_GPIO_PIN_MX50(4, 5, 1, 0xF8, 0x3A4),
+	MX50_PIN_SD2_CLK = _MXC_BUILD_GPIO_PIN_MX50(4, 6, 1, 0xFC, 0x3A8),
+	MX50_PIN_SD2_CMD = _MXC_BUILD_GPIO_PIN_MX50(4, 7, 1, 0x100, 0x3AC),
+	MX50_PIN_SD2_D0 = _MXC_BUILD_GPIO_PIN_MX50(4, 8, 1, 0x104, 0x3B0),
+	MX50_PIN_SD2_D1 = _MXC_BUILD_GPIO_PIN_MX50(4, 9, 1, 0x108, 0x3B4),
+	MX50_PIN_SD2_D2 = _MXC_BUILD_GPIO_PIN_MX50(4, 10, 1, 0x10C, 0x3B8),
+	MX50_PIN_SD2_D3 = _MXC_BUILD_GPIO_PIN_MX50(4, 11, 1, 0x110, 0x3BC),
+	MX50_PIN_SD2_D4 = _MXC_BUILD_GPIO_PIN_MX50(4, 12, 1, 0x114, 0x3C0),
+	MX50_PIN_SD2_D5 = _MXC_BUILD_GPIO_PIN_MX50(4, 13, 1, 0x118, 0x3C4),
+	MX50_PIN_SD2_D6 = _MXC_BUILD_GPIO_PIN_MX50(4, 14, 1, 0x11C, 0x3C8),
+	MX50_PIN_SD2_D7 = _MXC_BUILD_GPIO_PIN_MX50(4, 15, 1, 0x120, 0x3CC),
+	MX50_PIN_SD2_WP = _MXC_BUILD_GPIO_PIN_MX50(4, 16, 1, 0x124, 0x3D0),
+	MX50_PIN_SD2_CD = _MXC_BUILD_GPIO_PIN_MX50(4, 17, 1, 0x128, 0x3D4),
+
+	MX50_PIN_PMIC_ON_REQ = _MXC_BUILD_NON_GPIO_PIN_MX50(NON_MUX_I, 0x3D8),
+	MX50_PIN_PMIC_STBY_REQ = _MXC_BUILD_NON_GPIO_PIN_MX50(NON_MUX_I, 0x3DC),
+	MX50_PIN_PMIC_PORT_B = _MXC_BUILD_NON_GPIO_PIN_MX50(NON_MUX_I, 0x3E0),
+	MX50_PIN_PMIC_BOOT_MODE1 = _MXC_BUILD_NON_GPIO_PIN_MX50(NON_MUX_I, 0x3E4),
+	MX50_PIN_PMIC_RESET_IN_B = _MXC_BUILD_NON_GPIO_PIN_MX50(NON_MUX_I, 0x3E8),
+	MX50_PIN_PMIC_BOOT_MODE0 = _MXC_BUILD_NON_GPIO_PIN_MX50(NON_MUX_I, 0x3EC),
+	MX50_PIN_PMIC_TEST_MODE = _MXC_BUILD_NON_GPIO_PIN_MX50(NON_MUX_I, 0x3F0),
+	MX50_PIN_PMIC_JTAG_TMS = _MXC_BUILD_NON_GPIO_PIN_MX50(NON_MUX_I, 0x3F4),
+	MX50_PIN_PMIC_JTAG_MOD = _MXC_BUILD_NON_GPIO_PIN_MX50(NON_MUX_I, 0x3F8),
+	MX50_PIN_PMIC_JTAG_TRSTB = _MXC_BUILD_NON_GPIO_PIN_MX50(NON_MUX_I, 0x3FC),
+	MX50_PIN_PMIC_JTAG_TDI = _MXC_BUILD_NON_GPIO_PIN_MX50(NON_MUX_I, 0x400),
+	MX50_PIN_PMIC_JTAG_TCK = _MXC_BUILD_NON_GPIO_PIN_MX50(NON_MUX_I, 0x404),
+	MX50_PIN_PMIC_JTAG_TDO = _MXC_BUILD_NON_GPIO_PIN_MX50(NON_MUX_I, 0x408),
+
+	MX50_PIN_DISP_D0 = _MXC_BUILD_GPIO_PIN_MX50(1, 0, 1, 0x12C, 0x40C),
+	MX50_PIN_DISP_D1 = _MXC_BUILD_GPIO_PIN_MX50(1, 1, 1, 0x130, 0x410),
+	MX50_PIN_DISP_D2 = _MXC_BUILD_GPIO_PIN_MX50(1, 2, 1, 0x134, 0x414),
+	MX50_PIN_DISP_D3 = _MXC_BUILD_GPIO_PIN_MX50(1, 3, 1, 0x138, 0x418),
+	MX50_PIN_DISP_D4 = _MXC_BUILD_GPIO_PIN_MX50(1, 4, 1, 0x13C, 0x41C),
+	MX50_PIN_DISP_D5 = _MXC_BUILD_GPIO_PIN_MX50(1, 5, 1, 0x140, 0x420),
+	MX50_PIN_DISP_D6 = _MXC_BUILD_GPIO_PIN_MX50(1, 6, 1, 0x144, 0x424),
+	MX50_PIN_DISP_D7 = _MXC_BUILD_GPIO_PIN_MX50(1, 7, 1, 0x148, 0x428),
+	MX50_PIN_DISP_WR = _MXC_BUILD_GPIO_PIN_MX50(1, 16, 1, 0x14C, 0x42C),
+	MX50_PIN_DISP_RD = _MXC_BUILD_GPIO_PIN_MX50(1, 19, 1, 0x150, 0x430),
+	MX50_PIN_DISP_RS = _MXC_BUILD_GPIO_PIN_MX50(1, 17, 1, 0x154, 0x434),
+	MX50_PIN_DISP_CS = _MXC_BUILD_GPIO_PIN_MX50(1, 21, 1, 0x158, 0x438),
+	MX50_PIN_DISP_BUSY = _MXC_BUILD_GPIO_PIN_MX50(1, 18, 1, 0x15C, 0x43C),
+	MX50_PIN_DISP_RESET = _MXC_BUILD_GPIO_PIN_MX50(1, 20, 1, 0x160, 0x440),
+	MX50_PIN_SD3_CMD = _MXC_BUILD_GPIO_PIN_MX50(4, 18, 1, 0x164, 0x444),
+	MX50_PIN_SD3_CLK = _MXC_BUILD_GPIO_PIN_MX50(4, 19, 1, 0x168, 0x448),
+	MX50_PIN_SD3_D0 = _MXC_BUILD_GPIO_PIN_MX50(4, 20, 1, 0x16C, 0x44C),
+	MX50_PIN_SD3_D1 = _MXC_BUILD_GPIO_PIN_MX50(4, 21, 1, 0x170, 0x450),
+	MX50_PIN_SD3_D2 = _MXC_BUILD_GPIO_PIN_MX50(4, 22, 1, 0x174, 0x454),
+	MX50_PIN_SD3_D3 = _MXC_BUILD_GPIO_PIN_MX50(4, 23, 1, 0x178, 0x458),
+	MX50_PIN_SD3_D4 = _MXC_BUILD_GPIO_PIN_MX50(4, 24, 1, 0x17C, 0x45C),
+	MX50_PIN_SD3_D5 = _MXC_BUILD_GPIO_PIN_MX50(4, 25, 1, 0x180, 0x460),
+	MX50_PIN_SD3_D6 = _MXC_BUILD_GPIO_PIN_MX50(4, 26, 1, 0x184, 0x464),
+	MX50_PIN_SD3_D7 = _MXC_BUILD_GPIO_PIN_MX50(4, 27, 1, 0x188, 0x468),
+	MX50_PIN_SD3_WP = _MXC_BUILD_GPIO_PIN_MX50(4, 28, 1, 0x18C, 0x46C),
+	MX50_PIN_DISP_D8 = _MXC_BUILD_GPIO_PIN_MX50(1, 8, 1, 0x190, 0x470),
+	MX50_PIN_DISP_D9 = _MXC_BUILD_GPIO_PIN_MX50(1, 9, 1, 0x194, 0x474),
+	MX50_PIN_DISP_D10 = _MXC_BUILD_GPIO_PIN_MX50(1, 10, 1, 0x198, 0x478),
+	MX50_PIN_DISP_D11 = _MXC_BUILD_GPIO_PIN_MX50(1, 11, 1, 0x19C, 0x47C),
+	MX50_PIN_DISP_D12 = _MXC_BUILD_GPIO_PIN_MX50(1, 12, 1, 0x1A0, 0x480),
+	MX50_PIN_DISP_D13 = _MXC_BUILD_GPIO_PIN_MX50(1, 13, 1, 0x1A4, 0x484),
+	MX50_PIN_DISP_D14 = _MXC_BUILD_GPIO_PIN_MX50(1, 14, 1, 0x1A8, 0x488),
+	MX50_PIN_DISP_D15 = _MXC_BUILD_GPIO_PIN_MX50(1, 15, 1, 0x1AC, 0x48C),
+
+	MX50_PIN_EPDC_D0 = _MXC_BUILD_GPIO_PIN_MX50(2, 0, 1, 0x1B0, 0x54C),
+	MX50_PIN_EPDC_D1 = _MXC_BUILD_GPIO_PIN_MX50(2, 1, 1, 0x1B4, 0x550),
+	MX50_PIN_EPDC_D2 = _MXC_BUILD_GPIO_PIN_MX50(2, 2, 1, 0x1B8, 0x554),
+	MX50_PIN_EPDC_D3 = _MXC_BUILD_GPIO_PIN_MX50(2, 3, 1, 0x1BC, 0x558),
+	MX50_PIN_EPDC_D4 = _MXC_BUILD_GPIO_PIN_MX50(2, 4, 1, 0x1C0, 0x55C),
+	MX50_PIN_EPDC_D5 = _MXC_BUILD_GPIO_PIN_MX50(2, 5, 1, 0x1C4, 0x560),
+	MX50_PIN_EPDC_D6 = _MXC_BUILD_GPIO_PIN_MX50(2, 6, 1, 0x1C8, 0x564),
+	MX50_PIN_EPDC_D7 = _MXC_BUILD_GPIO_PIN_MX50(2, 7, 1, 0x1CC, 0x568),
+	MX50_PIN_EPDC_D8 = _MXC_BUILD_GPIO_PIN_MX50(2, 8, 1, 0x1D0, 0x56C),
+	MX50_PIN_EPDC_D9 = _MXC_BUILD_GPIO_PIN_MX50(2, 9, 1, 0x1D4, 0x570),
+	MX50_PIN_EPDC_D10 = _MXC_BUILD_GPIO_PIN_MX50(2, 10, 1, 0x1D8, 0x574),
+	MX50_PIN_EPDC_D11 = _MXC_BUILD_GPIO_PIN_MX50(2, 11, 1, 0x1DC, 0x578),
+	MX50_PIN_EPDC_D12 = _MXC_BUILD_GPIO_PIN_MX50(2, 12, 1, 0x1E0, 0x57C),
+	MX50_PIN_EPDC_D13 = _MXC_BUILD_GPIO_PIN_MX50(2, 13, 1, 0x1E4, 0x580),
+	MX50_PIN_EPDC_D14 = _MXC_BUILD_GPIO_PIN_MX50(2, 14, 1, 0x1E8, 0x584),
+	MX50_PIN_EPDC_D15 = _MXC_BUILD_GPIO_PIN_MX50(2, 15, 1, 0x1EC, 0x588),
+	MX50_PIN_EPDC_GDCLK = _MXC_BUILD_GPIO_PIN_MX50(2, 16, 1, 0x1F0, 0x58C),
+	MX50_PIN_EPDC_GDSP = _MXC_BUILD_GPIO_PIN_MX50(2, 17, 1, 0x1F4, 0x590),
+	MX50_PIN_EPDC_GDOE = _MXC_BUILD_GPIO_PIN_MX50(2, 18, 1, 0x1F8, 0x594),
+	MX50_PIN_EPDC_GDRL = _MXC_BUILD_GPIO_PIN_MX50(2, 19, 1, 0x1FC, 0x598),
+	MX50_PIN_EPDC_SDCLK = _MXC_BUILD_GPIO_PIN_MX50(2, 20, 1, 0x200, 0x59C),
+	MX50_PIN_EPDC_SDOEZ = _MXC_BUILD_GPIO_PIN_MX50(2, 21, 1, 0x204, 0x5A0),
+	MX50_PIN_EPDC_SDOED = _MXC_BUILD_GPIO_PIN_MX50(2, 22, 1, 0x208, 0x5A4),
+	MX50_PIN_EPDC_SDOE = _MXC_BUILD_GPIO_PIN_MX50(2, 23, 1, 0x20C, 0x5A8),
+	MX50_PIN_EPDC_SDLE = _MXC_BUILD_GPIO_PIN_MX50(2, 24, 1, 0x210, 0x5AC),
+	MX50_PIN_EPDC_SDCLKN = _MXC_BUILD_GPIO_PIN_MX50(2, 25, 1, 0x214, 0x5B0),
+	MX50_PIN_EPDC_SDSHR = _MXC_BUILD_GPIO_PIN_MX50(2, 26, 1, 0x218, 0x5B4),
+	MX50_PIN_EPDC_PWRCOM = _MXC_BUILD_GPIO_PIN_MX50(2, 27, 1, 0x21C, 0x5B8),
+	MX50_PIN_EPDC_PWRSTAT = _MXC_BUILD_GPIO_PIN_MX50(2, 28, 1, 0x220, 0x5BC),
+	MX50_PIN_EPDC_PWRCTRL0 = _MXC_BUILD_GPIO_PIN_MX50(2, 29, 1, 0x224, 0x5C0),
+	MX50_PIN_EPDC_PWRCTRL1 = _MXC_BUILD_GPIO_PIN_MX50(2, 30, 1, 0x228, 0x5C4),
+	MX50_PIN_EPDC_PWRCTRL2 = _MXC_BUILD_GPIO_PIN_MX50(2, 31, 1, 0x22C, 0x5C8),
+	MX50_PIN_EPDC_PWRCTRL3 = _MXC_BUILD_GPIO_PIN_MX50(3, 20, 1, 0x230, 0x5CC),
+	MX50_PIN_EPDC_VCOM0 = _MXC_BUILD_GPIO_PIN_MX50(3, 21, 1, 0x234, 0x5D0),
+	MX50_PIN_EPDC_VCOM1 = _MXC_BUILD_GPIO_PIN_MX50(3, 22, 1, 0x238, 0x5D4),
+	MX50_PIN_EPDC_BDR0 = _MXC_BUILD_GPIO_PIN_MX50(3, 23, 1, 0x23C, 0x5D8),
+	MX50_PIN_EPDC_BDR1 = _MXC_BUILD_GPIO_PIN_MX50(3, 24, 1, 0x240, 0x5DC),
+	MX50_PIN_EPDC_SDCE0 = _MXC_BUILD_GPIO_PIN_MX50(3, 25, 1, 0x244, 0x5E0),
+	MX50_PIN_EPDC_SDCE1 = _MXC_BUILD_GPIO_PIN_MX50(3, 26, 1, 0x248, 0x5E4),
+	MX50_PIN_EPDC_SDCE2 = _MXC_BUILD_GPIO_PIN_MX50(3, 27, 1, 0x24C, 0x5E8),
+	MX50_PIN_EPDC_SDCE3 = _MXC_BUILD_GPIO_PIN_MX50(3, 28, 1, 0x250, 0x5EC),
+	MX50_PIN_EPDC_SDCE4 = _MXC_BUILD_GPIO_PIN_MX50(3, 29, 1, 0x254, 0x5F0),
+	MX50_PIN_EPDC_SDCE5 = _MXC_BUILD_GPIO_PIN_MX50(3, 30, 1, 0x258, 0x5F4),
+	MX50_PIN_EIM_DA0 = _MXC_BUILD_GPIO_PIN_MX50(0, 0, 1, 0x25C, 0x5F8),
+	MX50_PIN_EIM_DA1 = _MXC_BUILD_GPIO_PIN_MX50(0, 1, 1, 0x260, 0x5FC),
+	MX50_PIN_EIM_DA2 = _MXC_BUILD_GPIO_PIN_MX50(0, 2, 1, 0x264, 0x600),
+	MX50_PIN_EIM_DA3 = _MXC_BUILD_GPIO_PIN_MX50(0, 3, 1, 0x268, 0x604),
+	MX50_PIN_EIM_DA4 = _MXC_BUILD_GPIO_PIN_MX50(0, 4, 1, 0x26C, 0x608),
+	MX50_PIN_EIM_DA5 = _MXC_BUILD_GPIO_PIN_MX50(0, 5, 1, 0x270, 0x60C),
+	MX50_PIN_EIM_DA6 = _MXC_BUILD_GPIO_PIN_MX50(0, 6, 1, 0x274, 0x610),
+	MX50_PIN_EIM_DA7 = _MXC_BUILD_GPIO_PIN_MX50(0, 7, 1, 0x278, 0x614),
+	MX50_PIN_EIM_DA8 = _MXC_BUILD_GPIO_PIN_MX50(0, 8, 1, 0x27C, 0x618),
+	MX50_PIN_EIM_DA9 = _MXC_BUILD_GPIO_PIN_MX50(0, 9, 1, 0x280, 0x61C),
+	MX50_PIN_EIM_DA10 = _MXC_BUILD_GPIO_PIN_MX50(0, 10, 1, 0x284, 0x620),
+	MX50_PIN_EIM_DA11 = _MXC_BUILD_GPIO_PIN_MX50(0, 11, 1, 0x288, 0x624),
+	MX50_PIN_EIM_DA12 = _MXC_BUILD_GPIO_PIN_MX50(0, 12, 1, 0x28C, 0x628),
+	MX50_PIN_EIM_DA13 = _MXC_BUILD_GPIO_PIN_MX50(0, 13, 1, 0x290, 0x62C),
+	MX50_PIN_EIM_DA14 = _MXC_BUILD_GPIO_PIN_MX50(0, 14, 1, 0x294, 0x630),
+	MX50_PIN_EIM_DA15 = _MXC_BUILD_GPIO_PIN_MX50(0, 15, 1, 0x298, 0x634),
+	MX50_PIN_EIM_CS2 = _MXC_BUILD_GPIO_PIN_MX50(0, 16, 1, 0x29C, 0x638),
+	MX50_PIN_EIM_CS1 = _MXC_BUILD_GPIO_PIN_MX50(0, 17, 1, 0x2A0, 0x63C),
+	MX50_PIN_EIM_CS0 = _MXC_BUILD_GPIO_PIN_MX50(0, 18, 1, 0x2A4, 0x640),
+	MX50_PIN_EIM_EB0 = _MXC_BUILD_GPIO_PIN_MX50(0, 19, 1, 0x2A8, 0x644),
+	MX50_PIN_EIM_EB1 = _MXC_BUILD_GPIO_PIN_MX50(0, 20, 1, 0x2AC, 0x648),
+	MX50_PIN_EIM_WAIT = _MXC_BUILD_GPIO_PIN_MX50(0, 21, 1, 0x2B0, 0x64C),
+	MX50_PIN_EIM_BCLK = _MXC_BUILD_GPIO_PIN_MX50(0, 22, 1, 0x2B4, 0x650),
+	MX50_PIN_EIM_RDY = _MXC_BUILD_GPIO_PIN_MX50(0, 23, 1, 0x2B8, 0x654),
+	MX50_PIN_EIM_OE = _MXC_BUILD_GPIO_PIN_MX50(0, 24, 1, 0x2BC, 0x658),
+	MX50_PIN_EIM_RW = _MXC_BUILD_GPIO_PIN_MX50(0, 25, 1, 0x2C0, 0x65C),
+	MX50_PIN_EIM_LBA = _MXC_BUILD_GPIO_PIN_MX50(0, 26, 1, 0x2C4, 0x660),
+	MX50_PIN_EIM_CRE = _MXC_BUILD_GPIO_PIN_MX50(0, 27, 1, 0x2C8, 0x664),
+
+};
+
+/*!
+ * various IOMUX input select register index
+ */
+enum iomux_input_select_mx50 {
+	MUX_IN_AUDMUX_P4_INPUT_DA_AMX_SELECT_I = 0,
+	MUX_IN_AUDMUX_P4_INPUT_DB_AMX_SELECT_I,
+	MUX_IN_AUDMUX_P4_INPUT_RXCLK_AMX_SELECT_INPUT,
+	MUX_IN_AUDMUX_P4_INPUT_RXFS_AMX_SELECT_INPUT,
+	MUX_IN_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT,
+	MUX_IN_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT,
+	MUX_IN_CCM_PLL1_BYPASS_CLK_SELECT_INPUT,
+	MUX_IN_CCM_PLL2_BYPASS_CLK_SELECT_INPUT,
+	MUX_IN_CCM_PLL3_BYPASS_CLK_SELECT_INPUT,
+	MUX_IN_CSPI_IPP_IND_DATAREADY_B_SELECT_INPUT,
+	MUX_IN_CSPI_IPP_IND_SS1_B_SELECT_INPUT,
+	MUX_IN_CSPI_IPP_IND_SS2_B_SELECT_INPUT,
+	MUX_IN_CSPI_IPP_IND_SS3_B_SELECT_INPUT,
+	MUX_IN_ELCDIF_LCDIF_BUSY_SELECT_INPUT,
+	MUX_IN_ELCDIF_LCDIF_RXDATA_0_SELECT_INPUT,
+	MUX_IN_ELCDIF_LCDIF_RXDATA_1_SELECT_INPUT,
+	MUX_IN_ELCDIF_LCDIF_RXDATA_2_SELECT_INPUT,
+	MUX_IN_ELCDIF_LCDIF_RXDATA_3_SELECT_INPUT,
+	MUX_IN_ELCDIF_LCDIF_RXDATA_4_SELECT_INPUT,
+	MUX_IN_ELCDIF_LCDIF_RXDATA_5_SELECT_INPUT,
+	MUX_IN_ELCDIF_LCDIF_RXDATA_6_SELECT_INPUT,
+	MUX_IN_ELCDIF_LCDIF_RXDATA_7_SELECT_INPUT,
+	MUX_IN_ELCDIF_LCDIF_RXDATA_8_SELECT_INPUT,
+	MUX_IN_ELCDIF_LCDIF_RXDATA_9_SELECT_INPUT,
+	MUX_IN_ELCDIF_LCDIF_RXDATA_10_SELECT_INPUT,
+	MUX_IN_ELCDIF_LCDIF_RXDATA_11_SELECT_INPUT,
+	MUX_IN_ELCDIF_LCDIF_RXDATA_12_SELECT_INPUT,
+	MUX_IN_ELCDIF_LCDIF_RXDATA_13_SELECT_INPUT,
+	MUX_IN_ELCDIF_LCDIF_RXDATA_14_SELECT_INPUT,
+	MUX_IN_ELCDIF_LCDIF_RXDATA_15_SELECT_INPUT,
+	MUX_IN_ELCDIF_VSYNC_I_SELECT_INPUT,
+	MUX_IN_ESDHC2_IPP_CARD_DET_SELECT_INPUT,
+	MUX_IN_ESDHC2_IPP_WP_ON_SELECT_INPUT,
+	MUX_IN_ESDHC4_IPP_CARD_CLK_IN_SELECT_INPUT,
+	MUX_IN_ESDHC4_IPP_CMD_IN_SELECT_INPUT,
+	MUX_IN_ESDHC4_IPP_DAT0_IN_SELECT_INPUT,
+	MUX_IN_ESDHC4_IPP_DAT1_IN_SELECT_INPUT,
+	MUX_IN_ESDHC4_IPP_DAT2_IN_SELECT_INPUT,
+	MUX_IN_ESDHC4_IPP_DAT3_IN_SELECT_INPUT,
+	MUX_IN_ESDHC4_IPP_DAT4_IN_SELECT_INPUT,
+	MUX_IN_ESDHC4_IPP_DAT5_IN_SELECT_INPUT,
+	MUX_IN_ESDHC4_IPP_DAT6_IN_SELECT_INPUT,
+	MUX_IN_ESDHC4_IPP_DAT7_IN_SELECT_INPUT,
+	MUX_IN_FEC_FEC_COL_SELECT_INPUT,
+	MUX_IN_FEC_FEC_MDI_SELECT_INPUT,
+	MUX_IN_FEC_FEC_RDATA_0_SELECT_INPUT,
+	MUX_IN_FEC_FEC_RDATA_1_SELECT_INPUT,
+	MUX_IN_FEC_FEC_RX_CLK_SELECT_INPUT,
+	MUX_IN_FEC_FEC_RX_DV_SELECT_INPUT,
+	MUX_IN_FEC_FEC_RX_ER_SELECT_INPUT,
+	MUX_IN_FEC_FEC_TX_CLK_SELECT_INPUT,
+	MUX_IN_KPP_IPP_IND_COL_4_SELECT_INPUT,
+	MUX_IN_KPP_IPP_IND_COL_5_SELECT_INPUT,
+	MUX_IN_KPP_IPP_IND_COL_6_SELECT_INPUT,
+	MUX_IN_KPP_IPP_IND_COL_7_SELECT_INPUT,
+	MUX_IN_KPP_IPP_IND_ROW_4_SELECT_INPUT,
+	MUX_IN_KPP_IPP_IND_ROW_5_SELECT_INPUT,
+	MUX_IN_KPP_IPP_IND_ROW_6_SELECT_INPUT,
+	MUX_IN_KPP_IPP_IND_ROW_7_SELECT_INPUT,
+	MUX_IN_RAWNAND_U_GPMI_INPUT_GPMI_DQS_IN_SELECT_INPUT,
+	MUX_IN_RAWNAND_U_GPMI_INPUT_GPMI_RDY0_IN_SELECT_INPUT,
+	MUX_IN_SDMA_EVENTS_14_SELECT_INPUT,
+	MUX_IN_SDMA_EVENTS_15_SELECT_INPUT,
+	MUX_IN_UART1_IPP_UART_RTS_B_SELECT_INPUT,
+	MUX_IN_UART1_IPP_UART_RXD_MUX_SELECT_INPUT,
+	MUX_IN_UART2_IPP_UART_RTS_B_SELECT_INPUT,
+	MUX_IN_UART2_IPP_UART_RXD_MUX_SELECT_INPUT,
+	MUX_IN_UART3_IPP_UART_RTS_B_SELECT_INPUT,
+	MUX_IN_UART3_IPP_UART_RXD_MUX_SELECT_INPUT,
+	MUX_IN_UART4_IPP_UART_RTS_B_SELECT_INPUT,
+	MUX_IN_UART4_IPP_UART_RXD_MUX_SELECT_INPUT,
+	MUX_IN_UART5_IPP_UART_RTS_B_SELECT_INPUT,
+	MUX_IN_UART5_IPP_UART_RXD_MUX_SELECT_INPUT,
+	MUX_IN_USBOH1_IPP_IND_OTG_OC_SELECT_INPUT,
+	MUX_IN_WEIMV2_IPP_IND_READ_DATA_0_SELECT_INPUT,
+	MUX_IN_WEIMV2_IPP_IND_READ_DATA_1_SELECT_INPUT,
+	MUX_IN_WEIMV2_IPP_IND_READ_DATA_2_SELECT_INPUT,
+	MUX_IN_WEIMV2_IPP_IND_READ_DATA_3_SELECT_INPUT,
+	MUX_IN_WEIMV2_IPP_IND_READ_DATA_4_SELECT_INPUT,
+	MUX_IN_WEIMV2_IPP_IND_READ_DATA_5_SELECT_INPUT,
+	MUX_IN_WEIMV2_IPP_IND_READ_DATA_6_SELECT_INPUT,
+	MUX_IN_WEIMV2_IPP_IND_READ_DATA_7_SELECT_INPUT,
+	MUX_IN_WEIMV2_IPP_IND_READ_DATA_8_SELECT_INPUT,
+	MUX_IN_WEIMV2_IPP_IND_READ_DATA_9_SELECT_INPUT,
+	MUX_IN_WEIMV2_IPP_IND_READ_DATA_10_SELECT_INPUT,
+	MUX_IN_WEIMV2_IPP_IND_READ_DATA_11_SELECT_INPUT,
+	MUX_IN_WEIMV2_IPP_IND_READ_DATA_12_SELECT_INPUT,
+	MUX_IN_WEIMV2_IPP_IND_READ_DATA_13_SELECT_INPUT,
+	MUX_IN_WEIMV2_IPP_IND_READ_DATA_14_SELECT_INPUT,
+	MUX_IN_WEIMV2_IPP_IND_READ_DATA_15_SELECT_INPUT,
+
+	MUX_INPUT_NUM_MUX,
+};
+
+#endif				/* __ASSEMBLY__ */
+#endif				/* __ASM_ARCH_MXC_MX50_PINS_H__ */
diff --git a/arch/arm/mach-mx5/mx51_3stack.c b/arch/arm/mach-mx5/mx51_3stack.c
index cc5a205d594d..4fade5a37ac2 100644
--- a/arch/arm/mach-mx5/mx51_3stack.c
+++ b/arch/arm/mach-mx5/mx51_3stack.c
@@ -184,77 +184,15 @@ static struct mxc_vpu_platform_data mxc_vpu_data = {
 	.reset = mx5_vpu_reset,
 };
 
-/* workaround for ecspi chipselect pin may not keep correct level when idle */
-static void mx51_3ds_gpio_spi_chipselect_active(int cspi_mode, int status,
-					     int chipselect)
-{
-	u32 gpio;
-
-	switch (cspi_mode) {
-	case 1:
-		switch (chipselect) {
-		case 0x1:
-			mxc_request_iomux(MX51_PIN_CSPI1_SS0,
-					  IOMUX_CONFIG_ALT0);
-			mxc_iomux_set_pad(MX51_PIN_CSPI1_SS0,
-					  PAD_CTL_HYS_ENABLE |
-					  PAD_CTL_PKE_ENABLE |
-					  PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
-			break;
-		case 0x2:
-			gpio = IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS0);
-			mxc_request_iomux(MX51_PIN_CSPI1_SS0,
-					  IOMUX_CONFIG_GPIO);
-			gpio_request(gpio, "cspi1_ss0");
-			gpio_direction_output(gpio, 0);
-			gpio_set_value(gpio, 1 & (~status));
-			break;
-		default:
-			break;
-		}
-		break;
-	case 2:
-		break;
-	case 3:
-		break;
-	default:
-		break;
-	}
-}
-
-static void mx51_3ds_gpio_spi_chipselect_inactive(int cspi_mode, int status,
-					       int chipselect)
-{
-	switch (cspi_mode) {
-	case 1:
-		switch (chipselect) {
-		case 0x1:
-			mxc_free_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT0);
-			mxc_request_iomux(MX51_PIN_CSPI1_SS0,
-					  IOMUX_CONFIG_GPIO);
-			mxc_free_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_GPIO);
-			break;
-		case 0x2:
-			mxc_free_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_GPIO);
-			break;
-		default:
-			break;
-		}
-		break;
-	case 2:
-		break;
-	case 3:
-		break;
-	default:
-		break;
-	}
-}
-
+extern void mx51_babbage_gpio_spi_chipselect_active(int cspi_mode, int status,
+						    int chipselect);
+extern void mx51_babbage_gpio_spi_chipselect_inactive(int cspi_mode, int status,
+						      int chipselect);
 static struct mxc_spi_master mxcspi1_data = {
 	.maxchipselect = 4,
 	.spi_version = 23,
-	.chipselect_active = mx51_3ds_gpio_spi_chipselect_active,
-	.chipselect_inactive = mx51_3ds_gpio_spi_chipselect_inactive,
+	.chipselect_active = mx51_babbage_gpio_spi_chipselect_active,
+	.chipselect_inactive = mx51_babbage_gpio_spi_chipselect_inactive,
 };
 
 static struct mxc_i2c_platform_data mxci2c_data = {
@@ -278,11 +216,11 @@ static struct mxc_dvfs_platform_data dvfs_core_data = {
 	.reg_id = "SW1",
 	.clk1_id = "cpu_clk",
 	.clk2_id = "gpc_dvfs_clk",
-	.gpc_cntr_offset = MXC_GPC_CNTR_OFFSET,
-	.gpc_vcr_offset = MXC_GPC_VCR_OFFSET,
-	.ccm_cdcr_offset = MXC_CCM_CDCR_OFFSET,
-	.ccm_cacrr_offset = MXC_CCM_CACRR_OFFSET,
-	.ccm_cdhipr_offset = MXC_CCM_CDHIPR_OFFSET,
+	.gpc_cntr_reg_addr = MXC_GPC_CNTR,
+	.gpc_vcr_reg_addr = MXC_GPC_VCR,
+	.ccm_cdcr_reg_addr = MXC_CCM_CDCR,
+	.ccm_cacrr_reg_addr = MXC_CCM_CACRR,
+	.ccm_cdhipr_reg_addr = MXC_CCM_CDHIPR,
 	.prediv_mask = 0x1F800,
 	.prediv_offset = 11,
 	.prediv_val = 3,
@@ -950,8 +888,6 @@ static void __init mxc_board_init(void)
 
 	mxc_ipu_data.di_clk[0] = clk_get(NULL, "ipu_di0_clk");
 	mxc_ipu_data.di_clk[1] = clk_get(NULL, "ipu_di1_clk");
-	mxc_ipu_data.csi_clk[0] = clk_get(NULL, "csi_mclk1");
-	mxc_ipu_data.csi_clk[1] = clk_get(NULL, "csi_mclk2");
 
 	mxc_spdif_data.spdif_core_clk = clk_get(NULL, "spdif_xtal_clk");
 	clk_put(mxc_spdif_data.spdif_core_clk);
@@ -1020,8 +956,6 @@ static void __init mxc_board_init(void)
 	mxc_register_device(&mxc_sgtl5000_device, &sgtl5000_data);
 	mxc_register_device(&mxc_bt_device, &mxc_bt_data);
 	mxc_register_device(&mxc_gps_device, &gps_data);
-	mxc_register_device(&mxc_v4l2_device, NULL);
-	mxc_register_device(&mxc_v4l2out_device, NULL);
 
 	mx5_usb_dr_init();
 	mx5_usbh1_init();
diff --git a/arch/arm/mach-mx5/mx51_babbage.c b/arch/arm/mach-mx5/mx51_babbage.c
index 1acc44937e65..6658a99e1d2e 100644
--- a/arch/arm/mach-mx5/mx51_babbage.c
+++ b/arch/arm/mach-mx5/mx51_babbage.c
@@ -31,7 +31,6 @@
 #include <linux/ipu.h>
 #include <linux/mxcfb.h>
 #include <linux/pwm_backlight.h>
-#include <linux/fec.h>
 #include <mach/common.h>
 #include <mach/hardware.h>
 #include <asm/setup.h>
@@ -44,16 +43,12 @@
 #include <mach/mmc.h>
 #include <mach/mxc_dvfs.h>
 #include <mach/mxc_edid.h>
-#include <mach/iomux-mx51.h>
-#include <mach/gpio.h>
 
 #include "devices.h"
+#include "iomux.h"
+#include "mx51_pins.h"
 #include "crm_regs.h"
 #include "usb.h"
-#include <mach/mxc_edid.h>
-#include <linux/android_pmem.h>
-#include <linux/usb/android.h>
-#include <linux/switch.h>
 
 /*!
  * @file mach-mx51/mx51_babbage.c
@@ -62,181 +57,12 @@
  *
  * @ingroup MSL_MX51
  */
-
-#define BABBAGE_SD1_CD			(0*32 + 0)	/* GPIO_1_0 */
-#define BABBAGE_SD1_WP		(0*32 + 1)	/* GPIO_1_1 */
-#define BABBAGE_SD2_CD_2_0		(0*32 + 4)	/* GPIO_1_4 */
-#define BABBAGE_SD2_WP		(0*32 + 5)	/* GPIO_1_5 */
-#define BABBAGE_SD2_CD_2_5		(0*32 + 6)	/* GPIO_1_6 */
-#define BABBAGE_USBH1_HUB_RST		(0*32 + 7)	/* GPIO_1_7 */
-#define BABBAGE_PMIC_INT		(0*32 + 8)	/* GPIO_1_8 */
-
-#define BABBAGE_USB_CLK_EN_B		(1*32 + 1)	/* GPIO_2_1 */
-#define BABBAGE_OSC_EN_B		(1*32 + 2)	/* GPIO_2_2 */
-#define BABBAGE_PHY_RESET		(1*32 + 5)	/* GPIO_2_5 */
-#define BABBAGE_CAM_RESET		(1*32 + 7)	/* GPIO_2_7 */
-#define BABBAGE_FM_PWR		(1*32 + 12)	/* GPIO_2_12 */
-#define BABBAGE_VGA_RESET		(1*32 + 13)	/* GPIO_2_13 */
-#define BABBAGE_FEC_PHY_RESET		(1*32 + 14)	/* GPIO_2_14 */
-#define BABBAGE_FM_RESET		(1*32 + 15)	/* GPIO_2_15 */
-#define BABBAGE_AUDAMP_STBY		(1*32 + 17)	/* GPIO_2_17 */
-#define BABBAGE_POWER_KEY		(1*32 + 21)	/* GPIO_2_21 */
-
-#define BABBAGE_26M_OSC_EN		(2*32 + 1)	/* GPIO_3_1 */
-#define BABBAGE_LVDS_POWER_DOWN	(2*32 + 3)	/* GPIO_3_3 */
-#define BABBAGE_DISP_BRIGHTNESS_CTL	(2*32 + 4)	/* GPIO_3_4 */
-#define BABBAGE_DVI_RESET		(2*32 + 5)	/* GPIO_3_5 */
-#define BABBAGE_DVI_POWER		(2*32 + 6)	/* GPIO_3_6 */
-#define BABBAGE_HEADPHONE_DET	(2*32 + 26)	/* GPIO_3_26 */
-#define BABBAGE_DVI_DET		(2*32 + 28)	/* GPIO_3_28 */
-
-#define BABBAGE_LCD_3V3_ON		(3*32 + 9)	/* GPIO_4_9 */
-#define BABBAGE_LCD_5V_ON		(3*32 + 10)	/* GPIO_4_10 */
-#define BABBAGE_CAM_LOW_POWER	(3*32 + 10)	/* GPIO_4_12 */
-#define BABBAGE_DVI_I2C_EN		(3*32 + 14)	/* GPIO_4_14 */
-#define BABBAGE_CSP1_SS0_GPIO		(3*32 + 24)	/* GPIO_4_24 */
-#define BABBAGE_AUDIO_CLK_EN		(3*32 + 26)	/* GPIO_4_26 */
-
 extern int __init mx51_babbage_init_mc13892(void);
+extern void __init mx51_babbage_io_init(void);
 extern struct cpu_wp *(*get_cpu_wp)(int *wp);
 extern void (*set_num_cpu_wp)(int num);
 static int num_cpu_wp = 3;
 
-static struct pad_desc mx51babbage_pads[] = {
-	/* UART1 */
-	MX51_PAD_UART1_RXD__UART1_RXD,
-	MX51_PAD_UART1_TXD__UART1_TXD,
-	MX51_PAD_UART1_RTS__UART1_RTS,
-	MX51_PAD_UART1_CTS__UART1_CTS,
-
-	/* USB HOST1 */
-	MX51_PAD_USBH1_STP__USBH1_STP,
-	MX51_PAD_USBH1_CLK__USBH1_CLK,
-	MX51_PAD_USBH1_DIR__USBH1_DIR,
-	MX51_PAD_USBH1_NXT__USBH1_NXT,
-	MX51_PAD_USBH1_DATA0__USBH1_DATA0,
-	MX51_PAD_USBH1_DATA1__USBH1_DATA1,
-	MX51_PAD_USBH1_DATA2__USBH1_DATA2,
-	MX51_PAD_USBH1_DATA3__USBH1_DATA3,
-	MX51_PAD_USBH1_DATA4__USBH1_DATA4,
-	MX51_PAD_USBH1_DATA5__USBH1_DATA5,
-	MX51_PAD_USBH1_DATA6__USBH1_DATA6,
-	MX51_PAD_USBH1_DATA7__USBH1_DATA7,
-
-	MX51_PAD_GPIO_1_0__GPIO_1_0,
-	MX51_PAD_GPIO_1_1__GPIO_1_1,
-	MX51_PAD_GPIO_1_4__GPIO_1_4,
-	MX51_PAD_GPIO_1_5__GPIO_1_5,
-	MX51_PAD_GPIO_1_6__GPIO_1_6,
-	MX51_PAD_GPIO_1_7__GPIO_1_7,
-	MX51_PAD_GPIO_1_8__GPIO_1_8,
-	MX51_PAD_UART3_RXD__GPIO_1_22,
-
-	MX51_PAD_EIM_D17__GPIO_2_1,
-	MX51_PAD_EIM_D18__GPIO_2_2,
-	MX51_PAD_EIM_D21__GPIO_2_5,
-	MX51_PAD_EIM_D23__GPIO_2_7,
-	MX51_PAD_EIM_A16__GPIO_2_10,
-	MX51_PAD_EIM_A17__GPIO_2_11,
-	MX51_PAD_EIM_A18__GPIO_2_12,
-	MX51_PAD_EIM_A19__GPIO_2_13,
-	MX51_PAD_EIM_A20__GPIO_2_14,
-	MX51_PAD_EIM_A21__GPIO_2_15,
-	MX51_PAD_EIM_A22__GPIO_2_16,
-	MX51_PAD_EIM_A23__GPIO_2_17,
-	MX51_PAD_EIM_A27__GPIO_2_21,
-	MX51_PAD_EIM_DTACK__GPIO_2_31,
-
-	MX51_PAD_EIM_LBA__GPIO_3_1,
-	MX51_PAD_DI1_D0_CS__GPIO_3_3,
-	MX51_PAD_DISPB2_SER_DIN__GPIO_3_5,
-	MX51_PAD_DISPB2_SER_DIO__GPIO_3_6,
-	MX51_PAD_NANDF_CS0__GPIO_3_16,
-	MX51_PAD_NANDF_CS1__GPIO_3_17,
-	MX51_PAD_NANDF_D14__GPIO_3_26,
-	MX51_PAD_NANDF_D12__GPIO_3_28,
-
-	MX51_PAD_CSI2_D12__GPIO_4_9,
-	MX51_PAD_CSI2_D13__GPIO_4_10,
-	MX51_PAD_CSI2_D19__GPIO_4_12,
-	MX51_PAD_CSI2_HSYNC__GPIO_4_14,
-	MX51_PAD_CSPI1_RDY__GPIO_4_26,
-
-	MX51_PAD_EIM_EB2__FEC_MDIO,
-	MX51_PAD_EIM_EB3__FEC_RDAT1,
-	MX51_PAD_EIM_CS2__FEC_RDAT2,
-	MX51_PAD_EIM_CS3__FEC_RDAT3,
-	MX51_PAD_EIM_CS4__FEC_RX_ER,
-	MX51_PAD_EIM_CS5__FEC_CRS,
-	MX51_PAD_NANDF_RB2__FEC_COL,
-	MX51_PAD_NANDF_RB3__FEC_RXCLK,
-	MX51_PAD_NANDF_RB6__FEC_RDAT0,
-	MX51_PAD_NANDF_RB7__FEC_TDAT0,
-	MX51_PAD_NANDF_CS2__FEC_TX_ER,
-	MX51_PAD_NANDF_CS3__FEC_MDC,
-	MX51_PAD_NANDF_CS4__FEC_TDAT1,
-	MX51_PAD_NANDF_CS5__FEC_TDAT2,
-	MX51_PAD_NANDF_CS6__FEC_TDAT3,
-	MX51_PAD_NANDF_CS7__FEC_TX_EN,
-	MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK,
-
-	MX51_PAD_GPIO_NAND__PATA_INTRQ,
-
-	MX51_PAD_DI_GP4__DI2_PIN15,
-#ifdef CONFIG_FB_MXC_CLAA_WVGA_SYNC_PANEL
-	MX51_PAD_DISP1_DAT22__DISP2_DAT16,
-	MX51_PAD_DISP1_DAT23__DISP2_DAT17,
-
-	MX51_PAD_DI1_D1_CS__GPIO_3_4,
-#endif
-	MX51_PAD_I2C1_CLK__HSI2C_CLK,
-	MX51_PAD_I2C1_DAT__HSI2C_DAT,
-	MX51_PAD_EIM_D16__I2C1_SDA,
-	MX51_PAD_EIM_D19__I2C1_SCL,
-
-	MX51_PAD_GPIO_1_2__PWM_PWMO,
-
-	MX51_PAD_KEY_COL5__I2C2_SDA,
-	MX51_PAD_KEY_COL4__I2C2_SCL,
-
-	MX51_PAD_SD1_CMD__SD1_CMD,
-	MX51_PAD_SD1_CLK__SD1_CLK,
-	MX51_PAD_SD1_DATA0__SD1_DATA0,
-	MX51_PAD_SD1_DATA1__SD1_DATA1,
-	MX51_PAD_SD1_DATA2__SD1_DATA2,
-	MX51_PAD_SD1_DATA3__SD1_DATA3,
-
-	MX51_PAD_SD2_CMD__SD2_CMD,
-	MX51_PAD_SD2_CLK__SD2_CLK,
-	MX51_PAD_SD2_DATA0__SD2_DATA0,
-	MX51_PAD_SD2_DATA1__SD2_DATA1,
-	MX51_PAD_SD2_DATA2__SD2_DATA2,
-	MX51_PAD_SD2_DATA3__SD2_DATA3,
-
-	MX51_PAD_AUD3_BB_TXD__AUD3_BB_TXD,
-	MX51_PAD_AUD3_BB_RXD__AUD3_BB_RXD,
-	MX51_PAD_AUD3_BB_CK__AUD3_BB_CK,
-	MX51_PAD_AUD3_BB_FS__AUD3_BB_FS,
-
-	MX51_PAD_CSPI1_SS1__CSPI1_SS1,
-
-	MX51_PAD_DI_GP3__CSI1_DATA_EN,
-	MX51_PAD_CSI1_D10__CSI1_D10,
-	MX51_PAD_CSI1_D11__CSI1_D11,
-	MX51_PAD_CSI1_D12__CSI1_D12,
-	MX51_PAD_CSI1_D13__CSI1_D13,
-	MX51_PAD_CSI1_D14__CSI1_D14,
-	MX51_PAD_CSI1_D15__CSI1_D15,
-	MX51_PAD_CSI1_D16__CSI1_D16,
-	MX51_PAD_CSI1_D17__CSI1_D17,
-	MX51_PAD_CSI1_D18__CSI1_D18,
-	MX51_PAD_CSI1_D19__CSI1_D19,
-	MX51_PAD_CSI1_VSYNC__CSI1_VSYNC,
-	MX51_PAD_CSI1_HSYNC__CSI1_HSYNC,
-
-	MX51_PAD_OWIRE_LINE__SPDIF_OUT1,
-};
-
 /* working point(wp): 0 - 800MHz; 1 - 166.25MHz; */
 static struct cpu_wp cpu_wp_auto[] = {
 	{
@@ -298,7 +124,7 @@ static struct fb_videomode video_modes[] = {
 	 FB_VMODE_NONINTERLACED,
 	 0,},
 	{
-	 /*MITSUBISHI LVDS panel */
+	 /* MITSUBISHI LVDS panel */
 	 "XGA", 60, 1024, 768, 15385,
 	 220, 40,
 	 21, 7,
@@ -364,73 +190,10 @@ static struct mxc_vpu_platform_data mxc_vpu_data = {
 	.reset = mx5_vpu_reset,
 };
 
-static struct fec_platform_data fec_data = {
-	.phy = PHY_INTERFACE_MODE_MII,
-	.phy_mask = ~1UL,
-};
-
-/* workaround for ecspi chipselect pin may not keep correct level when idle */
-static void mx51_babbage_gpio_spi_chipselect_active(int cspi_mode, int status,
-					     int chipselect)
-{
-	switch (cspi_mode) {
-	case 1:
-		switch (chipselect) {
-		case 0x1:
-			{
-			struct pad_desc cspi1_ss0 = MX51_PAD_CSPI1_SS0__CSPI1_SS0;
-
-			mxc_iomux_v3_setup_pad(&cspi1_ss0);
-			break;
-			}
-		case 0x2:
-			{
-			struct pad_desc cspi1_ss0_gpio = MX51_PAD_CSPI1_SS0__GPIO_4_24;
-
-			mxc_iomux_v3_setup_pad(&cspi1_ss0_gpio);
-			gpio_request(BABBAGE_CSP1_SS0_GPIO, "cspi1-gpio");
-			gpio_direction_output(BABBAGE_CSP1_SS0_GPIO, 0);
-			gpio_set_value(BABBAGE_CSP1_SS0_GPIO, 1 & (~status));
-			break;
-			}
-		default:
-			break;
-		}
-		break;
-	case 2:
-		break;
-	case 3:
-		break;
-	default:
-		break;
-	}
-}
-
-static void mx51_babbage_gpio_spi_chipselect_inactive(int cspi_mode, int status,
-					       int chipselect)
-{
-	switch (cspi_mode) {
-	case 1:
-		switch (chipselect) {
-		case 0x1:
-			break;
-		case 0x2:
-			gpio_free(BABBAGE_CSP1_SS0_GPIO);
-			break;
-
-		default:
-			break;
-		}
-		break;
-	case 2:
-		break;
-	case 3:
-		break;
-	default:
-		break;
-	}
-}
-
+extern void mx51_babbage_gpio_spi_chipselect_active(int cspi_mode, int status,
+						    int chipselect);
+extern void mx51_babbage_gpio_spi_chipselect_inactive(int cspi_mode, int status,
+						      int chipselect);
 static struct mxc_spi_master mxcspi1_data = {
 	.maxchipselect = 4,
 	.spi_version = 23,
@@ -458,11 +221,11 @@ static struct mxc_dvfs_platform_data dvfs_core_data = {
 	.reg_id = "SW1",
 	.clk1_id = "cpu_clk",
 	.clk2_id = "gpc_dvfs_clk",
-	.gpc_cntr_offset = MXC_GPC_CNTR_OFFSET,
-	.gpc_vcr_offset = MXC_GPC_VCR_OFFSET,
-	.ccm_cdcr_offset = MXC_CCM_CDCR_OFFSET,
-	.ccm_cacrr_offset = MXC_CCM_CACRR_OFFSET,
-	.ccm_cdhipr_offset = MXC_CCM_CDHIPR_OFFSET,
+	.gpc_cntr_reg_addr = MXC_GPC_CNTR,
+	.gpc_vcr_reg_addr = MXC_GPC_VCR,
+	.ccm_cdcr_reg_addr = MXC_CCM_CDCR,
+	.ccm_cacrr_reg_addr = MXC_CCM_CACRR,
+	.ccm_cdhipr_reg_addr = MXC_CCM_CDHIPR,
 	.prediv_mask = 0x1F800,
 	.prediv_offset = 11,
 	.prediv_val = 3,
@@ -533,24 +296,26 @@ static int __init mxc_init_fb(void)
 		return 0;
 
 	/* DI0-LVDS */
-	gpio_set_value(BABBAGE_LVDS_POWER_DOWN, 0);
+	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_DI1_D0_CS), 0);
 	msleep(1);
-	gpio_set_value(BABBAGE_LVDS_POWER_DOWN, 1);
-	gpio_set_value(BABBAGE_LCD_3V3_ON, 1);
-	gpio_set_value(BABBAGE_LCD_5V_ON, 1);
+	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_DI1_D0_CS), 1);
+	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSI2_D12), 1);
+	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSI2_D13), 1);
 
 	/* DVI Detect */
-	gpio_request(BABBAGE_DVI_DET, "dvi-detect");
-	gpio_direction_input(BABBAGE_DVI_DET);
+	gpio_request(IOMUX_TO_GPIO(MX51_PIN_NANDF_D12), "nandf_d12");
+	gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_NANDF_D12));
 	/* DVI Reset - Assert for i2c disabled mode */
-	gpio_request(BABBAGE_DVI_RESET, "dvi-reset");
-	gpio_direction_output(BABBAGE_DVI_RESET, 0);
+	gpio_request(IOMUX_TO_GPIO(MX51_PIN_DISPB2_SER_DIN), "dispb2_ser_din");
+	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_DISPB2_SER_DIN), 0);
+	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_DISPB2_SER_DIN), 0);
 	/* DVI Power-down */
-	gpio_request(BABBAGE_DVI_POWER, "dvi-power");
-	gpio_direction_output(BABBAGE_DVI_POWER, 1);
+	gpio_request(IOMUX_TO_GPIO(MX51_PIN_DISPB2_SER_DIO), "dispb2_ser_di0");
+	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_DISPB2_SER_DIO), 1);
+	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_DISPB2_SER_DIO), 0);
 
 	/* WVGA Reset */
-	gpio_set_value(BABBAGE_DISP_BRIGHTNESS_CTL, 1);
+	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_DI1_D1_CS), 1);
 
 	if (primary_di) {
 		printk(KERN_INFO "DI1 is primary\n");
@@ -672,15 +437,15 @@ static int handle_edid(int *pixclk)
 
 static void dvi_reset(void)
 {
-	gpio_direction_output(BABBAGE_DVI_RESET, 0);
-	gpio_set_value(BABBAGE_DVI_RESET, 0);
+	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_DISPB2_SER_DIN), 0);
+	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_DISPB2_SER_DIN), 0);
 	msleep(50);
 
 	/* do reset */
-	gpio_set_value(BABBAGE_DVI_RESET, 1);
+	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_DISPB2_SER_DIN), 1);
 	msleep(20);		/* tRES >= 50us */
 
-	gpio_set_value(BABBAGE_DVI_RESET, 0);
+	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_DISPB2_SER_DIN), 0);
 }
 
 static struct mxc_lcd_platform_data dvi_data = {
@@ -691,13 +456,14 @@ static struct mxc_lcd_platform_data dvi_data = {
 
 static void vga_reset(void)
 {
-
-	gpio_set_value(BABBAGE_VGA_RESET, 0);
+	gpio_request(IOMUX_TO_GPIO(MX51_PIN_EIM_A19), "eim_a19");
+	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A19), 0);
+	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A19), 0);
 	msleep(50);
 	/* do reset */
-	gpio_set_value(BABBAGE_VGA_RESET, 1);
+	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A19), 1);
 	msleep(10);		/* tRES >= 50us */
-	gpio_set_value(BABBAGE_VGA_RESET, 0);
+	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A19), 0);
 }
 
 static struct mxc_lcd_platform_data vga_data = {
@@ -710,23 +476,22 @@ static struct mxc_lcd_platform_data vga_data = {
 static void si4702_reset(void)
 {
 	return;
-
-	gpio_set_value(BABBAGE_FM_RESET, 0);
+	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A21), 0);
 	msleep(100);
-	gpio_set_value(BABBAGE_FM_RESET, 1);
+	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A21), 1);
 	msleep(100);
 }
 
 static void si4702_clock_ctl(int flag)
 {
-	gpio_set_value(BABBAGE_FM_PWR, flag);
+	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A18), flag);
 	msleep(100);
 }
 
 static void si4702_gpio_get(void)
 {
-	gpio_request(BABBAGE_FM_PWR, "fm-power");
-	gpio_direction_output(BABBAGE_FM_PWR, 0);
+	gpio_request(IOMUX_TO_GPIO(MX51_PIN_EIM_A18), "eim_a18");
+	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A18), 0);
 }
 
 static void si4702_gpio_put(void)
@@ -852,9 +617,9 @@ static int sdhc_write_protect(struct device *dev)
 	unsigned short rc = 0;
 
 	if (to_platform_device(dev)->id == 0)
-		rc = gpio_get_value(BABBAGE_SD1_WP);
+		rc = gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_1));
 	else
-		rc = gpio_get_value(BABBAGE_SD2_WP);
+		rc = gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_5));
 
 	return rc;
 }
@@ -864,15 +629,15 @@ static unsigned int sdhc_get_card_det_status(struct device *dev)
 	int ret;
 
 	if (to_platform_device(dev)->id == 0) {
-		ret = gpio_get_value(BABBAGE_SD1_CD);
+		ret = gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_0));
 		return ret;
 	} else {		/* config the det pin for SDHC2 */
 		if (board_is_rev(BOARD_REV_2))
 			/* BB2.5 */
-			ret = gpio_get_value(BABBAGE_SD2_CD_2_5);
+			ret = gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_6));
 		else
 			/* BB2.0 */
-			ret = gpio_get_value(BABBAGE_SD2_CD_2_0);
+			ret = gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_4));
 		return ret;
 	}
 }
@@ -900,25 +665,27 @@ static struct mxc_mmc_platform_data mmc2_data = {
 	.status = sdhc_get_card_det_status,
 	.wp_status = sdhc_write_protect,
 	.clock_mmc = "esdhc_clk",
-	.clk_always_on = 1,
 };
 
 static int mxc_sgtl5000_amp_enable(int enable)
 {
-	gpio_set_value(BABBAGE_AUDAMP_STBY, enable ? 1 : 0);
+	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A23), enable ? 1 : 0);
 	return 0;
 }
 
 static int headphone_det_status(void)
 {
-	return (gpio_get_value(BABBAGE_HEADPHONE_DET) == 0);
+	if (cpu_is_mx51_rev(CHIP_REV_1_1) == 2)
+		return (gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_NANDF_D14)) == 0);
+
+	return gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0));
 }
 
 static struct mxc_audio_platform_data sgtl5000_data = {
 	.ssi_num = 1,
 	.src_port = 2,
 	.ext_port = 3,
-	.hp_irq = IOMUX_TO_IRQ_V3(BABBAGE_HEADPHONE_DET),
+	.hp_irq = IOMUX_TO_IRQ(MX51_PIN_NANDF_D14),
 	.hp_status = headphone_det_status,
 	.amp_enable = mxc_sgtl5000_amp_enable,
 	.sysclk = 12288000,
@@ -928,41 +695,6 @@ static struct platform_device mxc_sgtl5000_device = {
 	.name = "imx-3stack-sgtl5000",
 };
 
-static int __initdata enable_w1 = { 0 };
-static int __init w1_setup(char *__unused)
-{
-	enable_w1 = 1;
-	return cpu_is_mx51();
-}
-
-__setup("w1", w1_setup);
-
-static struct android_pmem_platform_data android_pmem_pdata = {
-	.name = "pmem_adsp",
-	.start = 0,
-	.size = SZ_32M,
-	.no_allocator = 0,
-	.cached = PMEM_NONCACHE_NORMAL,
-};
-
-static struct android_pmem_platform_data android_pmem_gpu_pdata = {
-	.name = "pmem_gpu",
-	.start = 0,
-	.size = SZ_32M,
-	.no_allocator = 0,
-	.cached = PMEM_CACHE_ENABLE,
-};
-
-static struct android_usb_platform_data android_usb_pdata = {
-	.vendor_id      = 0x0bb4,
-	.product_id     = 0x0c01,
-	.adb_product_id = 0x0c02,
-	.version        = 0x0100,
-	.product_name   = "Android Phone",
-	.manufacturer_name = "Freescale",
-	.nluns = 3,
-};
-
 /*!
  * Board specific fixup function. It is called by \b setup_arch() in
  * setup.c file very early on during kernel starts. It allows the user to
@@ -984,32 +716,12 @@ static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags,
 	int left_mem = 0;
 	int gpu_mem = SZ_64M;
 	int fb_mem = SZ_32M;
-	int size;
 
 	mxc_set_cpu_type(MXC_CPU_MX51);
 
 	get_cpu_wp = mx51_babbage_get_cpu_wp;
 	set_num_cpu_wp = mx51_babbage_set_num_cpu_wp;
 
-	for_each_tag(t, tags) {
-		if (t->hdr.tag != ATAG_MEM)
-			continue;
-		size = t->u.mem.size;
-
-		android_pmem_pdata.start =
-				PHYS_OFFSET + size - android_pmem_pdata.size;
-		android_pmem_gpu_pdata.start =
-				android_pmem_pdata.start - android_pmem_gpu_pdata.size;
-		gpu_device.resource[5].start =
-				android_pmem_gpu_pdata.start - SZ_16M;
-		gpu_device.resource[5].end =
-				gpu_device.resource[5].start + SZ_16M - 1;
-		size -= android_pmem_pdata.size;
-		size -= android_pmem_gpu_pdata.size;
-		size -= SZ_16M;
-		t->u.mem.size = size;
-	}
-#if 0
 	for_each_tag(mem_tag, tags) {
 		if (mem_tag->hdr.tag == ATAG_MEM) {
 			total_mem = mem_tag->u.mem.size;
@@ -1066,83 +778,8 @@ static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags,
 		}
 #endif
 	}
-#endif
-}
-
-static struct switch_dev dvi_sdev;
-static int state;
-static struct delayed_work dvi_det_work;
-static void dvi_update_detect_status(void)
-{
-	int level;
-
-	level = gpio_get_value(BABBAGE_DVI_DET);
-	if (level == 1) {
-		pr_info(KERN_INFO "DVI device plug-in\n");
-		state = 1;
-	} else {
-		pr_info(KERN_INFO "DVI device plug-out\n");
-		state = 0;
-	}
-	switch_set_state(&dvi_sdev, state);
-}
-
-static void dvi_work_func(struct work_struct *work)
-{
-	dvi_update_detect_status();
-}
-
-static irqreturn_t dvi_det_int(int irq, void *dev_id)
-{
-	schedule_delayed_work(&dvi_det_work, msecs_to_jiffies(10));
-	return 0;
 }
 
-static ssize_t print_switch_name(struct switch_dev *sdev, char *buf)
-{
-	return sprintf(buf, "dvi_det\n");
-}
-
-static ssize_t print_switch_state(struct switch_dev *sdev, char *buf)
-{
-	return sprintf(buf, "%s\n", (state ? "online" : "offline"));
-}
-
-static int __init mxc_init_dvi_det(void)
-{
-	int irq, level, ret;
-
-	if (!machine_is_mx51_babbage())
-		return 0;
-
-	dvi_sdev.name = "dvi_det";
-	dvi_sdev.print_name = print_switch_name;
-	dvi_sdev.print_state = print_switch_state;
-	switch_dev_register(&dvi_sdev);
-
-	level = gpio_get_value(BABBAGE_DVI_DET);
-	if (level == 1) {
-		pr_info(KERN_INFO "DVI device plug-in\n");
-		state = 1;
-	} else {
-		pr_info(KERN_INFO "DVI device plug-out\n");
-		state = 0;
-	}
-
-	INIT_DELAYED_WORK(&dvi_det_work, dvi_work_func);
-
-	irq = IOMUX_TO_IRQ_V3(BABBAGE_DVI_DET);
-	set_irq_type(irq, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING);
-	ret = request_irq(irq, dvi_det_int, 0, "dvi_det", 0);
-	if (ret) {
-		pr_info("register DVI detect interrupt failed\n");
-		return -1;
-	}
-	return 0;
-}
-late_initcall(mxc_init_dvi_det);
-
-
 #define PWGT1SPIEN (1<<15)
 #define PWGT2SPIEN (1<<16)
 #define USEROFFSPI (1<<3)
@@ -1174,7 +811,7 @@ static int __init mxc_init_power_key(void)
 {
 	/* Set power key as wakeup resource */
 	int irq, ret;
-	irq = IOMUX_TO_IRQ_V3(BABBAGE_POWER_KEY);
+	irq = IOMUX_TO_IRQ(MX51_PIN_EIM_A27);
 	set_irq_type(irq, IRQF_TRIGGER_RISING);
 	ret = request_irq(irq, power_key_int, 0, "power_key", 0);
 	if (ret)
@@ -1185,113 +822,6 @@ static int __init mxc_init_power_key(void)
 }
 late_initcall(mxc_init_power_key);
 
-static void __init mx51_babbage_io_init(void)
-{
-	mxc_iomux_v3_setup_multiple_pads(mx51babbage_pads,
-					ARRAY_SIZE(mx51babbage_pads));
-
-	gpio_request(BABBAGE_PMIC_INT, "pmic-int");
-	gpio_request(BABBAGE_SD1_CD, "sdhc1-detect");
-	gpio_request(BABBAGE_SD1_WP, "sdhc1-wp");
-
-	gpio_direction_input(BABBAGE_PMIC_INT);
-	gpio_direction_input(BABBAGE_SD1_CD);
-	gpio_direction_input(BABBAGE_SD1_WP);
-
-	if (board_is_rev(BOARD_REV_2)) {
-		/* SD2 CD for BB2.5 */
-		gpio_request(BABBAGE_SD2_CD_2_5, "sdhc2-detect");
-		gpio_direction_input(BABBAGE_SD2_CD_2_5);
-	} else {
-		/* SD2 CD for BB2.0 */
-		gpio_request(BABBAGE_SD2_CD_2_0, "sdhc2-detect");
-		gpio_direction_input(BABBAGE_SD2_CD_2_0);
-	}
-	gpio_request(BABBAGE_SD2_WP, "sdhc2-wp");
-	gpio_direction_input(BABBAGE_SD2_WP);
-
-	/* reset usbh1 hub */
-	gpio_request(BABBAGE_USBH1_HUB_RST, "hub-rst");
-	gpio_direction_output(BABBAGE_USBH1_HUB_RST, 0);
-	gpio_set_value(BABBAGE_USBH1_HUB_RST, 0);
-	msleep(1);
-	gpio_set_value(BABBAGE_USBH1_HUB_RST, 1);
-
-	/* reset FEC PHY */
-	gpio_request(BABBAGE_FEC_PHY_RESET, "fec-phy-reset");
-	gpio_direction_output(BABBAGE_FEC_PHY_RESET, 0);
-	msleep(10);
-	gpio_set_value(BABBAGE_FEC_PHY_RESET, 1);
-
-	/* reset FM */
-	gpio_request(BABBAGE_FM_RESET, "fm-reset");
-	gpio_direction_output(BABBAGE_FM_RESET, 0);
-	msleep(10);
-	gpio_set_value(BABBAGE_FM_RESET, 1);
-
-	/* Drive 26M_OSC_EN line high */
-	gpio_request(BABBAGE_26M_OSC_EN, "26m-osc-en");
-	gpio_direction_output(BABBAGE_26M_OSC_EN, 1);
-
-	/* Drive USB_CLK_EN_B line low */
-	gpio_request(BABBAGE_USB_CLK_EN_B, "usb-clk_en_b");
-	gpio_direction_output(BABBAGE_USB_CLK_EN_B, 0);
-
-	/* De-assert USB PHY RESETB */
-	gpio_request(BABBAGE_PHY_RESET, "usb-phy-reset");
-	gpio_direction_output(BABBAGE_PHY_RESET, 1);
-
-	/* hphone_det_b */
-	gpio_request(BABBAGE_HEADPHONE_DET, "hphone-det");
-	gpio_direction_input(BABBAGE_HEADPHONE_DET);
-
-	/* audio_clk_en_b */
-	gpio_request(BABBAGE_AUDIO_CLK_EN, "audio-clk-en");
-	gpio_direction_output(BABBAGE_AUDIO_CLK_EN, 0);
-
-	/* power key */
-	gpio_request(BABBAGE_POWER_KEY, "power-key");
-	gpio_direction_input(BABBAGE_POWER_KEY);
-
-	if (cpu_is_mx51_rev(CHIP_REV_3_0) > 0) {
-		/* DVI_I2C_ENB = 0 tristates the DVI I2C level shifter */
-		gpio_request(BABBAGE_DVI_I2C_EN, "dvi-i2c-en");
-		gpio_direction_output(BABBAGE_DVI_I2C_EN, 0);
-	}
-
-	/* Deassert VGA reset to free i2c bus */
-	gpio_request(BABBAGE_VGA_RESET, "vga-reset");
-	gpio_direction_output(BABBAGE_VGA_RESET, 1);
-
-	/* LCD related gpio */
-	gpio_request(BABBAGE_DISP_BRIGHTNESS_CTL, "disp-brightness-ctl");
-	gpio_request(BABBAGE_LVDS_POWER_DOWN, "lvds-power-down");
-	gpio_request(BABBAGE_LCD_3V3_ON, "lcd-3v3-on");
-	gpio_request(BABBAGE_LCD_5V_ON, "lcd-5v-on");
-	gpio_direction_output(BABBAGE_DISP_BRIGHTNESS_CTL, 0);
-	gpio_direction_output(BABBAGE_LVDS_POWER_DOWN, 0);
-	gpio_direction_output(BABBAGE_LCD_3V3_ON, 0);
-	gpio_direction_output(BABBAGE_LCD_5V_ON, 0);
-
-	/* Camera reset */
-	gpio_request(BABBAGE_CAM_RESET, "cam-reset");
-	gpio_direction_output(BABBAGE_CAM_RESET, 1);
-
-	/* Camera low power */
-	gpio_request(BABBAGE_CAM_LOW_POWER, "cam-low-power");
-	gpio_direction_output(BABBAGE_CAM_LOW_POWER, 0);
-
-	/* OSC_EN */
-	gpio_request(BABBAGE_OSC_EN_B, "osc-en");
-	gpio_direction_output(BABBAGE_OSC_EN_B, 1);
-
-	if (enable_w1) {
-		/* OneWire */
-		struct pad_desc onewire = MX51_PAD_OWIRE_LINE__OWIRE_LINE;
-		mxc_iomux_v3_setup_pad(&onewire);
-	}
-}
-
 /*!
  * Board specific initialization.
  */
@@ -1299,16 +829,14 @@ static void __init mxc_board_init(void)
 {
 	mxc_ipu_data.di_clk[0] = clk_get(NULL, "ipu_di0_clk");
 	mxc_ipu_data.di_clk[1] = clk_get(NULL, "ipu_di1_clk");
-	mxc_ipu_data.csi_clk[0] = clk_get(NULL, "csi_mclk1");
-	mxc_ipu_data.csi_clk[1] = clk_get(NULL, "csi_mclk2");
 
 	mxc_spdif_data.spdif_core_clk = clk_get(NULL, "spdif_xtal_clk");
 	clk_put(mxc_spdif_data.spdif_core_clk);
 	/* SD card detect irqs */
-	mxcsdhc2_device.resource[2].start = IOMUX_TO_IRQ_V3(BABBAGE_SD2_CD_2_5);
-	mxcsdhc2_device.resource[2].end = IOMUX_TO_IRQ_V3(BABBAGE_SD2_CD_2_5);
-	mxcsdhc1_device.resource[2].start = IOMUX_TO_IRQ_V3(BABBAGE_SD1_CD);
-	mxcsdhc1_device.resource[2].end = IOMUX_TO_IRQ_V3(BABBAGE_SD1_CD);
+	mxcsdhc2_device.resource[2].start = IOMUX_TO_IRQ(MX51_PIN_GPIO1_6);
+	mxcsdhc2_device.resource[2].end = IOMUX_TO_IRQ(MX51_PIN_GPIO1_6);
+	mxcsdhc1_device.resource[2].start = IOMUX_TO_IRQ(MX51_PIN_GPIO1_0);
+	mxcsdhc1_device.resource[2].end = IOMUX_TO_IRQ(MX51_PIN_GPIO1_0);
 
 	mxc_cpu_common_init();
 	mxc_register_gpios();
@@ -1341,12 +869,7 @@ static void __init mxc_board_init(void)
 	mxc_register_device(&mxc_ssi1_device, NULL);
 	mxc_register_device(&mxc_ssi2_device, NULL);
 	mxc_register_device(&mxc_alsa_spdif_device, &mxc_spdif_data);
-	mxc_register_device(&mxc_fec_device, &fec_data);
-	mxc_register_device(&mxc_v4l2_device, NULL);
-	mxc_register_device(&mxc_v4l2out_device, NULL);
-	mxc_register_device(&mxc_android_pmem_device, &android_pmem_pdata);
-	mxc_register_device(&mxc_android_pmem_gpu_device, &android_pmem_gpu_pdata);
-	mxc_register_device(&android_usb_device, &android_usb_pdata);
+	mxc_register_device(&mxc_fec_device, NULL);
 
 	mx51_babbage_init_mc13892();
 
@@ -1377,8 +900,8 @@ static void __init mxc_board_init(void)
 	if (cpu_is_mx51_rev(CHIP_REV_1_1) == 2) {
 		sgtl5000_data.sysclk = 26000000;
 	}
-	gpio_request(BABBAGE_AUDAMP_STBY, "audioamp-stdby");
-	gpio_direction_output(BABBAGE_AUDAMP_STBY, 0);
+	gpio_request(IOMUX_TO_GPIO(MX51_PIN_EIM_A23), "eim_a23");
+	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A23), 0);
 	mxc_register_device(&mxc_sgtl5000_device, &sgtl5000_data);
 
 	mx5_usb_dr_init();
diff --git a/arch/arm/mach-mx5/mx51_babbage_gpio.c b/arch/arm/mach-mx5/mx51_babbage_gpio.c
index 4b3e2ee73faf..5d484b78832b 100644
--- a/arch/arm/mach-mx5/mx51_babbage_gpio.c
+++ b/arch/arm/mach-mx5/mx51_babbage_gpio.c
@@ -270,59 +270,83 @@ static struct mxc_iomux_pin_cfg __initdata mxc_iomux_pins[] = {
 	 },
 	{
 	 MX51_PIN_SD1_CMD, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION,
-	 (PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST),
+	 (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH
+	  | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE
+	  | PAD_CTL_SRE_FAST),
 	 },
 	{
 	 MX51_PIN_SD1_CLK, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION,
-	 (PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST),
+	 (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | PAD_CTL_HYS_ENABLE
+	  | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE
+	  | PAD_CTL_SRE_FAST),
 	 },
 	{
 	 MX51_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST),
+	 (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH
+	  | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE
+	  | PAD_CTL_SRE_FAST),
 	 },
 	{
 	 MX51_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST),
+	 (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH
+	  | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE
+	  | PAD_CTL_SRE_FAST),
 	 },
 	{
 	 MX51_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST),
+	 (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH
+	  | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE
+	  | PAD_CTL_SRE_FAST),
 	 },
 	{
 	 MX51_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST),
+	 (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH
+	  | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE
+	  | PAD_CTL_SRE_FAST),
 	 },
 	{
 	 MX51_PIN_GPIO1_0, IOMUX_CONFIG_GPIO | IOMUX_CONFIG_SION,
 	 (PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU),
 	 },
 	{
-	 MX51_PIN_GPIO1_1, IOMUX_CONFIG_GPIO | IOMUX_CONFIG_SION,
+	 MX51_PIN_GPIO1_1, IOMUX_CONFIG_GPIO,
 	 (PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU),
 	 },
 	{
 	 MX51_PIN_SD2_CMD, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION,
-	 (PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST),
+	 (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH
+	  | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE
+	  | PAD_CTL_SRE_FAST),
 	 },
 	{
 	 MX51_PIN_SD2_CLK, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION,
-	 (PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST),
+	 (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | PAD_CTL_HYS_ENABLE
+	  | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE
+	  | PAD_CTL_SRE_FAST),
 	 },
 	{
-	 MX51_PIN_SD2_DATA0, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST),
+	 MX51_PIN_SD2_DATA0, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION,
+	 (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH
+	  | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE
+	  | PAD_CTL_SRE_FAST),
 	 },
 	{
-	 MX51_PIN_SD2_DATA1, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST),
+	 MX51_PIN_SD2_DATA1, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION,
+	 (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH
+	  | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE
+	  | PAD_CTL_SRE_FAST),
 	 },
 	{
-	 MX51_PIN_SD2_DATA2, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST),
+	 MX51_PIN_SD2_DATA2, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION,
+	 (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH
+	  | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE
+	  | PAD_CTL_SRE_FAST),
 	 },
 	{
-	 MX51_PIN_SD2_DATA3, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST),
+	 MX51_PIN_SD2_DATA3, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION,
+	 (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH
+	  | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE
+	  | PAD_CTL_SRE_FAST),
 	 },
 	{
 	 MX51_PIN_GPIO1_4, IOMUX_CONFIG_GPIO | IOMUX_CONFIG_SION,
@@ -461,7 +485,7 @@ static int __initdata enable_w1 = { 0 };
 static int __init w1_setup(char *__unused)
 {
 	enable_w1 = 1;
-	return 1;
+	return cpu_is_mx51();
 }
 
 __setup("w1", w1_setup);
diff --git a/arch/arm/mach-mx5/mx51_babbage_pmic_mc13892.c b/arch/arm/mach-mx5/mx51_babbage_pmic_mc13892.c
index 1626c95d54d2..c97d2191b94b 100644
--- a/arch/arm/mach-mx5/mx51_babbage_pmic_mc13892.c
+++ b/arch/arm/mach-mx5/mx51_babbage_pmic_mc13892.c
@@ -23,8 +23,8 @@
 #include <linux/regulator/machine.h>
 #include <linux/mfd/mc13892/core.h>
 #include <mach/irqs.h>
-#include <mach/hardware.h>
-#include <mach/iomux-mx51.h>
+#include "iomux.h"
+#include "mx51_pins.h"
 
 /*
  * Convenience conversion.
@@ -406,7 +406,7 @@ static struct mc13892_platform_data mc13892_plat = {
 
 static struct spi_board_info __initdata mc13892_spi_device = {
 	.modalias = "pmic_spi",
-	.irq = IOMUX_TO_IRQ_V3(8),
+	.irq = IOMUX_TO_IRQ(MX51_PIN_GPIO1_8),
 	.max_speed_hz = 6000000,	/* max spi SCK clock speed in HZ */
 	.bus_num = 1,
 	.chip_select = 0,
diff --git a/arch/arm/mach-mx5/mx51_ccwmx51js.c b/arch/arm/mach-mx5/mx51_ccwmx51js.c
index bbacfc981d73..0ac060056f35 100644
--- a/arch/arm/mach-mx5/mx51_ccwmx51js.c
+++ b/arch/arm/mach-mx5/mx51_ccwmx51js.c
@@ -51,8 +51,6 @@
 #include "mx51_pins.h"
 #include "devices_ccwmx51.h"
 #include "usb.h"
-#include "linux/android_pmem.h"
-#include "linux/usb/android.h"
 
 extern struct cpu_wp *(*get_cpu_wp)(int *wp);
 extern void (*set_num_cpu_wp)(int num);
@@ -145,36 +143,6 @@ void mx51_set_num_cpu_wp(int num)
 	return;
 }
 
-#if defined CONFIG_ANDROID_PMEM
-static struct android_pmem_platform_data android_pmem_pdata = {
-	.name = "pmem_adsp",
-	.start = 0,
-	.size = SZ_32M,
-	.no_allocator = 0,
-	.cached = PMEM_NONCACHE_NORMAL,
-};
-
-static struct android_pmem_platform_data android_pmem_gpu_pdata = {
-	.name = "pmem_gpu",
-	.start = 0,
-	.size = SZ_32M,
-	.no_allocator = 0,
-	.cached = PMEM_CACHE_ENABLE,
-};
-#endif
-
-#ifdef CONFIG_USB_ANDROID
-static struct android_usb_platform_data android_usb_pdata = {
-	.vendor_id      = 0x0bb4,
-	.product_id     = 0x0c01,
-	.adb_product_id = 0x0c02,
-	.version        = 0x0100,
-	.product_name   = "Android Phone",
-	.manufacturer_name = "Freescale",
-	.nluns = 3,
-};
-#endif
-
 /*!
  * Board specific fixup function. It is called by \b setup_arch() in
  * setup.c file very early on during kernel starts. It allows the user to
@@ -189,48 +157,19 @@ static struct android_usb_platform_data android_usb_pdata = {
 static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags,
 				   char **cmdline, struct meminfo *mi)
 {
-	struct tag *t;
-#ifdef CONFIG_ANDROID
-	int size;
-#else
 	char *str;
+	struct tag *t;
 	struct tag *mem_tag = 0;
 	int total_mem = SZ_512M;
 	int left_mem = 0;
 	int gpu_mem = SZ_64M;
 	int fb_mem = FB_MEM_SIZE;
-#endif
 
 	mxc_set_cpu_type(MXC_CPU_MX51);
 
 	get_cpu_wp = mx51_get_cpu_wp;
 	set_num_cpu_wp = mx51_set_num_cpu_wp;
 
-#ifdef CONFIG_ANDROID
-	// TODO: Dual head support for Android.
-	// See commit 358e938e78b3380357f8f0c6dd54fa9fe4cc84c5
-	// This commit removes Digi's dual display customizations
-
-	for_each_tag(t, tags) {
-		if (t->hdr.tag != ATAG_MEM)
-			continue;
-		size = t->u.mem.size;
-
-		android_pmem_pdata.start =
-				PHYS_OFFSET + size - android_pmem_pdata.size;
-		android_pmem_gpu_pdata.start =
-				android_pmem_pdata.start - android_pmem_gpu_pdata.size;
-		gpu_device.resource[5].start =
-				android_pmem_gpu_pdata.start - SZ_16M;
-		gpu_device.resource[5].end =
-				gpu_device.resource[5].start + SZ_16M - 1;
-		size -= android_pmem_pdata.size;
-		size -= android_pmem_gpu_pdata.size;
-		size -= SZ_16M;
-		t->u.mem.size = size;
-	}
-
-#else
 	for_each_tag(mem_tag, tags) {
 		if (mem_tag->hdr.tag == ATAG_MEM) {
 			total_mem = mem_tag->u.mem.size;
@@ -268,7 +207,6 @@ static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags,
 			fb_mem = 0;
 		}
 		mem_tag->u.mem.size = left_mem;
-
 #if defined(CONFIG_CCWMX51_DISP1) && defined(CONFIG_CCWMX51_DISP2)
 		fb_mem = fb_mem / 2;	/* Divide the mem for between the displays */
 #endif
@@ -298,9 +236,6 @@ static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags,
 		}
 #endif
 	}
-#endif
-
-
 }
 
 #define PWGT1SPIEN (1<<15)
@@ -376,13 +311,6 @@ static void __init mxc_board_init(void)
 #endif
 	mxc_register_device(&mxc_pwm1_device, NULL);
 	mxc_register_device(&mxc_pwm_backlight_device, &mxc_pwm_backlight_data);
-#ifdef CONFIG_ANDROID_PMEM
-	mxc_register_device(&mxc_android_pmem_device, &android_pmem_pdata);
-	mxc_register_device(&mxc_android_pmem_gpu_device, &android_pmem_gpu_pdata);
-#endif
-#ifdef CONFIG_USB_ANDROID
-	mxc_register_device(&android_usb_device, &android_usb_pdata);
-#endif
 
 #ifdef CONFIG_ESDHCI_MXC_SELECT1
 	ccwmx51_register_sdio(0);	/* SDHC1 */
@@ -393,7 +321,7 @@ static void __init mxc_board_init(void)
 #endif /* CONFIG_ESDHCI_MXC_SELECT3 && !CONFIG_PATA_FSL && !CONFIG_PATA_FSL_MODULE */
 
 #if defined(CONFIG_FEC) || defined(CONFIG_FEC_MODULE)
-	mxc_register_device(&mxc_fec_device, &fec_data);
+	mxc_register_device(&mxc_fec_device, NULL);
 #endif
 #if defined(CONFIG_MTD_NAND_MXC) \
 	|| defined(CONFIG_MTD_NAND_MXC_MODULE) \
@@ -435,9 +363,6 @@ static void __init mxc_board_init(void)
 #ifdef CONFIG_CCWMX51_SECOND_TOUCH
 	ccwmx51_init_2nd_touch();
 #endif
-#if defined(CONFIG_KEYBOARD_GPIO)
-	mxc_register_device(&ccwmx51js_keys_gpio, &ccwmx51js_gpio_key_info);
-#endif
 	pm_power_off = mxc_power_off;
 }
 
diff --git a/arch/arm/mach-mx5/mx53_evk.c b/arch/arm/mach-mx5/mx53_evk.c
index 702d7d8912d0..443857c76a84 100644
--- a/arch/arm/mach-mx5/mx53_evk.c
+++ b/arch/arm/mach-mx5/mx53_evk.c
@@ -57,47 +57,11 @@
 #include <mach/gpio.h>
 #include <mach/mmc.h>
 #include <mach/mxc_dvfs.h>
-#include <mach/iomux-mx53.h>
-
+#include "iomux.h"
+#include "mx53_pins.h"
 #include "crm_regs.h"
 #include "devices.h"
 #include "usb.h"
-#include <linux/android_pmem.h>
-#include <linux/usb/android.h>
-
-#define ARM2_SD1_CD			(0*32 + 1)	/* GPIO_1_1 */
-
-#define MX53_HP_DETECT			(1*32 + 5)	/* GPIO_2_5 */
-
-#define EVK_SD3_CD			(2*32 + 11)	/* GPIO_3_11 */
-#define EVK_SD3_WP			(2*32 + 12)	/* GPIO_3_12 */
-#define EVK_SD1_CD			(2*32 + 13)	/* GPIO_3_13 */
-#define EVK_SD1_WP			(2*32 + 14)	/* GPIO_3_14 */
-#define ARM2_OTG_VBUS			(2*32 + 22)	/* GPIO_3_22 */
-#define MX53_DVI_PD			(2*32 + 24)	/* GPIO_3_24 */
-#define EVK_TS_INT			(2*32 + 26)	/* GPIO_3_26 */
-#define MX53_DVI_I2C			(2*32 + 28)	/* GPIO_3_28 */
-#define MX53_DVI_DETECT		(2*32 + 31)	/* GPIO_3_31 */
-
-#define MX53_CAM_RESET			(3*32 + 0)	/* GPIO_4_0 */
-#define MX53_ESAI_RESET			(3*32 + 2)	/* GPIO_4_2 */
-#define MX53_CAN2_EN2			(3*32 + 4)	/* GPIO_4_4 */
-#define MX53_12V_EN			(3*32 + 5)	/* GPIO_4_5 */
-#define ARM2_LCD_CONTRAST		(3*32 + 20)	/* GPIO_4_20 */
-
-#define MX53_DVI_RESET			(4*32 + 0)	/* GPIO_5_0 */
-#define EVK_USB_HUB_RESET		(4*32 + 20)	/* GPIO_5_20 */
-#define MX53_TVIN_PWR			(4*32 + 23)	/* GPIO_5_23 */
-#define MX53_CAN2_EN1			(4*32 + 24)	/* GPIO_5_24 */
-#define MX53_TVIN_RESET			(4*32 + 25)	/* GPIO_5_25 */
-
-#define EVK_OTG_VBUS			(5*32 + 6)	/* GPIO_6_6 */
-
-#define EVK_FEC_PHY_RESET		(6*32 + 6)	/* GPIO_7_6 */
-#define EVK_USBH1_VBUS			(6*32 + 8)	/* GPIO_7_8 */
-#define MX53_PMIC_INT			(6*32 + 11)	/* GPIO_7_11 */
-#define MX53_CAN1_EN1			(6*32 + 12)	/* GPIO_7_12 */
-#define MX53_CAN1_EN2			(6*32 + 13)	/* GPIO_7_13 */
 
 /*!
  * @file mach-mx53/mx53_evk.c
@@ -107,297 +71,11 @@
  * @ingroup MSL_MX53
  */
 extern int __init mx53_evk_init_mc13892(void);
+extern void __init mx53_evk_io_init(void);
 extern struct cpu_wp *(*get_cpu_wp)(int *wp);
 extern void (*set_num_cpu_wp)(int num);
 static int num_cpu_wp = 3;
 
-static struct pad_desc mx53common_pads[] = {
-	MX53_PAD_EIM_WAIT__GPIO_5_0,
-
-	MX53_PAD_EIM_OE__DI1_PIN7,
-	MX53_PAD_EIM_RW__DI1_PIN8,
-
-	MX53_PAD_EIM_A25__DI0_D1_CS,
-
-	MX53_PAD_EIM_D16__CSPI1_SCLK,
-	MX53_PAD_EIM_D17__CSPI1_MISO,
-	MX53_PAD_EIM_D18__CSPI1_MOSI,
-
-	MX53_PAD_EIM_D20__SER_DISP0_CS,
-
-	MX53_PAD_EIM_D23__DI0_D0_CS,
-
-	MX53_PAD_EIM_D24__GPIO_3_24,
-	MX53_PAD_EIM_D26__GPIO_3_26,
-
-	MX53_PAD_EIM_D29__DISPB0_SER_RS,
-
-	MX53_PAD_EIM_D30__DI0_PIN11,
-	MX53_PAD_EIM_D31__DI0_PIN12,
-
-	MX53_PAD_ATA_DA_1__GPIO_7_7,
-	MX53_PAD_ATA_DATA4__GPIO_2_4,
-	MX53_PAD_ATA_DATA5__GPIO_2_5,
-	MX53_PAD_ATA_DATA6__GPIO_2_6,
-
-	MX53_PAD_SD2_CLK__SD2_CLK,
-	MX53_PAD_SD2_CMD__SD2_CMD,
-	MX53_PAD_SD2_DATA0__SD2_DAT0,
-	MX53_PAD_SD2_DATA1__SD2_DAT1,
-	MX53_PAD_SD2_DATA2__SD2_DAT2,
-	MX53_PAD_SD2_DATA3__SD2_DAT3,
-	MX53_PAD_ATA_DATA12__SD2_DAT4,
-	MX53_PAD_ATA_DATA13__SD2_DAT5,
-	MX53_PAD_ATA_DATA14__SD2_DAT6,
-	MX53_PAD_ATA_DATA15__SD2_DAT7,
-
-	MX53_PAD_CSI0_D10__UART1_TXD,
-	MX53_PAD_CSI0_D11__UART1_RXD,
-
-	MX53_PAD_ATA_BUFFER_EN__UART2_RXD,
-	MX53_PAD_ATA_DMARQ__UART2_TXD,
-	MX53_PAD_ATA_DIOR__UART2_RTS,
-	MX53_PAD_ATA_INTRQ__UART2_CTS,
-
-	MX53_PAD_ATA_CS_0__UART3_TXD,
-	MX53_PAD_ATA_CS_1__UART3_RXD,
-
-	MX53_PAD_KEY_COL0__AUD5_TXC,
-	MX53_PAD_KEY_ROW0__AUD5_TXD,
-	MX53_PAD_KEY_COL1__AUD5_TXFS,
-	MX53_PAD_KEY_ROW1__AUD5_RXD,
-
-	MX53_PAD_CSI0_D7__GPIO_5_25,
-
-	MX53_PAD_GPIO_2__MLBDAT,
-	MX53_PAD_GPIO_3__MLBCLK,
-
-	MX53_PAD_GPIO_6__MLBSIG,
-
-	MX53_PAD_GPIO_4__GPIO_1_4,
-	MX53_PAD_GPIO_7__GPIO_1_7,
-	MX53_PAD_GPIO_8__GPIO_1_8,
-
-	MX53_PAD_GPIO_10__GPIO_4_0,
-
-	MX53_PAD_KEY_COL2__TXCAN1,
-	MX53_PAD_KEY_ROW2__RXCAN1,
-
-	/* CAN1 -- EN */
-	MX53_PAD_GPIO_18__GPIO_7_13,
-	/* CAN1 -- STBY */
-	MX53_PAD_GPIO_17__GPIO_7_12,
-	/* CAN1 -- NERR */
-	MX53_PAD_GPIO_5__GPIO_1_5,
-
-	MX53_PAD_KEY_COL4__TXCAN2,
-	MX53_PAD_KEY_ROW4__RXCAN2,
-
-	/* CAN2 -- EN */
-	MX53_PAD_CSI0_D6__GPIO_5_24,
-	/* CAN2 -- STBY */
-	MX53_PAD_GPIO_14__GPIO_4_4,
-	/* CAN2 -- NERR */
-	MX53_PAD_CSI0_D4__GPIO_5_22,
-
-	MX53_PAD_GPIO_11__GPIO_4_1,
-	MX53_PAD_GPIO_12__GPIO_4_2,
-	MX53_PAD_GPIO_13__GPIO_4_3,
-	MX53_PAD_GPIO_16__GPIO_7_11,
-	MX53_PAD_GPIO_19__GPIO_4_5,
-
-	/* DI0 display clock */
-	MX53_PAD_DI0_DISP_CLK__DI0_DISP_CLK,
-
-	/* DI0 data enable */
-	MX53_PAD_DI0_PIN15__DI0_PIN15,
-	/* DI0 HSYNC */
-	MX53_PAD_DI0_PIN2__DI0_PIN2,
-	/* DI0 VSYNC */
-	MX53_PAD_DI0_PIN3__DI0_PIN3,
-
-	MX53_PAD_DISP0_DAT0__DISP0_DAT0,
-	MX53_PAD_DISP0_DAT1__DISP0_DAT1,
-	MX53_PAD_DISP0_DAT2__DISP0_DAT2,
-	MX53_PAD_DISP0_DAT3__DISP0_DAT3,
-	MX53_PAD_DISP0_DAT4__DISP0_DAT4,
-	MX53_PAD_DISP0_DAT5__DISP0_DAT5,
-	MX53_PAD_DISP0_DAT6__DISP0_DAT6,
-	MX53_PAD_DISP0_DAT7__DISP0_DAT7,
-	MX53_PAD_DISP0_DAT8__DISP0_DAT8,
-	MX53_PAD_DISP0_DAT9__DISP0_DAT9,
-	MX53_PAD_DISP0_DAT10__DISP0_DAT10,
-	MX53_PAD_DISP0_DAT11__DISP0_DAT11,
-	MX53_PAD_DISP0_DAT12__DISP0_DAT12,
-	MX53_PAD_DISP0_DAT13__DISP0_DAT13,
-	MX53_PAD_DISP0_DAT14__DISP0_DAT14,
-	MX53_PAD_DISP0_DAT15__DISP0_DAT15,
-	MX53_PAD_DISP0_DAT16__DISP0_DAT16,
-	MX53_PAD_DISP0_DAT17__DISP0_DAT17,
-	MX53_PAD_DISP0_DAT18__DISP0_DAT18,
-	MX53_PAD_DISP0_DAT19__DISP0_DAT19,
-	MX53_PAD_DISP0_DAT20__DISP0_DAT20,
-	MX53_PAD_DISP0_DAT21__DISP0_DAT21,
-	MX53_PAD_DISP0_DAT22__DISP0_DAT22,
-	MX53_PAD_DISP0_DAT23__DISP0_DAT23,
-
-	MX53_PAD_LVDS0_TX3_P__LVDS0_TX3,
-	MX53_PAD_LVDS0_CLK_P__LVDS0_CLK,
-	MX53_PAD_LVDS0_TX2_P__LVDS0_TX2,
-	MX53_PAD_LVDS0_TX1_P__LVDS0_TX1,
-	MX53_PAD_LVDS0_TX0_P__LVDS0_TX0,
-
-	MX53_PAD_LVDS1_TX3_P__LVDS1_TX3,
-	MX53_PAD_LVDS1_CLK_P__LVDS1_CLK,
-	MX53_PAD_LVDS1_TX2_P__LVDS1_TX2,
-	MX53_PAD_LVDS1_TX1_P__LVDS1_TX1,
-	MX53_PAD_LVDS1_TX0_P__LVDS1_TX0,
-
-	/* audio and CSI clock out */
-	MX53_PAD_GPIO_0__SSI_EXT1_CLK,
-
-	MX53_PAD_CSI0_D12__CSI0_D12,
-	MX53_PAD_CSI0_D13__CSI0_D13,
-	MX53_PAD_CSI0_D14__CSI0_D14,
-	MX53_PAD_CSI0_D15__CSI0_D15,
-	MX53_PAD_CSI0_D16__CSI0_D16,
-	MX53_PAD_CSI0_D17__CSI0_D17,
-	MX53_PAD_CSI0_D18__CSI0_D18,
-	MX53_PAD_CSI0_D19__CSI0_D19,
-
-	MX53_PAD_CSI0_VSYNC__CSI0_VSYNC,
-	MX53_PAD_CSI0_MCLK__CSI0_HSYNC,
-	MX53_PAD_CSI0_PIXCLK__CSI0_PIXCLK,
-	/* Camera low power */
-	MX53_PAD_CSI0_D5__GPIO_5_23,
-
-	/* esdhc1 */
-	MX53_PAD_SD1_CMD__SD1_CMD,
-	MX53_PAD_SD1_CLK__SD1_CLK,
-	MX53_PAD_SD1_DATA0__SD1_DATA0,
-	MX53_PAD_SD1_DATA1__SD1_DATA1,
-	MX53_PAD_SD1_DATA2__SD1_DATA2,
-	MX53_PAD_SD1_DATA3__SD1_DATA3,
-
-	/* esdhc3 */
-	MX53_PAD_ATA_DATA8__SD3_DAT0,
-	MX53_PAD_ATA_DATA9__SD3_DAT1,
-	MX53_PAD_ATA_DATA10__SD3_DAT2,
-	MX53_PAD_ATA_DATA11__SD3_DAT3,
-	MX53_PAD_ATA_DATA0__SD3_DAT4,
-	MX53_PAD_ATA_DATA1__SD3_DAT5,
-	MX53_PAD_ATA_DATA2__SD3_DAT6,
-	MX53_PAD_ATA_DATA3__SD3_DAT7,
-	MX53_PAD_ATA_RESET_B__SD3_CMD,
-	MX53_PAD_ATA_IORDY__SD3_CLK,
-
-	/* FEC pins */
-	MX53_PAD_FEC_MDIO__FEC_MDIO,
-	MX53_PAD_FEC_REF_CLK__FEC_REF_CLK,
-	MX53_PAD_FEC_RX_ER__FEC_RX_ER,
-	MX53_PAD_FEC_CRS_DV__FEC_CRS_DV,
-	MX53_PAD_FEC_RXD1__FEC_RXD1,
-	MX53_PAD_FEC_RXD0__FEC_RXD0,
-	MX53_PAD_FEC_TX_EN__FEC_TX_EN,
-	MX53_PAD_FEC_TXD1__FEC_TXD1,
-	MX53_PAD_FEC_TXD0__FEC_TXD0,
-	MX53_PAD_FEC_MDC__FEC_MDC,
-
-	MX53_PAD_CSI0_D8__I2C1_SDA,
-	MX53_PAD_CSI0_D9__I2C1_SCL,
-
-	MX53_PAD_KEY_COL3__I2C2_SCL,
-	MX53_PAD_KEY_ROW3__I2C2_SDA,
-};
-
-static struct pad_desc mx53evk_pads[] = {
-	/* USB OTG USB_OC */
-	MX53_PAD_EIM_A24__GPIO_5_4,
-
-	/* USB OTG USB_PWR */
-	MX53_PAD_EIM_A23__GPIO_6_6,
-
-	/* DISPB0_SER_CLK */
-	MX53_PAD_EIM_D21__DISPB0_SER_CLK,
-
-	/* DI0_PIN1 */
-	MX53_PAD_EIM_D22__DISPB0_SER_DIN,
-
-	/* DVI I2C ENABLE */
-	MX53_PAD_EIM_D28__GPIO_3_28,
-
-	/* DVI DET */
-	MX53_PAD_EIM_D31__GPIO_3_31,
-
-	/* SDHC1 SD_CD */
-	MX53_PAD_EIM_DA13__GPIO_3_13,
-
-	/* SDHC1 SD_WP */
-	MX53_PAD_EIM_DA14__GPIO_3_14,
-
-	/* SDHC3 SD_CD */
-	MX53_PAD_EIM_DA11__GPIO_3_11,
-
-	/* SDHC3 SD_WP */
-	MX53_PAD_EIM_DA12__GPIO_3_12,
-
-	/* PWM backlight */
-	MX53_PAD_GPIO_1__PWMO,
-
-	/* USB HOST USB_PWR */
-	MX53_PAD_ATA_DA_2__GPIO_7_8,
-
-	/* USB HOST USB_RST */
-	MX53_PAD_CSI0_DATA_EN__GPIO_5_20,
-
-	/* USB HOST CARD_ON */
-	MX53_PAD_EIM_DA15__GPIO_3_15,
-
-	/* USB HOST CARD_RST */
-	MX53_PAD_ATA_DATA7__GPIO_2_7,
-
-	/* USB HOST WAN_WAKE */
-	MX53_PAD_EIM_D25__GPIO_3_25,
-
-	/* FEC_RST */
-	MX53_PAD_ATA_DA_0__GPIO_7_6,
-};
-
-static struct pad_desc mx53arm2_pads[] = {
-	/* USB OTG USB_OC */
-	MX53_PAD_EIM_D21__GPIO_3_21,
-
-	/* USB OTG USB_PWR */
-	MX53_PAD_EIM_D22__GPIO_3_22,
-
-	/* SDHC1 SD_CD */
-	MX53_PAD_GPIO_1__GPIO_1_1,
-
-	/* gpio backlight */
-	MX53_PAD_DI0_PIN4__GPIO_4_20,
-};
-
-static struct pad_desc mx53_nand_pads[] = {
-	MX53_PAD_NANDF_CLE__NANDF_CLE,
-	MX53_PAD_NANDF_ALE__NANDF_ALE,
-	MX53_PAD_NANDF_WP_B__NANDF_WP_B,
-	MX53_PAD_NANDF_WE_B__NANDF_WE_B,
-	MX53_PAD_NANDF_RE_B__NANDF_RE_B,
-	MX53_PAD_NANDF_RB0__NANDF_RB0,
-	MX53_PAD_NANDF_CS0__NANDF_CS0,
-	MX53_PAD_NANDF_CS1__NANDF_CS1	,
-	MX53_PAD_NANDF_CS2__NANDF_CS2,
-	MX53_PAD_NANDF_CS3__NANDF_CS3	,
-	MX53_PAD_EIM_DA0__EIM_DA0,
-	MX53_PAD_EIM_DA1__EIM_DA1,
-	MX53_PAD_EIM_DA2__EIM_DA2,
-	MX53_PAD_EIM_DA3__EIM_DA3,
-	MX53_PAD_EIM_DA4__EIM_DA4,
-	MX53_PAD_EIM_DA5__EIM_DA5,
-	MX53_PAD_EIM_DA6__EIM_DA6,
-	MX53_PAD_EIM_DA7__EIM_DA7,
-};
-
 /* working point(wp): 0 - 800MHz; 1 - 166.25MHz; */
 static struct cpu_wp cpu_wp_auto[] = {
 	{
@@ -511,40 +189,10 @@ static struct platform_pwm_backlight_data mxc_pwm_backlight_data = {
 	.pwm_id = 1,
 	.max_brightness = 255,
 	.dft_brightness = 128,
-	.pwm_period_ns = 50000,
+	.pwm_period_ns = 78770,
 };
 
-static void flexcan_xcvr_enable(int id, int en)
-{
-	static int pwdn;
-	if (id < 0 || id > 1)
-		return;
-
-	if (en) {
-		if (!(pwdn++))
-			gpio_set_value(MX53_12V_EN, 1);
-
-		if (id == 0) {
-			gpio_set_value(MX53_CAN1_EN1, 1);
-			gpio_set_value(MX53_CAN1_EN2, 1);
-		} else {
-			gpio_set_value(MX53_CAN2_EN1, 1);
-			gpio_set_value(MX53_CAN2_EN2, 1);
-		}
-
-	} else {
-		if (!(--pwdn))
-			gpio_set_value(MX53_12V_EN, 0);
-
-		if (id == 0) {
-			gpio_set_value(MX53_CAN1_EN1, 0);
-			gpio_set_value(MX53_CAN1_EN2, 0);
-		} else {
-			gpio_set_value(MX53_CAN2_EN1, 0);
-			gpio_set_value(MX53_CAN2_EN2, 0);
-		}
-	}
-}
+extern void flexcan_xcvr_enable(int id, int en);
 
 static struct flexcan_platform_data flexcan0_data = {
 	.core_reg = NULL,
@@ -594,72 +242,12 @@ static struct mxc_vpu_platform_data mxc_vpu_data = {
 
 static struct fec_platform_data fec_data = {
 	.phy = PHY_INTERFACE_MODE_RMII,
-	.phy_mask = ~1UL,
 };
 
-/* workaround for ecspi chipselect pin may not keep correct level when idle */
-static void mx53_evk_gpio_spi_chipselect_active(int cspi_mode, int status,
-					     int chipselect)
-{
-	switch (cspi_mode) {
-	case 1:
-		switch (chipselect) {
-		case 0x1:
-			{
-			struct pad_desc eim_d19_gpio = MX53_PAD_EIM_D19__GPIO_3_19;
-			struct pad_desc cspi_ss0 = MX53_PAD_EIM_EB2__CSPI_SS0;
-
-			/* de-select SS1 of instance: ecspi1. */
-			mxc_iomux_v3_setup_pad(&eim_d19_gpio);
-			mxc_iomux_v3_setup_pad(&cspi_ss0);
-			}
-			break;
-		case 0x2:
-			{
-			struct pad_desc eim_eb2_gpio = MX53_PAD_EIM_EB2__GPIO_2_30;
-			struct pad_desc cspi_ss1 = MX53_PAD_EIM_D19__CSPI_SS1;
-
-			/* de-select SS0 of instance: ecspi1. */
-			mxc_iomux_v3_setup_pad(&eim_eb2_gpio);
-			mxc_iomux_v3_setup_pad(&cspi_ss1);
-			}
-			break;
-		default:
-			break;
-		}
-		break;
-	case 2:
-		break;
-	case 3:
-		break;
-	default:
-		break;
-	}
-}
-
-static void mx53_evk_gpio_spi_chipselect_inactive(int cspi_mode, int status,
-					       int chipselect)
-{
-	switch (cspi_mode) {
-	case 1:
-		switch (chipselect) {
-		case 0x1:
-			break;
-		case 0x2:
-			break;
-		default:
-			break;
-		}
-		break;
-	case 2:
-		break;
-	case 3:
-		break;
-	default:
-		break;
-	}
-}
-
+extern void mx53_evk_gpio_spi_chipselect_active(int cspi_mode, int status,
+						    int chipselect);
+extern void mx53_evk_gpio_spi_chipselect_inactive(int cspi_mode, int status,
+						      int chipselect);
 static struct mxc_spi_master mxcspi1_data = {
 	.maxchipselect = 4,
 	.spi_version = 23,
@@ -679,11 +267,11 @@ static struct mxc_dvfs_platform_data dvfs_core_data = {
 	.reg_id = "SW1",
 	.clk1_id = "cpu_clk",
 	.clk2_id = "gpc_dvfs_clk",
-	.gpc_cntr_offset = MXC_GPC_CNTR_OFFSET,
-	.gpc_vcr_offset = MXC_GPC_VCR_OFFSET,
-	.ccm_cdcr_offset = MXC_CCM_CDCR_OFFSET,
-	.ccm_cacrr_offset = MXC_CCM_CACRR_OFFSET,
-	.ccm_cdhipr_offset = MXC_CCM_CDHIPR_OFFSET,
+	.gpc_cntr_reg_addr = MXC_GPC_CNTR,
+	.gpc_vcr_reg_addr = MXC_GPC_VCR,
+	.ccm_cdcr_reg_addr = MXC_CCM_CDCR,
+	.ccm_cacrr_reg_addr = MXC_CCM_CACRR,
+	.ccm_cdhipr_reg_addr = MXC_CCM_CDHIPR,
 	.prediv_mask = 0x1F800,
 	.prediv_offset = 11,
 	.prediv_val = 3,
@@ -709,98 +297,18 @@ static struct ldb_platform_data ldb_data = {
 	.ext_ref = 1,
 };
 
-static struct pad_desc mx53esai_pads[] = {
-	MX53_PAD_FEC_MDIO__ESAI_SCKR,
-	MX53_PAD_FEC_REF_CLK__ESAI_FSR,
-	MX53_PAD_FEC_RX_ER__ESAI_HCKR,
-	MX53_PAD_FEC_CRS_DV__ESAI_SCKT,
-	MX53_PAD_FEC_RXD1__ESAI_FST,
-	MX53_PAD_FEC_RXD0__ESAI_HCKT,
-	MX53_PAD_FEC_TX_EN__ESAI_TX3_RX2,
-	MX53_PAD_FEC_TXD1__ESAI_TX2_RX3,
-	MX53_PAD_FEC_TXD0__ESAI_TX4_RX1,
-	MX53_PAD_FEC_MDC__ESAI_TX5_RX0,
-	MX53_PAD_NANDF_CS2__ESAI_TX0,
-	MX53_PAD_NANDF_CS3__ESAI_TX1,
-};
-
-void gpio_activate_esai_ports(void)
-{
-	mxc_iomux_v3_setup_multiple_pads(mx53esai_pads,
-					ARRAY_SIZE(mx53esai_pads));
-}
-
 static struct mxc_esai_platform_data esai_data = {
 	.activate_esai_ports = gpio_activate_esai_ports,
 };
 
-void gpio_cs42888_pdwn(int pdwn)
-{
-	if (pdwn)
-		gpio_set_value(MX53_ESAI_RESET, 0);
-	else
-		gpio_set_value(MX53_ESAI_RESET, 1);
-}
-EXPORT_SYMBOL(gpio_cs42888_pdwn);
-
-static void gpio_usbotg_vbus_active(void)
-{
-	if (board_is_mx53_arm2()) {
-		/* MX53 ARM2 CPU board */
-		/* Enable OTG VBus with GPIO low */
-		gpio_set_value(ARM2_OTG_VBUS, 0);
-	} else  if (board_is_mx53_evk_a()) {
-		/* MX53 EVK board ver A*/
-		/* Enable OTG VBus with GPIO low */
-		gpio_set_value(EVK_OTG_VBUS, 0);
-	} else  if (board_is_mx53_evk_b()) {
-		/* MX53 EVK board ver B*/
-		/* Enable OTG VBus with GPIO high */
-		gpio_set_value(EVK_OTG_VBUS, 1);
-	}
-}
-
-static void gpio_usbotg_vbus_inactive(void)
-{
-	if (board_is_mx53_arm2()) {
-		/* MX53 ARM2 CPU board */
-		/* Disable OTG VBus with GPIO high */
-		gpio_set_value(ARM2_OTG_VBUS, 1);
-	} else  if (board_is_mx53_evk_a()) {
-		/* MX53 EVK board ver A*/
-		/* Disable OTG VBus with GPIO high */
-		gpio_set_value(EVK_OTG_VBUS, 1);
-	} else  if (board_is_mx53_evk_b()) {
-		/* MX53 EVK board ver B*/
-		/* Disable OTG VBus with GPIO low */
-		gpio_set_value(EVK_OTG_VBUS, 0);
-	}
-}
-
-static void mx53_gpio_usbotg_driver_vbus(bool on)
-{
-	if (on)
-		gpio_usbotg_vbus_active();
-	else
-		gpio_usbotg_vbus_inactive();
-}
-
-static void mx53_gpio_host1_driver_vbus(bool on)
-{
-	if (on)
-		gpio_set_value(EVK_USBH1_VBUS, 1);
-	else
-		gpio_set_value(EVK_USBH1_VBUS, 0);
-}
-
 static void adv7180_pwdn(int pwdn)
 {
-	gpio_request(MX53_TVIN_PWR, "tvin-pwr");
-	gpio_direction_output(MX53_TVIN_PWR, 0);
+	gpio_request(IOMUX_TO_GPIO(MX53_PIN_CSI0_D5), "gpio5_23");
+	gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_CSI0_D5), 0);
 	if (pwdn)
-		gpio_set_value(MX53_TVIN_PWR, 0);
+		gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_CSI0_D5), 0);
 	else
-		gpio_set_value(MX53_TVIN_PWR, 1);
+		gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_CSI0_D5), 1);
 }
 
 static struct mxc_tvin_platform_data adv7180_data = {
@@ -871,14 +379,13 @@ device_initcall(mxc_init_fb);
 
 static void camera_pwdn(int pwdn)
 {
-	gpio_request(MX53_TVIN_PWR, "tvin-pwr");
-	gpio_direction_output(MX53_TVIN_PWR, 0);
-	gpio_set_value(MX53_TVIN_PWR, pwdn);
+	gpio_request(IOMUX_TO_GPIO(MX53_PIN_CSI0_D5), "gpio5_23");
+	gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_CSI0_D5), 0);
+	gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_CSI0_D5), pwdn);
 }
 
 static struct mxc_camera_platform_data camera_data = {
 	.analog_regulator = "VSD",
-	.gpo_regulator = "VVIDEO",
 	.mclk = 24000000,
 	.csi = 0,
 	.pwdn = camera_pwdn,
@@ -901,18 +408,6 @@ static struct i2c_board_info mxc_i2c0_board_info[] __initdata = {
 	 },
 };
 
-static void sii9022_hdmi_reset(void)
-{
-	gpio_set_value(MX53_DVI_RESET, 0);
-	msleep(10);
-	gpio_set_value(MX53_DVI_RESET, 1);
-	msleep(10);
-}
-
-static struct mxc_lcd_platform_data sii9022_hdmi_data = {
-	.reset = sii9022_hdmi_reset,
-};
-
 /* TO DO add platform data */
 static struct i2c_board_info mxc_i2c1_board_info[] __initdata = {
 	{
@@ -922,7 +417,7 @@ static struct i2c_board_info mxc_i2c1_board_info[] __initdata = {
 	{
 	 .type = "tsc2007",
 	 .addr = 0x48,
-	 .irq  = IOMUX_TO_IRQ_V3(EVK_TS_INT),
+	 .irq  = IOMUX_TO_IRQ(MX53_PIN_EIM_A25),
 	},
 	{
 	 .type = "backlight-i2c",
@@ -936,11 +431,6 @@ static struct i2c_board_info mxc_i2c1_board_info[] __initdata = {
 	 .type = "eeprom",
 	 .addr = 0x50,
 	 },
-	{
-	.type = "sii9022",
-	.addr = 0x39,
-	.platform_data = &sii9022_hdmi_data,
-	},
 };
 
 static struct mtd_partition mxc_dataflash_partitions[] = {
@@ -978,9 +468,9 @@ static int sdhc_write_protect(struct device *dev)
 
 	if (!board_is_mx53_arm2()) {
 		if (to_platform_device(dev)->id == 0)
-			rc = gpio_get_value(EVK_SD1_WP);
+			rc = gpio_get_value(IOMUX_TO_GPIO(MX53_PIN_EIM_DA14));
 		else
-			rc = gpio_get_value(EVK_SD3_WP);
+			rc = gpio_get_value(IOMUX_TO_GPIO(MX53_PIN_EIM_DA12));
 	}
 
 	return rc;
@@ -991,14 +481,14 @@ static unsigned int sdhc_get_card_det_status(struct device *dev)
 	int ret;
 	if (board_is_mx53_arm2()) {
 		if (to_platform_device(dev)->id == 0)
-			ret = gpio_get_value(ARM2_SD1_CD);
+			ret = gpio_get_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_1));
 		else
 			ret = 1;
 	} else {
 		if (to_platform_device(dev)->id == 0) {
-			ret = gpio_get_value(EVK_SD1_CD);
+			ret = gpio_get_value(IOMUX_TO_GPIO(MX53_PIN_EIM_DA13));
 		} else{		/* config the det pin for SDHC3 */
-			ret = gpio_get_value(EVK_SD3_CD);
+			ret = gpio_get_value(IOMUX_TO_GPIO(MX53_PIN_EIM_DA11));
 			}
 	}
 
@@ -1029,7 +519,6 @@ static struct mxc_mmc_platform_data mmc3_data = {
 	.status = sdhc_get_card_det_status,
 	.wp_status = sdhc_write_protect,
 	.clock_mmc = "esdhc_clk",
-	.clk_always_on = 1,
 };
 
 /* return value 1 failure, 0 success */
@@ -1195,7 +684,7 @@ return 0;
 
 static int headphone_det_status(void)
 {
-	return (gpio_get_value(MX53_HP_DETECT) == 0);
+	return (gpio_get_value(IOMUX_TO_GPIO(MX53_PIN_ATA_DATA5)) == 0);
 }
 
 static int mxc_sgtl5000_init(void);
@@ -1204,7 +693,7 @@ static struct mxc_audio_platform_data sgtl5000_data = {
 	.ssi_num = 1,
 	.src_port = 2,
 	.ext_port = 5,
-	.hp_irq = IOMUX_TO_IRQ(MX53_HP_DETECT),
+	.hp_irq = IOMUX_TO_IRQ(MX53_PIN_ATA_DATA5),
 	.hp_status = headphone_det_status,
 	.amp_enable = mxc_sgtl5000_amp_enable,
 	.init = mxc_sgtl5000_init,
@@ -1251,19 +740,23 @@ static struct mxc_mlb_platform_data mlb_data = {
 #ifdef CONFIG_MTD_PARTITIONS
 static struct mtd_partition nand_flash_partitions[] = {
 	{
-	 .name = "BOOT",
+	 .name = "bootloader",
 	 .offset = 0,
-	 .size = 7 * 1024 * 1024},
+	 .size = 3 * 1024 * 1024},
 	{
-	 .name = "MISC",
+	 .name = "nand.kernel",
 	 .offset = MTDPART_OFS_APPEND,
-	 .size = 1 * 1024 * 1024},
+	 .size = 5 * 1024 * 1024},
 	{
-	 .name = "RECOVERY",
+	 .name = "nand.rootfs",
 	 .offset = MTDPART_OFS_APPEND,
-	 .size = 20 * 1024 * 1024},
+	 .size = 256 * 1024 * 1024},
 	{
-	 .name = "ROOT",
+	 .name = "nand.userfs1",
+	 .offset = MTDPART_OFS_APPEND,
+	 .size = 256 * 1024 * 1024},
+	{
+	 .name = "nand.userfs2",
 	 .offset = MTDPART_OFS_APPEND,
 	 .size = MTDPART_SIZ_FULL},
 };
@@ -1324,6 +817,7 @@ static struct platform_device mxc_alsa_surround_device = {
 };
 
 static int __initdata mxc_apc_on = { 0 };	/* OFF: 0 (default), ON: 1 */
+
 static int __init apc_setup(char *__unused)
 {
 	mxc_apc_on = 1;
@@ -1332,48 +826,6 @@ static int __init apc_setup(char *__unused)
 }
 __setup("apc", apc_setup);
 
-static int __initdata enable_w1 = { 0 };
-static int __init w1_setup(char *__unused)
-{
-	enable_w1 = 1;
-	return cpu_is_mx53();
-}
-__setup("w1", w1_setup);
-
-
-static int __initdata enable_spdif = { 0 };
-static int __init spdif_setup(char *__unused)
-{
-	enable_spdif = 1;
-	return 1;
-}
-__setup("spdif", spdif_setup);
-
-static struct android_pmem_platform_data android_pmem_pdata = {
-	.name = "pmem_adsp",
-	.start = 0,
-	.size = SZ_64M,
-	.no_allocator = 0,
-	.cached = PMEM_NONCACHE_NORMAL,
-};
-
-static struct android_pmem_platform_data android_pmem_gpu_pdata = {
-	.name = "pmem_gpu",
-	.start = 0,
-	.size = SZ_32M,
-	.no_allocator = 0,
-	.cached = PMEM_CACHE_ENABLE,
-};
-
-static struct android_usb_platform_data android_usb_pdata = {
-	.vendor_id      = 0x0bb4,
-	.product_id     = 0x0c01,
-	.adb_product_id = 0x0c02,
-	.version        = 0x0100,
-	.product_name   = "Android Phone",
-	.manufacturer_name = "Freescale",
-	.nluns = 3,
-};
 
 /*!
  * Board specific fixup function. It is called by \b setup_arch() in
@@ -1396,38 +848,17 @@ static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags,
 	int gpu_mem = SZ_128M;
 	int fb_mem = SZ_32M;
 	char *str;
-	int size;
 
 	mxc_set_cpu_type(MXC_CPU_MX53);
 
 	get_cpu_wp = mx53_evk_get_cpu_wp;
 	set_num_cpu_wp = mx53_evk_set_num_cpu_wp;
 
-	for_each_tag(t, tags) {
-		if (t->hdr.tag != ATAG_MEM)
-			continue;
-		size = t->u.mem.size;
-
-		android_pmem_pdata.start =
-				PHYS_OFFSET + size - android_pmem_pdata.size;
-		android_pmem_gpu_pdata.start =
-				android_pmem_pdata.start - android_pmem_gpu_pdata.size;
-		gpu_device.resource[5].start =
-				android_pmem_gpu_pdata.start - SZ_16M;
-		gpu_device.resource[5].end = 
-				gpu_device.resource[5].start + SZ_16M - 1;
-		size -= android_pmem_pdata.size;
-		size -= android_pmem_gpu_pdata.size;
-		size -= SZ_16M;
-		t->u.mem.size = size;
-	}
-#if 0
 	for_each_tag(mem_tag, tags) {
 		if (mem_tag->hdr.tag == ATAG_MEM) {
 			total_mem = mem_tag->u.mem.size;
 			left_mem = total_mem - gpu_mem - fb_mem;
 			break;
-
 		}
 	}
 
@@ -1479,142 +910,9 @@ static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags,
 		}
 #endif
 	}
-#endif
-}
-
-static void __init mx53_evk_io_init(void)
-{
-	mxc_iomux_v3_setup_multiple_pads(mx53common_pads,
-					ARRAY_SIZE(mx53common_pads));
-
-	if (board_is_mx53_arm2()) {
-		/* MX53 ARM2 CPU board */
-		pr_info("MX53 ARM2 board \n");
-		mxc_iomux_v3_setup_multiple_pads(mx53arm2_pads,
-					ARRAY_SIZE(mx53arm2_pads));
-
-		/* Config GPIO for OTG VBus */
-		gpio_request(ARM2_OTG_VBUS, "otg-vbus");
-		gpio_direction_output(ARM2_OTG_VBUS, 1);
-
-		gpio_request(ARM2_SD1_CD, "sdhc1-cd");
-		gpio_direction_input(ARM2_SD1_CD);	/* SD1 CD */
-
-		gpio_request(ARM2_LCD_CONTRAST, "lcd-contrast");
-		gpio_direction_output(ARM2_LCD_CONTRAST, 1);
-	} else {
-		/* MX53 EVK board */
-		pr_info("MX53 EVK board \n");
-		mxc_iomux_v3_setup_multiple_pads(mx53evk_pads,
-					ARRAY_SIZE(mx53evk_pads));
-
-		/* Host1 Vbus with GPIO high */
-		gpio_request(EVK_USBH1_VBUS, "usbh1-vbus");
-		gpio_direction_output(EVK_USBH1_VBUS, 1);
-		/* shutdown the Host1 Vbus when system bring up,
-		* Vbus will be opened in Host1 driver's probe function */
-		gpio_set_value(EVK_USBH1_VBUS, 0);
-
-		/* USB HUB RESET - De-assert USB HUB RESET_N */
-		gpio_request(EVK_USB_HUB_RESET, "usb-hub-reset");
-		gpio_direction_output(EVK_USB_HUB_RESET, 0);
-		msleep(1);
-		gpio_set_value(EVK_USB_HUB_RESET, 1);
-
-		/* Config GPIO for OTG VBus */
-		gpio_request(EVK_OTG_VBUS, "otg-vbus");
-		gpio_direction_output(EVK_OTG_VBUS, 0);
-		if (board_is_mx53_evk_a()) /*rev A,"1" disable, "0" enable vbus*/
-			gpio_set_value(EVK_OTG_VBUS, 1);
-		else if (board_is_mx53_evk_b()) /* rev B,"0" disable,"1" enable Vbus*/
-			gpio_set_value(EVK_OTG_VBUS, 0);
-
-		gpio_request(EVK_SD1_CD, "sdhc1-cd");
-		gpio_direction_input(EVK_SD1_CD);	/* SD1 CD */
-		gpio_request(EVK_SD1_WP, "sdhc1-wp");
-		gpio_direction_input(EVK_SD1_WP);	/* SD1 WP */
-
-		/* SD3 CD */
-		gpio_request(EVK_SD3_CD, "sdhc3-cd");
-		gpio_direction_input(EVK_SD3_CD);
-
-		/* SD3 WP */
-		gpio_request(EVK_SD3_WP, "sdhc3-wp");
-		gpio_direction_input(EVK_SD3_WP);
-
-		/* reset FEC PHY */
-		gpio_request(EVK_FEC_PHY_RESET, "fec-phy-reset");
-		gpio_direction_output(EVK_FEC_PHY_RESET, 0);
-		msleep(1);
-		gpio_set_value(EVK_FEC_PHY_RESET, 1);
-
-		gpio_request(MX53_ESAI_RESET, "fesai-reset");
-		gpio_direction_output(MX53_ESAI_RESET, 0);
-	}
-
-	/* DVI Detect */
-	gpio_request(MX53_DVI_DETECT, "dvi-detect");
-	gpio_direction_input(MX53_DVI_DETECT);
-	/* DVI Reset - Assert for i2c disabled mode */
-	gpio_request(MX53_DVI_RESET, "dvi-reset");
-	gpio_set_value(MX53_DVI_RESET, 0);
-
-	/* DVI Power-down */
-	gpio_request(MX53_DVI_PD, "dvi-pd");
-	gpio_direction_output(MX53_DVI_PD, 1);
-
-	/* DVI I2C enable */
-	gpio_request(MX53_DVI_I2C, "dvi-i2c");
-	gpio_direction_output(MX53_DVI_I2C, 0);
-
-	mxc_iomux_v3_setup_multiple_pads(mx53_nand_pads,
-					ARRAY_SIZE(mx53_nand_pads));
-
-	gpio_request(MX53_PMIC_INT, "pmic-int");
-	gpio_direction_input(MX53_PMIC_INT);	/*PMIC_INT*/
-
-	/* headphone_det_b */
-	gpio_request(MX53_HP_DETECT, "hp-detect");
-	gpio_direction_input(MX53_HP_DETECT);
-
-	/* power key */
-
-	/* LCD related gpio */
-
-	/* Camera reset */
-	gpio_request(MX53_CAM_RESET, "cam-reset");
-	gpio_direction_output(MX53_CAM_RESET, 1);
-
-	/* TVIN reset */
-	gpio_request(MX53_TVIN_RESET, "tvin-reset");
-	gpio_direction_output(MX53_TVIN_RESET, 0);
-	msleep(5);
-	gpio_set_value(MX53_TVIN_RESET, 1);
-
-	/* CAN1 enable GPIO*/
-	gpio_request(MX53_CAN1_EN1, "can1-en1");
-	gpio_direction_output(MX53_CAN1_EN1, 0);
-
-	gpio_request(MX53_CAN1_EN2, "can1-en2");
-	gpio_direction_output(MX53_CAN1_EN2, 0);
-
-	/* CAN2 enable GPIO*/
-	gpio_request(MX53_CAN2_EN1, "can2-en1");
-	gpio_direction_output(MX53_CAN2_EN1, 0);
-
-	gpio_request(MX53_CAN2_EN2, "can2-en2");
-	gpio_direction_output(MX53_CAN2_EN2, 0);
-
-	if (enable_spdif) {
-		struct pad_desc spdif_pin = MX53_PAD_GPIO_19__SPDIF_TX1;
-		mxc_iomux_v3_setup_pad(&spdif_pin);
-	} else {
-		/* GPIO for 12V */
-		gpio_request(MX53_12V_EN, "12v-en");
-		gpio_direction_output(MX53_12V_EN, 0);
-	}
 }
-
+extern void mx53_gpio_usbotg_driver_vbus(bool on);
+extern void mx53_gpio_host1_driver_vbus(bool on);
 /*!
  * Board specific initialization.
  */
@@ -1627,17 +925,17 @@ static void __init mxc_board_init(void)
 
 	/* SD card detect irqs */
 	if (board_is_mx53_arm2()) {
-		mxcsdhc1_device.resource[2].start = IOMUX_TO_IRQ_V3(ARM2_SD1_CD);
-		mxcsdhc1_device.resource[2].end = IOMUX_TO_IRQ_V3(ARM2_SD1_CD);
+		mxcsdhc1_device.resource[2].start = IOMUX_TO_IRQ(MX53_PIN_GPIO_1);
+		mxcsdhc1_device.resource[2].end = IOMUX_TO_IRQ(MX53_PIN_GPIO_1);
 		mmc3_data.card_inserted_state = 1;
 		mmc3_data.status = NULL;
 		mmc3_data.wp_status = NULL;
 		mmc1_data.wp_status = NULL;
 	} else {
-		mxcsdhc3_device.resource[2].start = IOMUX_TO_IRQ_V3(EVK_SD3_CD);
-		mxcsdhc3_device.resource[2].end = IOMUX_TO_IRQ_V3(EVK_SD3_CD);
-		mxcsdhc1_device.resource[2].start = IOMUX_TO_IRQ_V3(EVK_SD1_CD);
-		mxcsdhc1_device.resource[2].end = IOMUX_TO_IRQ_V3(EVK_SD1_CD);
+		mxcsdhc3_device.resource[2].start = IOMUX_TO_IRQ(MX53_PIN_EIM_DA11);
+		mxcsdhc3_device.resource[2].end = IOMUX_TO_IRQ(MX53_PIN_EIM_DA11);
+		mxcsdhc1_device.resource[2].start = IOMUX_TO_IRQ(MX53_PIN_EIM_DA13);
+		mxcsdhc1_device.resource[2].end = IOMUX_TO_IRQ(MX53_PIN_EIM_DA13);
 	}
 
 	mxc_cpu_common_init();
@@ -1695,10 +993,7 @@ static void __init mxc_board_init(void)
 				ARRAY_SIZE(mxc_i2c0_board_info));
 	i2c_register_board_info(1, mxc_i2c1_board_info,
 				ARRAY_SIZE(mxc_i2c1_board_info));
-	mxc_register_device(&mxc_android_pmem_device, &android_pmem_pdata);
-	mxc_register_device(&mxc_android_pmem_gpu_device, &android_pmem_gpu_pdata);
-	mxc_register_device(&android_usb_device, &android_usb_pdata);
-	mxc_register_device(&mxc_powerkey_device, NULL);
+
 	mx53_evk_init_mc13892();
 /*
 	pm_power_off = mxc_power_off;
@@ -1715,8 +1010,6 @@ static void __init mxc_board_init(void)
 		mxc_register_device(&mxc_alsa_surround_device,
 			&mxc_surround_audio_data);
 	}
-	mxc_register_device(&mxc_v4l2_device, NULL);
-	mxc_register_device(&mxc_v4l2out_device, NULL);
 }
 
 static void __init mx53_evk_timer_init(void)
diff --git a/arch/arm/mach-mx5/mx53_evk_gpio.c b/arch/arm/mach-mx5/mx53_evk_gpio.c
index 450280e2d96a..caeee73ea414 100644
--- a/arch/arm/mach-mx5/mx53_evk_gpio.c
+++ b/arch/arm/mach-mx5/mx53_evk_gpio.c
@@ -50,15 +50,21 @@ static struct mxc_iomux_pin_cfg __initdata mxc_iomux_pins[] = {
 	 },
 	{
 	 MX53_PIN_EIM_D16, IOMUX_CONFIG_ALT4,
+	 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH,
+	 MUX_IN_ECSPI1_IPP_CSPI_CLK_IN_SELECT_INPUT,
+	 INPUT_CTL_PATH3,
 	 },
 	{
 	 MX53_PIN_EIM_D17, IOMUX_CONFIG_ALT4,
+	 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH,
+	 MUX_IN_ECSPI1_IPP_IND_MISO_SELECT_INPUT,
+	 INPUT_CTL_PATH3,
 	 },
 	{
-	 MX53_PIN_EIM_D18, IOMUX_CONFIG_ALT2,
-	 },
-	{
-	 MX53_PIN_EIM_D19, IOMUX_CONFIG_ALT2,
+	 MX53_PIN_EIM_D18, IOMUX_CONFIG_ALT4,
+	 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH,
+	 MUX_IN_ECSPI1_IPP_IND_MOSI_SELECT_INPUT,
+	 INPUT_CTL_PATH3,
 	 },
 	{
 	 MX53_PIN_EIM_D20, IOMUX_CONFIG_ALT3,
@@ -73,9 +79,6 @@ static struct mxc_iomux_pin_cfg __initdata mxc_iomux_pins[] = {
 	 MX53_PIN_EIM_D26, IOMUX_CONFIG_GPIO,
 	 },
 	{
-	 MX53_PIN_EIM_D28, IOMUX_CONFIG_ALT3,
-	 },
-	{
 	 MX53_PIN_EIM_D29, IOMUX_CONFIG_ALT3,
 	 },
 	{
@@ -85,12 +88,6 @@ static struct mxc_iomux_pin_cfg __initdata mxc_iomux_pins[] = {
 	 MX53_PIN_EIM_D31, IOMUX_CONFIG_ALT4,
 	 },
 	{
-	 MX53_PIN_NANDF_CS2, IOMUX_CONFIG_ALT3,
-	 },
-	{
-	 MX53_PIN_NANDF_CS3, IOMUX_CONFIG_ALT3,
-	 },
-	{
 	 MX53_PIN_ATA_BUFFER_EN, IOMUX_CONFIG_ALT3,
 	 (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
 	  PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST),
@@ -166,31 +163,7 @@ static struct mxc_iomux_pin_cfg __initdata mxc_iomux_pins[] = {
 	 MX53_PIN_KEY_ROW1, IOMUX_CONFIG_ALT2,
 	 },
 	{
-	 MX53_PIN_KEY_COL2, IOMUX_CONFIG_ALT2,
-	 },
-	{
-	 MX53_PIN_KEY_ROW2, IOMUX_CONFIG_ALT2,
-	 },
-	{
-	 MX53_PIN_KEY_COL3, IOMUX_CONFIG_ALT4,
-	 },
-	{
-	 MX53_PIN_KEY_COL4, IOMUX_CONFIG_ALT2,
-	 },
-	{
-	 MX53_PIN_KEY_ROW4, IOMUX_CONFIG_ALT2,
-	 },
-	{
-	 MX53_PIN_CSI0_D4, IOMUX_CONFIG_ALT5,
-	 },
-	{
-	 MX53_PIN_CSI0_D6, IOMUX_CONFIG_ALT5,
-	 },
-	{
-	 MX53_PIN_CSI0_D7, IOMUX_CONFIG_ALT5,
-	 },
-	{
-	 MX53_PIN_CSI0_D9, IOMUX_CONFIG_ALT5,
+	 MX53_PIN_CSI0_D7, IOMUX_CONFIG_ALT1,
 	 },
 	{ /* UART1 Tx */
 	 MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT2,
@@ -205,19 +178,31 @@ static struct mxc_iomux_pin_cfg __initdata mxc_iomux_pins[] = {
 	 INPUT_CTL_PATH1,
 	},
 	{
-	 MX53_PIN_GPIO_2, IOMUX_CONFIG_GPIO,
+	 MX53_PIN_GPIO_2, IOMUX_CONFIG_ALT7,
+	 (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
+	 PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE |
+	 PAD_CTL_360K_PD),
+	 MUX_IN_MLB_MLBDAT_IN_SELECT_INPUT,
+	 INPUT_CTL_PATH2,
 	 },
 	{
-	 MX53_PIN_GPIO_3, IOMUX_CONFIG_GPIO,
+	 MX53_PIN_GPIO_3, IOMUX_CONFIG_ALT7,
+	 (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
+	 PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE |
+	 PAD_CTL_360K_PD),
+	 MUX_IN_MLB_MLBCLK_IN_SELECT_INPUT,
+	 INPUT_CTL_PATH2,
 	 },
 	{
 	 MX53_PIN_GPIO_4, IOMUX_CONFIG_GPIO,
 	 },
 	{
-	 MX53_PIN_GPIO_5, IOMUX_CONFIG_GPIO,
-	 },
-	{
-	 MX53_PIN_GPIO_6, IOMUX_CONFIG_GPIO,
+	 MX53_PIN_GPIO_6, IOMUX_CONFIG_ALT7,
+	 (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
+	 PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE |
+	 PAD_CTL_360K_PD),
+	 MUX_IN_MLB_MLBSIG_IN_SELECT_INPUT,
+	 INPUT_CTL_PATH2,
 	 },
 	{
 	 MX53_PIN_GPIO_7, IOMUX_CONFIG_GPIO,
@@ -228,29 +213,79 @@ static struct mxc_iomux_pin_cfg __initdata mxc_iomux_pins[] = {
 	{
 	 MX53_PIN_GPIO_10, IOMUX_CONFIG_GPIO,
 	 },
-	{
-	 MX53_PIN_GPIO_11, IOMUX_CONFIG_GPIO,
+	{ /* CAN1-TX */
+	 MX53_PIN_KEY_COL2, IOMUX_CONFIG_ALT2,
+	 (PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
+	  PAD_CTL_PUE_PULL | PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE),
 	 },
-	{
-	 MX53_PIN_GPIO_12, IOMUX_CONFIG_GPIO,
+	{ /* CAN1-RX */
+	 MX53_PIN_KEY_ROW2, IOMUX_CONFIG_ALT2,
+	 (PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
+	  PAD_CTL_PUE_PULL | PAD_CTL_360K_PD | PAD_CTL_ODE_OPENDRAIN_NONE),
+	 MUX_IN_CAN1_IPP_IND_CANRX_SELECT_INPUT,
+	 INPUT_CTL_PATH0,
+	 },
+	{ /* CAN1 -- EN */
+	 MX53_PIN_GPIO_18, IOMUX_CONFIG_ALT1,
+	 (PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
+	  PAD_CTL_PUE_PULL | PAD_CTL_360K_PD | PAD_CTL_ODE_OPENDRAIN_NONE),
+	 },
+	{ /* CAN1 -- STBY */
+	 MX53_PIN_GPIO_17, IOMUX_CONFIG_ALT1,
+	 (PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
+	  PAD_CTL_PUE_PULL | PAD_CTL_360K_PD | PAD_CTL_ODE_OPENDRAIN_NONE),
+	 },
+	{ /* CAN1 -- NERR */
+	 MX53_PIN_GPIO_5, IOMUX_CONFIG_ALT1,
+	 (PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
+	  PAD_CTL_PUE_PULL | PAD_CTL_360K_PD | PAD_CTL_ODE_OPENDRAIN_NONE),
+	 MUX_IN_CAN2_IPP_IND_CANRX_SELECT_INPUT,
+	 INPUT_CTL_PATH1,
 	 },
-	{
-	 MX53_PIN_GPIO_13, IOMUX_CONFIG_GPIO,
+	{ /* CAN2-TX */
+	 MX53_PIN_KEY_COL4, IOMUX_CONFIG_ALT2,
+	 (PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
+	  PAD_CTL_PUE_PULL | PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE),
 	 },
-	{
-	 MX53_PIN_GPIO_14, IOMUX_CONFIG_GPIO,
+	{ /* CAN2-RX */
+	 MX53_PIN_KEY_ROW4, IOMUX_CONFIG_ALT2,
+	 (PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
+	  PAD_CTL_PUE_PULL | PAD_CTL_360K_PD | PAD_CTL_ODE_OPENDRAIN_NONE),
+	 MUX_IN_CAN2_IPP_IND_CANRX_SELECT_INPUT,
+	 INPUT_CTL_PATH0,
+	 },
+	{ /* CAN2 -- EN */
+	 MX53_PIN_CSI0_D6, IOMUX_CONFIG_ALT1,
+	 (PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
+	  PAD_CTL_PUE_PULL | PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE),
+	 },
+	{ /* CAN2 -- STBY */
+	 MX53_PIN_GPIO_14, IOMUX_CONFIG_ALT0,
+	 (PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
+	  PAD_CTL_PUE_PULL | PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE),
+	 },
+	{ /* CAN2 -- NERR */
+	 MX53_PIN_CSI0_D4, IOMUX_CONFIG_ALT1,
+	 (PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
+	  PAD_CTL_PUE_PULL | PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE),
 	 },
 	{
-	 MX53_PIN_GPIO_16, IOMUX_CONFIG_ALT1,
+	 MX53_PIN_GPIO_11, IOMUX_CONFIG_GPIO,
+	 },
+	{ /* ESAI reset */
+	 MX53_PIN_GPIO_12, IOMUX_CONFIG_ALT0,
+	(PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
+	  PAD_CTL_PUE_PULL | PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE |
+	  PAD_CTL_SRE_FAST),
 	 },
 	{
-	 MX53_PIN_GPIO_17, IOMUX_CONFIG_GPIO,
+	 MX53_PIN_GPIO_13, IOMUX_CONFIG_GPIO,
 	 },
 	{
-	 MX53_PIN_GPIO_18, IOMUX_CONFIG_GPIO,
+	 MX53_PIN_GPIO_16, IOMUX_CONFIG_ALT1,
 	 },
 	{
-	 MX53_PIN_GPIO_19, IOMUX_CONFIG_ALT3,
+	 MX53_PIN_GPIO_19, IOMUX_CONFIG_ALT1,
 	 },
 	{	/* DI0 display clock */
 	 MX53_PIN_DI0_DISP_CLK, IOMUX_CONFIG_ALT0,
@@ -392,6 +427,36 @@ static struct mxc_iomux_pin_cfg __initdata mxc_iomux_pins[] = {
 	 (PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE |
 	  PAD_CTL_DRV_HIGH | PAD_CTL_SRE_SLOW),
 	 },
+	{
+	 MX53_PIN_LVDS0_TX3_P, IOMUX_CONFIG_ALT1,
+	 },
+	{
+	 MX53_PIN_LVDS0_CLK_P, IOMUX_CONFIG_ALT1,
+	 },
+	{
+	 MX53_PIN_LVDS0_TX2_P, IOMUX_CONFIG_ALT1,
+	 },
+	{
+	 MX53_PIN_LVDS0_TX1_P, IOMUX_CONFIG_ALT1,
+	 },
+	{
+	 MX53_PIN_LVDS0_TX0_P, IOMUX_CONFIG_ALT1,
+	 },
+	{
+	 MX53_PIN_LVDS1_TX3_P, IOMUX_CONFIG_ALT1,
+	 },
+	{
+	 MX53_PIN_LVDS1_CLK_P, IOMUX_CONFIG_ALT1,
+	 },
+	{
+	 MX53_PIN_LVDS1_TX2_P, IOMUX_CONFIG_ALT1,
+	 },
+	{
+	 MX53_PIN_LVDS1_TX1_P, IOMUX_CONFIG_ALT1,
+	 },
+	{
+	 MX53_PIN_LVDS1_TX0_P, IOMUX_CONFIG_ALT1,
+	 },
 	{ /* audio and CSI clock out */
 	 MX53_PIN_GPIO_0, IOMUX_CONFIG_ALT3,
 	 },
@@ -450,68 +515,100 @@ static struct mxc_iomux_pin_cfg __initdata mxc_iomux_pins[] = {
 	/* esdhc1 */
 	{
 	 MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION,
-	 (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST),
+	 (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH
+	  | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE
+	  | PAD_CTL_SRE_FAST),
 	 },
 	{
 	 MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION,
-	 (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST),
+	 (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | PAD_CTL_HYS_ENABLE
+	  | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE
+	  | PAD_CTL_SRE_FAST),
 	 },
 	{
 	 MX53_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0,
-	(PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST),
+	 (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH
+	  | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE
+	  | PAD_CTL_SRE_FAST),
 	 },
 	 {
 	 MX53_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST),
+	 (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH
+	  | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE
+	  | PAD_CTL_SRE_FAST),
 	 },
 	 {
 	 MX53_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST),
+	 (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH
+	  | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE
+	  | PAD_CTL_SRE_FAST),
 	 },
 	 {
 	 MX53_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST),
+	 (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH
+	  | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE
+	  | PAD_CTL_SRE_FAST),
 	 },
 	/* esdhc3 */
 	{
 	 MX53_PIN_ATA_DATA0, IOMUX_CONFIG_ALT4,
-	 (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST),
+	 (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH
+	  | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE
+	  | PAD_CTL_SRE_FAST),
 	 },
 	{
 	 MX53_PIN_ATA_DATA1, IOMUX_CONFIG_ALT4,
-	 (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST),
+	 (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH
+	  | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE
+	  | PAD_CTL_SRE_FAST),
 	 },
 	{
 	 MX53_PIN_ATA_DATA2, IOMUX_CONFIG_ALT4,
-	 (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST),
+	 (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH
+	  | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE
+	  | PAD_CTL_SRE_FAST),
 	 },
 	{
 	 MX53_PIN_ATA_DATA3, IOMUX_CONFIG_ALT4,
-	 (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST),
+	 (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH
+	  | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE
+	  | PAD_CTL_SRE_FAST),
 	 },
 	{
 	 MX53_PIN_ATA_DATA8, IOMUX_CONFIG_ALT4,
-	 (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST),
+	 (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH
+	  | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE
+	  | PAD_CTL_SRE_FAST),
 	 },
 	{
 	 MX53_PIN_ATA_DATA9, IOMUX_CONFIG_ALT4,
-	 (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST),
+	 (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH
+	  | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE
+	  | PAD_CTL_SRE_FAST),
 	 },
 	{
 	 MX53_PIN_ATA_DATA10, IOMUX_CONFIG_ALT4,
-	 (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST),
+	 (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH
+	  | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE
+	  | PAD_CTL_SRE_FAST),
 	 },
 	{
 	 MX53_PIN_ATA_DATA11, IOMUX_CONFIG_ALT4,
-	 (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST),
+	 (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH
+	  | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE
+	  | PAD_CTL_SRE_FAST),
 	 },
 	{
 	 MX53_PIN_ATA_IORDY, IOMUX_CONFIG_ALT2,
-	 (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST),
+	 (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | PAD_CTL_HYS_ENABLE
+	  | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE
+	  | PAD_CTL_SRE_FAST),
 	 },
 	{
 	 MX53_PIN_ATA_RESET_B, IOMUX_CONFIG_ALT2,
-	 (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST),
+	 (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH
+	  | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE
+	  | PAD_CTL_SRE_FAST),
 	 },
 	{ /* FEC pins */
 	 MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0,
@@ -556,6 +653,38 @@ static struct mxc_iomux_pin_cfg __initdata mxc_iomux_pins[] = {
 	 MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0,
 	 PAD_CTL_DRV_HIGH,
 	 },
+	 { /* I2C1 SDA */
+	 MX53_PIN_CSI0_D8, IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION,
+	 (PAD_CTL_SRE_FAST | PAD_CTL_ODE_OPENDRAIN_ENABLE |
+	 PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
+	 PAD_CTL_HYS_ENABLE),
+	 MUX_IN_I2C1_IPP_SDA_IN_SELECT_INPUT,
+	 INPUT_CTL_PATH0,
+	 },
+	 { /* I2C1 SCL */
+	 MX53_PIN_CSI0_D9, IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION,
+	 (PAD_CTL_SRE_FAST | PAD_CTL_ODE_OPENDRAIN_ENABLE |
+	 PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
+	 PAD_CTL_HYS_ENABLE),
+	 MUX_IN_I2C1_IPP_SCL_IN_SELECT_INPUT,
+	 INPUT_CTL_PATH0,
+	 },
+	 { /* I2C2 SDA */
+	 MX53_PIN_KEY_ROW3, IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION,
+	 (PAD_CTL_SRE_FAST | PAD_CTL_ODE_OPENDRAIN_ENABLE |
+	 PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
+	 PAD_CTL_HYS_ENABLE),
+	 MUX_IN_I2C2_IPP_SDA_IN_SELECT_INPUT,
+	 INPUT_CTL_PATH0,
+	 },
+	 { /* I2C1 SCL */
+	 MX53_PIN_KEY_COL3, IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION,
+	 (PAD_CTL_SRE_FAST | PAD_CTL_ODE_OPENDRAIN_ENABLE |
+	 PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
+	 PAD_CTL_HYS_ENABLE),
+	 MUX_IN_I2C2_IPP_SCL_IN_SELECT_INPUT,
+	 INPUT_CTL_PATH0,
+	 },
 };
 
 static struct mxc_iomux_pin_cfg __initdata mx53_evk_iomux_pins[] = {
@@ -631,11 +760,87 @@ static int __initdata enable_w1 = { 0 };
 static int __init w1_setup(char *__unused)
 {
 	enable_w1 = 1;
-	return 1;
+	return cpu_is_mx53();
 }
 
 __setup("w1", w1_setup);
 
+static struct mxc_iomux_pin_cfg __initdata nand_iomux_pins[] = {
+	{
+	 MX53_PIN_NANDF_CS0, IOMUX_CONFIG_ALT0, PAD_CTL_DRV_HIGH,
+	},
+	{
+	 MX53_PIN_NANDF_CS1, IOMUX_CONFIG_ALT0, PAD_CTL_DRV_HIGH,
+	},
+	{
+	 MX53_PIN_NANDF_CS2, IOMUX_CONFIG_ALT0, PAD_CTL_DRV_HIGH,
+	},
+	{
+	 MX53_PIN_NANDF_CS3, IOMUX_CONFIG_ALT0, PAD_CTL_DRV_HIGH,
+	},
+	{
+	 MX53_PIN_NANDF_RB0, IOMUX_CONFIG_ALT0,
+	 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | PAD_CTL_100K_PU,
+	},
+	{
+	 MX53_PIN_NANDF_CLE, IOMUX_CONFIG_ALT0, PAD_CTL_DRV_HIGH,
+	},
+	{
+	 MX53_PIN_NANDF_ALE, IOMUX_CONFIG_ALT0, PAD_CTL_DRV_HIGH,
+	},
+	{
+	 MX53_PIN_NANDF_WP_B, IOMUX_CONFIG_ALT0,
+	 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | PAD_CTL_100K_PU,
+	},
+	{
+	 MX53_PIN_NANDF_RE_B, IOMUX_CONFIG_ALT0, PAD_CTL_DRV_HIGH,
+	},
+	{
+	 MX53_PIN_NANDF_WE_B, IOMUX_CONFIG_ALT0, PAD_CTL_DRV_HIGH,
+	},
+	{
+	 MX53_PIN_EIM_DA0, IOMUX_CONFIG_ALT0,
+	 PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH,
+	},
+	{
+	 MX53_PIN_EIM_DA1, IOMUX_CONFIG_ALT0,
+	 PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH,
+	},
+	{
+	 MX53_PIN_EIM_DA2, IOMUX_CONFIG_ALT0,
+	 PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH,
+	},
+	{
+	 MX53_PIN_EIM_DA3, IOMUX_CONFIG_ALT0,
+	 PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH,
+	},
+	{
+	 MX53_PIN_EIM_DA4, IOMUX_CONFIG_ALT0,
+	 PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH,
+	},
+	{
+	 MX53_PIN_EIM_DA5, IOMUX_CONFIG_ALT0,
+	 PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH,
+	},
+	{
+	 MX53_PIN_EIM_DA6, IOMUX_CONFIG_ALT0,
+	 PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH,
+	},
+	{
+	 MX53_PIN_EIM_DA7, IOMUX_CONFIG_ALT0,
+	 PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH,
+	},
+};
+
+static int __initdata enable_spdif = { 0 };
+static int __init spdif_setup(char *__unused)
+{
+	enable_spdif = 1;
+	return 1;
+}
+
+__setup("spdif", spdif_setup);
+
 void __init mx53_evk_io_init(void)
 {
 	int i;
@@ -665,12 +870,12 @@ void __init mx53_evk_io_init(void)
 						    mx53_arm2_iomux_pins[i].in_mode);
 		}
 
-		/* Enable OTG VBus with GPIO low */
+		/* Config GPIO for OTG VBus */
 		mxc_iomux_set_pad(MX53_PIN_EIM_D22, PAD_CTL_DRV_HIGH |
 				PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
 		gpio_request(IOMUX_TO_GPIO(MX53_PIN_EIM_D22), "gpio3_22");
 		gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_EIM_D22), 0);
-		gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_EIM_D22), 0);
+		gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_EIM_D22), 1);
 
 		gpio_request(IOMUX_TO_GPIO(MX53_PIN_GPIO_1), "gpio1_1");
 		gpio_direction_input(IOMUX_TO_GPIO(MX53_PIN_GPIO_1));	/* SD1 CD */
@@ -696,6 +901,9 @@ void __init mx53_evk_io_init(void)
 				PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
 		gpio_request(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_2), "gpio7_8");
 		gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_2), 1);
+		/* shutdown the Host1 Vbus when system bring up,
+		 * Vbus will be opened in Host1 driver's probe function */
+		gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_2), 0);
 
 		/* USB HUB RESET - De-assert USB HUB RESET_N */
 		mxc_iomux_set_pad(MX53_PIN_CSI0_DATA_EN, PAD_CTL_DRV_HIGH |
@@ -708,12 +916,16 @@ void __init mx53_evk_io_init(void)
 		msleep(1);
 		gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_CSI0_DATA_EN), 1);
 
-		/* Enable OTG VBus with GPIO low */
+		/* Config GPIO for OTG VBus */
 		mxc_iomux_set_pad(MX53_PIN_EIM_A23, PAD_CTL_DRV_HIGH |
 				PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
 		gpio_request(IOMUX_TO_GPIO(MX53_PIN_EIM_A23), "gpio6_6");
 		gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_EIM_A23), 0);
-		gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_EIM_A23), 0);
+
+		if (board_is_mx53_evk_a()) /*rev A,"1" disable, "0" enable vbus*/
+			gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_EIM_A23), 1);
+		else if (board_is_mx53_evk_b()) /* rev B,"0" disable,"1" enable Vbus*/
+			gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_EIM_A23), 0);
 
 		gpio_request(IOMUX_TO_GPIO(MX53_PIN_EIM_DA13), "gpio3_13");
 		gpio_direction_input(IOMUX_TO_GPIO(MX53_PIN_EIM_DA13));	/* SD1 CD */
@@ -735,70 +947,42 @@ void __init mx53_evk_io_init(void)
 		msleep(1);
 		gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_0), 1);
 
-		/* DVI Detect */
-		gpio_request(IOMUX_TO_GPIO(MX53_PIN_EIM_D31), "gpio3_31");
-		gpio_direction_input(IOMUX_TO_GPIO(MX53_PIN_EIM_D31));
-		/* DVI Reset - Assert for i2c disabled mode */
-		gpio_request(IOMUX_TO_GPIO(MX53_PIN_EIM_WAIT), "gpio5_0");
-		gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_EIM_WAIT), 0);
-		gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_EIM_WAIT), 0);
-		/* DVI Power-down */
-		gpio_request(IOMUX_TO_GPIO(MX53_PIN_EIM_D24), "gpio3_24");
-		gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_EIM_D24), 0);
-		gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_EIM_D24), 1);
-		/* DVI I2C enable */
-		gpio_request(IOMUX_TO_GPIO(MX53_PIN_EIM_D28), "gpio3_28");
-		gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_EIM_D28), 0);
-		gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_EIM_D28), 0);
+		/* CS42888 reset GPIO */
+		gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_GPIO_12), 0);
+		gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_12), 0);
+
 	}
 
+	/* DVI Detect */
+	gpio_request(IOMUX_TO_GPIO(MX53_PIN_EIM_D31), "gpio3_31");
+	gpio_direction_input(IOMUX_TO_GPIO(MX53_PIN_EIM_D31));
+	/* DVI Reset - Assert for i2c disabled mode */
+	gpio_request(IOMUX_TO_GPIO(MX53_PIN_EIM_WAIT), "gpio5_0");
+	gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_EIM_WAIT), 0);
+	gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_EIM_WAIT), 0);
+	/* DVI Power-down */
+	gpio_request(IOMUX_TO_GPIO(MX53_PIN_EIM_D24), "gpio3_24");
+	gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_EIM_D24), 0);
+	gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_EIM_D24), 1);
+	/* DVI I2C enable */
+	gpio_request(IOMUX_TO_GPIO(MX53_PIN_EIM_D28), "gpio3_28");
+	gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_EIM_D28), 0);
+	gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_EIM_D28), 0);
+
+	for (i = 0; i <  ARRAY_SIZE(nand_iomux_pins); i++) {
+		mxc_request_iomux(nand_iomux_pins[i].pin,
+					nand_iomux_pins[i].mux_mode);
+		if (nand_iomux_pins[i].pad_cfg)
+			mxc_iomux_set_pad(nand_iomux_pins[i].pin,
+					nand_iomux_pins[i].pad_cfg);
+		if (nand_iomux_pins[i].in_select)
+			mxc_iomux_set_input(nand_iomux_pins[i].in_select,
+					nand_iomux_pins[i].in_mode);
+	}
 
 	gpio_request(IOMUX_TO_GPIO(MX53_PIN_GPIO_16), "gpio7_11");
 	gpio_direction_input(IOMUX_TO_GPIO(MX53_PIN_GPIO_16));	/*PMIC_INT*/
 
-
-	/* i2c1 SDA */
-	mxc_request_iomux(MX53_PIN_CSI0_D8,
-			  IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
-	mxc_iomux_set_input(MUX_IN_I2C1_IPP_SDA_IN_SELECT_INPUT,
-			    INPUT_CTL_PATH0);
-	mxc_iomux_set_pad(MX53_PIN_CSI0_D8, PAD_CTL_SRE_FAST |
-			  PAD_CTL_ODE_OPENDRAIN_ENABLE |
-			  PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
-			  PAD_CTL_HYS_ENABLE);
-
-	/* i2c1 SCL */
-	mxc_request_iomux(MX53_PIN_CSI0_D9,
-			  IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
-	mxc_iomux_set_input(MUX_IN_I2C1_IPP_SCL_IN_SELECT_INPUT,
-			    INPUT_CTL_PATH0);
-	mxc_iomux_set_pad(MX53_PIN_CSI0_D9, PAD_CTL_SRE_FAST |
-			  PAD_CTL_ODE_OPENDRAIN_ENABLE |
-			  PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
-			  PAD_CTL_HYS_ENABLE);
-
-	/* i2c2 SDA */
-	mxc_request_iomux(MX53_PIN_KEY_ROW3,
-			  IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION);
-	mxc_iomux_set_input(MUX_IN_I2C2_IPP_SDA_IN_SELECT_INPUT,
-			    INPUT_CTL_PATH0);
-	mxc_iomux_set_pad(MX53_PIN_KEY_ROW3,
-			  PAD_CTL_SRE_FAST |
-			  PAD_CTL_ODE_OPENDRAIN_ENABLE |
-			  PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
-			  PAD_CTL_HYS_ENABLE);
-
-	/* i2c2 SCL */
-	mxc_request_iomux(MX53_PIN_KEY_COL3,
-			  IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION);
-	mxc_iomux_set_input(MUX_IN_I2C2_IPP_SCL_IN_SELECT_INPUT,
-			    INPUT_CTL_PATH0);
-	mxc_iomux_set_pad(MX53_PIN_KEY_COL3,
-			  PAD_CTL_SRE_FAST |
-			  PAD_CTL_ODE_OPENDRAIN_ENABLE |
-			  PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
-			  PAD_CTL_HYS_ENABLE);
-
 	/* headphone_det_b */
 	mxc_request_iomux(MX53_PIN_ATA_DATA5, IOMUX_CONFIG_GPIO);
 	mxc_iomux_set_pad(MX53_PIN_ATA_DATA5, PAD_CTL_100K_PU);
@@ -814,36 +998,82 @@ void __init mx53_evk_io_init(void)
 	gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_GPIO_10), 0);
 	gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_10), 1);
 
-	/* Camera low power */
-	gpio_request(IOMUX_TO_GPIO(MX53_PIN_CSI0_D5), "gpio5_23");
-	gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_CSI0_D5), 0);
-	gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_CSI0_D5), 0);
+	/* TVIN reset */
+	gpio_request(IOMUX_TO_GPIO(MX53_PIN_CSI0_D7), "gpio5_25");
+	gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_CSI0_D7), 0);
+	gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_CSI0_D7), 0);
+	msleep(5);
+	gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_CSI0_D7), 1);
+
+	/* CAN1 enable GPIO*/
+	gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_GPIO_18), 0);
+	gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_18), 0);
+	gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_GPIO_17), 0);
+	gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_17), 0);
+
+	/* CAN2 enable GPIO*/
+	gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_CSI0_D6), 0);
+	gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_CSI0_D6), 0);
+	gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_GPIO_14), 0);
+	gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_14), 0);
+
+	if (enable_spdif) {
+		mxc_free_iomux(MX53_PIN_GPIO_19, IOMUX_CONFIG_ALT1);
+		mxc_request_iomux(MX53_PIN_GPIO_19, IOMUX_CONFIG_ALT3);
+		mxc_iomux_set_pad(MX53_PIN_GPIO_19,
+			PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE |
+			PAD_CTL_PUE_PULL | PAD_CTL_100K_PU |
+			PAD_CTL_PKE_ENABLE);
+	} else {
+		/* GPIO for CAN 12V */
+		gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_GPIO_19), 0);
+		gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_19), 0);
+	}
 }
 
 /* workaround for ecspi chipselect pin may not keep correct level when idle */
 void mx53_evk_gpio_spi_chipselect_active(int cspi_mode, int status,
 					     int chipselect)
 {
-	u32 gpio;
-
 	switch (cspi_mode) {
 	case 1:
 		switch (chipselect) {
 		case 0x1:
-			mxc_request_iomux(MX53_PIN_EIM_D19,
-					  IOMUX_CONFIG_ALT4);
+			/* de-select SS1 of instance: ecspi1. */
+			mxc_request_iomux(MX53_PIN_EIM_D19, IOMUX_CONFIG_ALT1);
 			mxc_iomux_set_pad(MX53_PIN_EIM_D19,
 					  PAD_CTL_HYS_ENABLE |
 					  PAD_CTL_PKE_ENABLE |
-					  PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+					  PAD_CTL_PUE_PULL |
+					  PAD_CTL_100K_PU |
+					  PAD_CTL_DRV_HIGH);
+
+			/* mux mode: ALT4 mux port: SS0 of instance: ecspi1. */
+			mxc_request_iomux(MX53_PIN_EIM_EB2, IOMUX_CONFIG_ALT4);
+			mxc_iomux_set_pad(MX53_PIN_EIM_EB2,
+					  PAD_CTL_HYS_ENABLE |
+					  PAD_CTL_DRV_HIGH);
+			mxc_iomux_set_input(
+				MUX_IN_ECSPI1_IPP_IND_SS_B_1_SELECT_INPUT,
+					  INPUT_CTL_PATH3);
 			break;
 		case 0x2:
-			gpio = IOMUX_TO_GPIO(MX53_PIN_EIM_D19);
-			mxc_request_iomux(MX53_PIN_EIM_D19,
-					  IOMUX_CONFIG_GPIO);
-			gpio_request(gpio, "cspi1_ss1");
-			gpio_direction_output(gpio, 0);
-			gpio_set_value(gpio, 1 & (~status));
+			/* de-select SS0 of instance: ecspi1. */
+			mxc_request_iomux(MX53_PIN_EIM_EB2, IOMUX_CONFIG_ALT1);
+			mxc_iomux_set_pad(MX53_PIN_EIM_EB2,
+					  PAD_CTL_HYS_ENABLE |
+					  PAD_CTL_PKE_ENABLE |
+					  PAD_CTL_PUE_PULL |
+					  PAD_CTL_100K_PU |
+					  PAD_CTL_DRV_HIGH);
+			mxc_request_iomux(MX53_PIN_EIM_D19, IOMUX_CONFIG_ALT4);
+			mxc_iomux_set_pad(MX53_PIN_EIM_D19,
+					  PAD_CTL_HYS_ENABLE |
+					  PAD_CTL_DRV_HIGH);
+			mxc_iomux_set_input(
+				MUX_IN_ECSPI1_IPP_IND_SS_B_1_SELECT_INPUT,
+					  INPUT_CTL_PATH3);
+
 			break;
 		default:
 			break;
@@ -870,9 +1100,14 @@ void mx53_evk_gpio_spi_chipselect_inactive(int cspi_mode, int status,
 			mxc_request_iomux(MX53_PIN_EIM_D19,
 					  IOMUX_CONFIG_GPIO);
 			mxc_free_iomux(MX53_PIN_EIM_D19, IOMUX_CONFIG_GPIO);
+			mxc_free_iomux(MX53_PIN_EIM_EB2, IOMUX_CONFIG_ALT4);
 			break;
 		case 0x2:
-			mxc_free_iomux(MX53_PIN_EIM_D19, IOMUX_CONFIG_GPIO);
+			mxc_free_iomux(MX53_PIN_EIM_EB2, IOMUX_CONFIG_ALT4);
+			mxc_request_iomux(MX53_PIN_EIM_EB2,
+					  IOMUX_CONFIG_GPIO);
+			mxc_free_iomux(MX53_PIN_EIM_EB2, IOMUX_CONFIG_GPIO);
+			mxc_free_iomux(MX53_PIN_EIM_D19, IOMUX_CONFIG_ALT4);
 			break;
 		default:
 			break;
@@ -888,8 +1123,201 @@ void mx53_evk_gpio_spi_chipselect_inactive(int cspi_mode, int status,
 }
 EXPORT_SYMBOL(mx53_evk_gpio_spi_chipselect_inactive);
 
+void flexcan_xcvr_enable(int id, int en)
+{
+	static int pwdn;
+	if (id < 0 || id > 1)
+		return;
+
+	if (en) {
+		if (!(pwdn++))
+			gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_19), 1);
+
+		if (id == 0) {
+			gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_18), 1);
+			gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_17), 1);
+		} else {
+			gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_CSI0_D6), 1);
+			gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_14), 1);
+		}
+
+	} else {
+		if (!(--pwdn))
+			gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_19), 0);
+
+		if (id == 0) {
+			gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_18), 0);
+			gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_17), 0);
+		} else {
+			gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_CSI0_D6), 0);
+			gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_14), 0);
+		}
+	}
+}
+EXPORT_SYMBOL(flexcan_xcvr_enable);
+
 void gpio_lcd_active(void)
 {
 /* TO DO */
 }
 EXPORT_SYMBOL(gpio_lcd_active);
+
+void gpio_activate_esai_ports(void)
+{
+	unsigned int pad_val;
+
+	/* ESAI1-HCKR */
+	mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT2);
+	/* ESAI1-SCKR */
+	mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT2);
+	/* ESAI1-FSR */
+	mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT2);
+	/* ESAI1-HCKT */
+	mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT2);
+	/* ESAI1-SCKT */
+	mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT2);
+	/* ESAI1-FST */
+	mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT2);
+	/* ESAI1-TX5-RX0 */
+	mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT2);
+	/* ESAI1-TX4-RX1 */
+	mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT2);
+	/* ESAI1-TX3-RX2 */
+	mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT2);
+	/* ESAI1-TX2-RX3 */
+	mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT2);
+	/* ESAI1-TX1 */
+	mxc_request_iomux(MX53_PIN_NANDF_CS3, IOMUX_CONFIG_ALT3);
+	/* ESAI1-TX0 */
+	mxc_request_iomux(MX53_PIN_NANDF_CS2, IOMUX_CONFIG_ALT3);
+
+	pad_val = PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE |
+		    PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
+		    PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE;
+
+	/* ESAI1-HCKR */
+	mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER, pad_val);
+	/* ESAI1-SCKR */
+	mxc_iomux_set_pad(MX53_PIN_FEC_MDIO, pad_val);
+	/* ESAI1-FSR */
+	mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK, pad_val);
+	/* ESAI1-HCKT */
+	mxc_iomux_set_pad(MX53_PIN_FEC_RXD0, pad_val);
+	/* ESAI1-SCKT */
+	mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV, pad_val);
+	/* ESAI1-FST */
+	mxc_iomux_set_pad(MX53_PIN_FEC_RXD1, pad_val);
+	/* ESAI1-TX5-RX0 */
+	mxc_iomux_set_pad(MX53_PIN_FEC_MDC, pad_val);
+	/* ESAI1-TX4-RX1 */
+	mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, pad_val);
+	/* ESAI1-TX3-RX2 */
+	mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, pad_val);
+	/* ESAI1-TX2-RX3 */
+	mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, pad_val);
+	/* ESAI1-TX1 */
+	mxc_iomux_set_pad(MX53_PIN_NANDF_CS3, pad_val);
+	/* ESAI1-TX0 */
+	mxc_iomux_set_pad(MX53_PIN_NANDF_CS2, pad_val);
+
+	/* ESAI1-HCKR */
+	mxc_iomux_set_input(MUX_IN_ESAI1_IPP_IND_HCKR_SELECT_INPUT,
+		INPUT_CTL_PATH0);
+	/* ESAI1-SCKR */
+	mxc_iomux_set_input(MUX_IN_ESAI1_IPP_IND_SCKR_SELECT_INPUT,
+		INPUT_CTL_PATH0);
+	/* ESAI1-FSR */
+	mxc_iomux_set_input(MUX_IN_ESAI1_IPP_IND_FSR_SELECT_INPUT,
+		INPUT_CTL_PATH0);
+	/* ESAI1-HCKT */
+	mxc_iomux_set_input(MUX_IN_ESAI1_IPP_IND_HCKT_SELECT_INPUT,
+		INPUT_CTL_PATH0);
+	/* ESAI1-SCKT */
+	mxc_iomux_set_input(MUX_IN_ESAI1_IPP_IND_SCKT_SELECT_INPUT,
+		INPUT_CTL_PATH0);
+	/* ESAI1-FST */
+	mxc_iomux_set_input(MUX_IN_ESAI1_IPP_IND_FST_SELECT_INPUT,
+		INPUT_CTL_PATH0);
+	/* ESAI1-TX5-RX0 */
+	mxc_iomux_set_input(MUX_IN_ESAI1_IPP_IND_SDO5_SDI0_SELECT_INPUT,
+		INPUT_CTL_PATH0);
+	/* ESAI1-TX4-RX1 */
+	mxc_iomux_set_input(MUX_IN_ESAI1_IPP_IND_SDO4_SDI1_SELECT_INPUT,
+		INPUT_CTL_PATH0);
+	/* ESAI1-TX3-RX2 */
+	mxc_iomux_set_input(MUX_IN_ESAI1_IPP_IND_SDO3_SDI2_SELECT_INPUT,
+		INPUT_CTL_PATH0);
+	/* ESAI1-TX2-RX3 */
+	mxc_iomux_set_input(MUX_IN_ESAI1_IPP_IND_SDO2_SDI3_SELECT_INPUT,
+		INPUT_CTL_PATH0);
+	/* ESAI1-TX1 */
+	mxc_iomux_set_input(MUX_IN_ESAI1_IPP_IND_SDO1_SELECT_INPUT,
+		INPUT_CTL_PATH0);
+	/* ESAI1-TX0 */
+	mxc_iomux_set_input(MUX_IN_ESAI1_IPP_IND_SDO0_SELECT_INPUT,
+		INPUT_CTL_PATH0);
+
+}
+EXPORT_SYMBOL(gpio_activate_esai_ports);
+
+void gpio_cs42888_pdwn(int pdwn)
+{
+	if (pdwn)
+		gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_12), 0);
+	else
+		gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_12), 1);
+}
+EXPORT_SYMBOL(gpio_cs42888_pdwn);
+
+static void gpio_usbotg_vbus_active(void)
+{
+	if (board_is_mx53_arm2()) {
+		/* MX53 ARM2 CPU board */
+		/* Enable OTG VBus with GPIO low */
+		gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_EIM_D22), 0);
+	} else  if (board_is_mx53_evk_a()) {
+		/* MX53 EVK board ver A*/
+		/* Enable OTG VBus with GPIO low */
+		gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_EIM_A23), 0);
+	} else  if (board_is_mx53_evk_b()) {
+		/* MX53 EVK board ver B*/
+		/* Enable OTG VBus with GPIO high */
+		gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_EIM_A23), 1);
+	}
+}
+
+static void gpio_usbotg_vbus_inactive(void)
+{
+	if (board_is_mx53_arm2()) {
+		/* MX53 ARM2 CPU board */
+		/* Disable OTG VBus with GPIO high */
+		gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_EIM_D22), 1);
+	} else  if (board_is_mx53_evk_a()) {
+		/* MX53 EVK board ver A*/
+		/* Disable OTG VBus with GPIO high */
+		gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_EIM_A23), 1);
+	} else  if (board_is_mx53_evk_b()) {
+		/* MX53 EVK board ver B*/
+		/* Disable OTG VBus with GPIO low */
+		gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_EIM_A23), 0);
+	}
+}
+
+
+void mx53_gpio_usbotg_driver_vbus(bool on)
+{
+	if (on)
+		gpio_usbotg_vbus_active();
+	else
+		gpio_usbotg_vbus_inactive();
+}
+EXPORT_SYMBOL(mx53_gpio_usbotg_driver_vbus);
+
+void mx53_gpio_host1_driver_vbus(bool on)
+{
+	if (on)
+		gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_2), 1);
+	else
+		gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_2), 0);
+}
+EXPORT_SYMBOL(mx53_gpio_host1_driver_vbus);
diff --git a/arch/arm/mach-mx5/mx53_evk_pmic_mc13892.c b/arch/arm/mach-mx5/mx53_evk_pmic_mc13892.c
index be5f850fcf97..f8ec651cd459 100644
--- a/arch/arm/mach-mx5/mx53_evk_pmic_mc13892.c
+++ b/arch/arm/mach-mx5/mx53_evk_pmic_mc13892.c
@@ -23,8 +23,8 @@
 #include <linux/regulator/machine.h>
 #include <linux/mfd/mc13892/core.h>
 #include <mach/irqs.h>
-
-#include <mach/iomux-mx53.h>
+#include "iomux.h"
+#include "mx53_pins.h"
 
 /*
  * Convenience conversion.
@@ -183,8 +183,6 @@ static struct regulator_init_data vvideo_init = {
 		.min_uV = mV_to_uV(2500),
 		.max_uV = mV_to_uV(2775),
 		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
-		.always_on = 1,
-		.boot_on = 1,
 	}
 };
 
@@ -268,7 +266,7 @@ static struct regulator_init_data gpo4_init = {
 		.name = "GPO4",
 	}
 };
-#if 0
+
 /*!
  * the event handler for power on event
  */
@@ -276,20 +274,20 @@ static void power_on_evt_handler(void)
 {
 	pr_info("pwr on event1 is received \n");
 }
-#endif
+
 static int mc13892_regulator_init(struct mc13892 *mc13892)
 {
 	unsigned int value;
-//	pmic_event_callback_t power_key_event;
+	pmic_event_callback_t power_key_event;
 	int register_mask;
 
 	pr_info("Initializing regulators for MX53 EVK \n");
-#if 0
+
 	/* subscribe PWRON1 event to enable ON_OFF key */
 	power_key_event.param = NULL;
 	power_key_event.func = (void *)power_on_evt_handler;
 	pmic_event_subscribe(EVENT_PWRONI, power_key_event);
-#endif
+
 	/* Bit 4 DRM: keep VSRTC and CLK32KMCU on for all states */
 #if defined(CONFIG_RTC_DRV_MXC_V2) || defined(CONFIG_RTC_DRV_MXC_V2_MODULE)
 	value = BITFVAL(DRM, 1);
@@ -339,7 +337,7 @@ static struct mc13892_platform_data mc13892_plat = {
 
 static struct i2c_board_info __initdata mc13892_i2c_device = {
 	I2C_BOARD_INFO("mc13892", 0x08),
-	.irq = IOMUX_TO_IRQ_V3(203),
+	.irq = IOMUX_TO_IRQ(MX53_PIN_GPIO_16),
 	.platform_data = &mc13892_plat,
 };
 
diff --git a/arch/arm/mach-mx5/pm.c b/arch/arm/mach-mx5/pm.c
index b2bf2f8355fd..2839bffeda62 100644
--- a/arch/arm/mach-mx5/pm.c
+++ b/arch/arm/mach-mx5/pm.c
@@ -29,10 +29,6 @@
 
 #define MXC_SRPG_EMPGC0_SRPGCR (IO_ADDRESS(GPC_BASE_ADDR) + 0x2C0)
 #define MXC_SRPG_EMPGC1_SRPGCR (IO_ADDRESS(GPC_BASE_ADDR) + 0x2D0)
-#define DATABAHN_CTL_REG0			0
-#define DATABAHN_CTL_REG19		0x4c
-#define DATABAHN_CTL_REG79		0x13c
-#define DATABAHN_PHY_REG25		0x264
 
 static struct cpu_wp *cpu_wp_tbl;
 static struct clk *cpu_clk;
@@ -47,17 +43,16 @@ extern int set_cpu_freq(int wp);
 static struct device *pm_dev;
 struct clk *gpc_dvfs_clk;
 extern void cpu_do_suspend_workaround(u32 sdclk_iomux_addr);
-extern void mx50_suspend(u32 databahn_addr);
+extern void cpu_cortexa8_do_idle(void *);
 extern struct cpu_wp *(*get_cpu_wp)(int *wp);
-extern void __iomem *databahn_base;
 
 extern int iram_ready;
 void *suspend_iram_base;
 void (*suspend_in_iram)(void *sdclk_iomux_addr) = NULL;
-void __iomem *suspend_param1;
 
-static int mx5_suspend_enter(suspend_state_t state)
+static int mx51_suspend_enter(suspend_state_t state)
 {
+	void __iomem *sdclk_iomux_addr = IO_ADDRESS(IOMUXC_BASE_ADDR + 0x4b8);
 	u32 * wake_src;
 
 	/* Check that we have a wake up source. We don't want to suspend if not.*/
@@ -89,15 +84,12 @@ static int mx5_suspend_enter(suspend_state_t state)
 		local_flush_tlb_all();
 		flush_cache_all();
 
-		if (cpu_is_mx51() || cpu_is_mx53()) {
-			/* Run the suspend code from iRAM. */
-			suspend_in_iram(suspend_param1);
+		/* Run the suspend code from iRAM. */
+		suspend_in_iram(sdclk_iomux_addr);
 
-			/*clear the EMPGC0/1 bits */
-			__raw_writel(0, MXC_SRPG_EMPGC0_SRPGCR);
-			__raw_writel(0, MXC_SRPG_EMPGC1_SRPGCR);
-		} else
-			suspend_in_iram(databahn_base);
+		/*clear the EMPGC0/1 bits */
+		__raw_writel(0, MXC_SRPG_EMPGC0_SRPGCR);
+		__raw_writel(0, MXC_SRPG_EMPGC1_SRPGCR);
 	} else {
 			cpu_do_idle();
 	}
@@ -109,7 +101,7 @@ static int mx5_suspend_enter(suspend_state_t state)
 /*
  * Called after processes are frozen, but before we shut down devices.
  */
-static int mx5_suspend_prepare(void)
+static int mx51_suspend_prepare(void)
 {
 #if defined(CONFIG_CPU_FREQ)
 	struct cpufreq_freqs freqs;
@@ -132,7 +124,7 @@ static int mx5_suspend_prepare(void)
 /*
  * Called before devices are re-setup.
  */
-static void mx5_suspend_finish(void)
+static void mx51_suspend_finish(void)
 {
 #if defined(CONFIG_CPU_FREQ)
 	struct cpufreq_freqs freqs;
@@ -155,35 +147,35 @@ static void mx5_suspend_finish(void)
 /*
  * Called after devices are re-setup, but before processes are thawed.
  */
-static void mx5_suspend_end(void)
+static void mx51_suspend_end(void)
 {
 }
 
-static int mx5_pm_valid(suspend_state_t state)
+static int mx51_pm_valid(suspend_state_t state)
 {
 	return (state > PM_SUSPEND_ON && state <= PM_SUSPEND_MAX);
 }
 
-struct platform_suspend_ops mx5_suspend_ops = {
-	.valid = mx5_pm_valid,
-	.prepare = mx5_suspend_prepare,
-	.enter = mx5_suspend_enter,
-	.finish = mx5_suspend_finish,
-	.end = mx5_suspend_end,
+struct platform_suspend_ops mx51_suspend_ops = {
+	.valid = mx51_pm_valid,
+	.prepare = mx51_suspend_prepare,
+	.enter = mx51_suspend_enter,
+	.finish = mx51_suspend_finish,
+	.end = mx51_suspend_end,
 };
 
 
-static int __devinit mx5_pm_probe(struct platform_device *pdev)
+static int __devinit mx51_pm_probe(struct platform_device *pdev)
 {
 	pm_dev = &pdev->dev;
 	return 0;
 }
 
-static struct platform_driver mx5_pm_driver = {
+static struct platform_driver mx51_pm_driver = {
 	.driver = {
-		   .name = "mx5_pm",
+		   .name = "mx51_pm",
 		   },
-	.probe = mx5_pm_probe,
+	.probe = mx51_pm_probe,
 };
 
 static int __init pm_init(void)
@@ -191,32 +183,19 @@ static int __init pm_init(void)
 	int cpu_wp_nr;
 	unsigned long iram_paddr;
 
-	pr_info("Static Power Management for Freescale i.MX5\n");
-	if (platform_driver_register(&mx5_pm_driver) != 0) {
-		printk(KERN_ERR "mx5_pm_driver register failed\n");
+	pr_info("Static Power Management for Freescale i.MX51\n");
+	if (platform_driver_register(&mx51_pm_driver) != 0) {
+		printk(KERN_ERR "mx51_pm_driver register failed\n");
 		return -ENODEV;
 	}
-	suspend_set_ops(&mx5_suspend_ops);
+	suspend_set_ops(&mx51_suspend_ops);
 	/* Move suspend routine into iRAM */
 	iram_alloc(SZ_4K, &iram_paddr);
 	/* Need to remap the area here since we want the memory region
 		 to be executable. */
 	suspend_iram_base = __arm_ioremap(iram_paddr, SZ_4K,
 					  MT_HIGH_VECTORS);
-
-	if (cpu_is_mx51() || cpu_is_mx53()) {
-		suspend_param1 = IO_ADDRESS(IOMUXC_BASE_ADDR + 0x4b8);
-		memcpy(suspend_iram_base, cpu_do_suspend_workaround,
-				SZ_4K);
-	} else if (cpu_is_mx50()) {
-		/*
-		 * Need to run the suspend code from IRAM as the DDR needs
-		 * to be put into self refresh mode manually.
-		 */
-		memcpy(suspend_iram_base, mx50_suspend, SZ_4K);
-
-		suspend_param1 = databahn_base;
-	}
+	memcpy(suspend_iram_base, cpu_do_suspend_workaround, SZ_4K);
 	suspend_in_iram = (void *)suspend_iram_base;
 
 	cpu_wp_tbl = get_cpu_wp(&cpu_wp_nr);
@@ -235,7 +214,7 @@ static int __init pm_init(void)
 static void __exit pm_cleanup(void)
 {
 	/* Unregister the device structure */
-	platform_driver_unregister(&mx5_pm_driver);
+	platform_driver_unregister(&mx51_pm_driver);
 }
 
 module_init(pm_init);
diff --git a/arch/arm/mach-mx5/system.c b/arch/arm/mach-mx5/system.c
index 199c30e26947..da27fc4605a3 100644
--- a/arch/arm/mach-mx5/system.c
+++ b/arch/arm/mach-mx5/system.c
@@ -16,7 +16,6 @@
 #include <linux/platform_device.h>
 #include <asm/io.h>
 #include <mach/hardware.h>
-#include <mach/clock.h>
 #include <asm/proc-fns.h>
 #include <asm/system.h>
 #include "crm_regs.h"
@@ -34,14 +33,11 @@
 
 extern int mxc_jtag_enabled;
 extern int iram_ready;
-extern void __iomem *ccm_base;
-extern void __iomem *databahn_base;
-extern void (*wait_in_iram)(void *ccm_addr, void *databahn_addr);
-extern void *wait_in_iram_base;
-extern void mx50_wait(u32 ccm_base, u32 databahn_addr);
-
 static struct clk *gpc_dvfs_clk;
 
+extern void cpu_cortexa8_do_idle(void *addr);
+
+
 /* set cpu low power mode before WFI instruction */
 void mxc_cpu_lp_set(enum mxc_cpu_pwr_mode mode)
 {
@@ -70,7 +66,6 @@ void mxc_cpu_lp_set(enum mxc_cpu_pwr_mode mode)
 		if (mode == WAIT_UNCLOCKED_POWER_OFF) {
 			ccm_clpcr |= (0x1 << MXC_CCM_CLPCR_LPM_OFFSET);
 			ccm_clpcr &= ~MXC_CCM_CLPCR_VSTBY;
-			ccm_clpcr &= ~MXC_CCM_CLPCR_SBYOS;
 			stop_mode = 0;
 		} else {
 			ccm_clpcr |= (0x2 << MXC_CCM_CLPCR_LPM_OFFSET);
@@ -101,8 +96,7 @@ void mxc_cpu_lp_set(enum mxc_cpu_pwr_mode mode)
 	__raw_writel(ccm_clpcr, MXC_CCM_CLPCR);
 	if (cpu_is_mx51())
 		__raw_writel(arm_srpgcr, MXC_SRPG_ARM_SRPGCR);
-	if (!cpu_is_mx50())
-		__raw_writel(arm_srpgcr, MXC_SRPG_NEON_SRPGCR);
+	__raw_writel(arm_srpgcr, MXC_SRPG_NEON_SRPGCR);
 	if (stop_mode) {
 		__raw_writel(empgc0, MXC_SRPG_EMPGC0_SRPGCR);
 		__raw_writel(empgc1, MXC_SRPG_EMPGC1_SRPGCR);
@@ -156,21 +150,14 @@ static int arch_idle_mode = WAIT_UNCLOCKED_POWER_OFF;
  */
 void arch_idle(void)
 {
-/*	if (likely(!mxc_jtag_enabled)) */{
-		struct clk *ddr_clk = clk_get(NULL, "ddr_clk");
+	if (likely(!mxc_jtag_enabled)) {
 		if (gpc_dvfs_clk == NULL)
 			gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs_clk");
 		/* gpc clock is needed for SRPG */
 		clk_enable(gpc_dvfs_clk);
 		mxc_cpu_lp_set(arch_idle_mode);
-		if (cpu_is_mx50() && (clk_get_usecount(ddr_clk) == 0)) {
-			memcpy(wait_in_iram_base, mx50_wait, SZ_4K);
-			wait_in_iram = (void *)wait_in_iram_base;
-			wait_in_iram(ccm_base, databahn_base);
-		} else
-			cpu_do_idle();
+		cpu_do_idle();
 		clk_disable(gpc_dvfs_clk);
-		clk_put(ddr_clk);
 	}
 }
 
@@ -190,93 +177,3 @@ void arch_reset(char mode)
 	/* Assert SRS signal */
 	mxc_wd_reset();
 }
-
-
-static int __mxs_reset_block(void __iomem *hwreg, int just_enable)
-{
-	u32 c;
-	int timeout;
-
-	/* the process of software reset of IP block is done
-	   in several steps:
-
-	   - clear SFTRST and wait for block is enabled;
-	   - clear clock gating (CLKGATE bit);
-	   - set the SFTRST again and wait for block is in reset;
-	   - clear SFTRST and wait for reset completion.
-	 */
-	c = __raw_readl(hwreg);
-	c &= ~(1 << 31);	/* clear SFTRST */
-	__raw_writel(c, hwreg);
-	for (timeout = 1000000; timeout > 0; timeout--)
-		/* still in SFTRST state ? */
-		if ((__raw_readl(hwreg) & (1 << 31)) == 0)
-			break;
-	if (timeout <= 0) {
-		printk(KERN_ERR "%s(%p): timeout when enabling\n",
-		       __func__, hwreg);
-		return -ETIME;
-	}
-
-	c = __raw_readl(hwreg);
-	c &= ~(1 << 30);	/* clear CLKGATE */
-	__raw_writel(c, hwreg);
-
-	if (!just_enable) {
-		c = __raw_readl(hwreg);
-		c |= (1 << 31);	/* now again set SFTRST */
-		__raw_writel(c, hwreg);
-		for (timeout = 1000000; timeout > 0; timeout--)
-			/* poll until CLKGATE set */
-			if (__raw_readl(hwreg) & (1 << 30))
-				break;
-		if (timeout <= 0) {
-			printk(KERN_ERR "%s(%p): timeout when resetting\n",
-			       __func__, hwreg);
-			return -ETIME;
-		}
-
-		c = __raw_readl(hwreg);
-		c &= ~(1 << 31);	/* clear SFTRST */
-		__raw_writel(c, hwreg);
-		for (timeout = 1000000; timeout > 0; timeout--)
-			/* still in SFTRST state ? */
-			if ((__raw_readl(hwreg) & (1 << 31)) == 0)
-				break;
-		if (timeout <= 0) {
-			printk(KERN_ERR "%s(%p): timeout when enabling "
-			       "after reset\n", __func__, hwreg);
-			return -ETIME;
-		}
-
-		c = __raw_readl(hwreg);
-		c &= ~(1 << 30);	/* clear CLKGATE */
-		__raw_writel(c, hwreg);
-	}
-	for (timeout = 1000000; timeout > 0; timeout--)
-		/* still in SFTRST state ? */
-		if ((__raw_readl(hwreg) & (1 << 30)) == 0)
-			break;
-
-	if (timeout <= 0) {
-		printk(KERN_ERR "%s(%p): timeout when unclockgating\n",
-		       __func__, hwreg);
-		return -ETIME;
-	}
-
-	return 0;
-}
-
-int mxs_reset_block(void __iomem *hwreg, int just_enable)
-{
-	int try = 10;
-	int r;
-
-	while (try--) {
-		r = __mxs_reset_block(hwreg, just_enable);
-		if (!r)
-			break;
-		pr_debug("%s: try %d failed\n", __func__, 10 - try);
-	}
-	return r;
-}
diff --git a/arch/arm/mach-mx5/usb_dr.c b/arch/arm/mach-mx5/usb_dr.c
index 4f36379b8d64..0878fd6e0d38 100644
--- a/arch/arm/mach-mx5/usb_dr.c
+++ b/arch/arm/mach-mx5/usb_dr.c
@@ -18,12 +18,12 @@
 #include <linux/fsl_devices.h>
 #include <mach/arc_otg.h>
 #include <mach/hardware.h>
-#include <asm/delay.h>
 #include "usb.h"
 
 #if defined(CONFIG_USB_OTG) || defined(CONFIG_USB_EHCI_ARC_OTG) || defined(CONFIG_USB_GADGET_ARC)
 static int usbotg_init_ext(struct platform_device *pdev);
 static void usbotg_uninit_ext(struct fsl_usb2_platform_data *pdata);
+static void _wake_up_enable(struct fsl_usb2_platform_data *pdata, bool enable);
 static void usbotg_clock_gate(bool on);
 
 /*
@@ -40,6 +40,7 @@ static struct fsl_usb2_platform_data dr_utmi_config = {
 	.gpio_usb_active   = gpio_usbotg_hs_active,
 	.gpio_usb_inactive = gpio_usbotg_hs_inactive,
 	.usb_clock_for_pm  = usbotg_clock_gate,
+	.wake_up_enable = _wake_up_enable,
 	.transceiver       = "utmi",
 };
 
@@ -47,13 +48,6 @@ static struct fsl_usb2_platform_data dr_utmi_config = {
 static int usbotg_init_ext(struct platform_device *pdev)
 {
 	struct clk *usb_clk;
-	if (cpu_is_mx50()) {
-		usb_clk = clk_get(&pdev->dev, "usb_phy1_clk");
-		clk_enable(usb_clk);
-		clk_put(usb_clk);
-
-		return usbotg_init(pdev);
-	}
 
 	usb_clk = clk_get(NULL, "usboh3_clk");
 	clk_enable(usb_clk);
@@ -75,15 +69,6 @@ static void usbotg_uninit_ext(struct fsl_usb2_platform_data *pdata)
 {
 	struct clk *usb_clk;
 
-	if (cpu_is_mx50()) {
-		usb_clk = clk_get(&pdata->pdev->dev, "usb_phy1_clk");
-		clk_disable(usb_clk);
-		clk_put(usb_clk);
-
-		usbotg_uninit(pdata);
-		return;
-	}
-
 	usb_clk = clk_get(NULL, "usboh3_clk");
 	clk_disable(usb_clk);
 	clk_put(usb_clk);
@@ -95,149 +80,33 @@ static void usbotg_uninit_ext(struct fsl_usb2_platform_data *pdata)
 	usbotg_uninit(pdata);
 }
 
-#define ENABLED_BY_HOST   (0x1 << 0)
-#define ENABLED_BY_DEVICE (0x1 << 1)
-#if defined(CONFIG_USB_EHCI_ARC_OTG) && defined(CONFIG_USB_GADGET_ARC)
-/* Below two macros are used at otg mode to indicate usb mode*/
-static u32 wakeup_irq_enable_src = 0;
-static void __wakeup_irq_enable(bool on, int source)
+static void _wake_up_enable(struct fsl_usb2_platform_data *pdata, bool enable)
 {
-	/* otg host and device share the OWIE bit, only when host and device
-	* all enable the wakeup irq, we can enable the OWIE bit
-	*/
-	if (on) {
-		wakeup_irq_enable_src |= source;
-		if (wakeup_irq_enable_src == (ENABLED_BY_HOST | ENABLED_BY_DEVICE)) {
+	if (get_usb_mode(pdata) == FSL_USB_DR_DEVICE) {
+		if (enable) {
 			USBCTRL |= UCTRL_OWIE;
+			USBCTRL_HOST2 |= UCTRL_H2OVBWK_EN;
 			USB_PHY_CTR_FUNC |= USB_UTMI_PHYCTRL_CONF2;
-			printk("OTG wakeup irq is enabled\n");
+		} else {
+			USBCTRL &= ~UCTRL_OWIE;
+			USBCTRL_HOST2 &= ~UCTRL_H2OVBWK_EN;
+			USB_PHY_CTR_FUNC &= ~USB_UTMI_PHYCTRL_CONF2;
 		}
-	}else {
-		printk("OTG wakeup irq disable\n");
-		USB_PHY_CTR_FUNC &= ~USB_UTMI_PHYCTRL_CONF2;
-		USBCTRL &= ~UCTRL_OWIE;
-		wakeup_irq_enable_src &= ~source;
-		/* The interrupt must be disabled for at least 3 clock
-		 * cycles of the standby clock(32k Hz) , that is 0.094 ms*/
-		udelay(100);
-	}
-}
-#else
-static void __wakeup_irq_enable(bool on, int source)
-{
-	if (on) {
-		USBCTRL |= UCTRL_OWIE;
-		USB_PHY_CTR_FUNC |= USB_UTMI_PHYCTRL_CONF2;
-	}else {
-		USBCTRL &= ~UCTRL_OWIE;
-		USB_PHY_CTR_FUNC &= ~USB_UTMI_PHYCTRL_CONF2;
-		/* The interrupt must be disabled for at least 3 clock
-		 * cycles of the standby clock(32k Hz) , that is 0.094 ms*/
-		udelay(100);
-	}
-}
-#endif
-
-#ifdef CONFIG_USB_EHCI_ARC_OTG
-static void _host_wakeup_enable(struct fsl_usb2_platform_data *pdata, bool enable)
-{
-	__wakeup_irq_enable(enable, ENABLED_BY_HOST);
-	/* host only care the ID change wakeup event */
-	if (enable) {
-		USBCTRL_HOST2 |= UCTRL_H2OIDWK_EN;
-	}else {
-		USBCTRL_HOST2 &= ~UCTRL_H2OIDWK_EN;
-		/* The interrupt must be disabled for at least 2 clock
-		 * cycles of the standby clock(32k Hz) , that is 0.0625 ms*/
-		udelay(100);
-	}
-}
-#endif
-
-#ifdef CONFIG_USB_GADGET_ARC
-static void _device_wakeup_enable(struct fsl_usb2_platform_data *pdata, bool enable)
-{
-	__wakeup_irq_enable(enable, ENABLED_BY_DEVICE);
-	/* if udc is not used by any gadget, we can not enable the vbus wakeup */
-	if (!pdata->port_enables)
-	{
-		USBCTRL_HOST2 &= ~UCTRL_H2OVBWK_EN;
-		return;
-	}
-	if (enable) {
-		USBCTRL_HOST2 |= UCTRL_H2OVBWK_EN;
-	}else {
-		USBCTRL_HOST2 &= ~UCTRL_H2OVBWK_EN;
-	}
-}
-#endif
-
-#if defined(CONFIG_USB_EHCI_ARC_OTG) && defined(CONFIG_USB_GADGET_ARC)
-static u32 low_power_enable_src = 0;
-static void __phy_lowpower_suspend(bool enable, int source)
-{
-	if (enable) {
-		low_power_enable_src |= source;
-		if (low_power_enable_src == (ENABLED_BY_HOST | ENABLED_BY_DEVICE)) {
-			UOG_PORTSC1 |= PORTSC_PHCD;
-		printk("OTG phy lowpower enable\n");
+	} else {
+		if (enable) {
+			USBCTRL |= UCTRL_OWIE;
+			USBCTRL_HOST2 |= (1 << 5);
+		} else {
+			USBCTRL &= ~UCTRL_OWIE;
+			USBCTRL_HOST2 &= ~(1 << 5);
 		}
-	}else {
-		printk("OTG phy lowpower disable\n");
-		UOG_PORTSC1 &= ~PORTSC_PHCD;
-		low_power_enable_src &= ~source;
-	}
-}
-#else
-static void __phy_lowpower_suspend(bool enable, int source)
-{
-	if (enable) {
-		UOG_PORTSC1 |= PORTSC_PHCD;
-	}else {
-		UOG_PORTSC1 &= ~PORTSC_PHCD;
 	}
 }
-#endif
-
-#ifdef CONFIG_USB_EHCI_ARC_OTG
-static void _host_phy_lowpower_suspend(bool enable)
-{
-	__phy_lowpower_suspend(enable, ENABLED_BY_HOST);
-}
-#endif
-
-#ifdef CONFIG_USB_GADGET_ARC
-static void _device_phy_lowpower_suspend(bool enable)
-{
-	__phy_lowpower_suspend(enable, ENABLED_BY_DEVICE);
-}
-#endif
 
 static void usbotg_clock_gate(bool on)
 {
 	struct clk *usb_clk;
 
-	if (cpu_is_mx50()) {
-		if (on) {
-			usb_clk = clk_get(NULL, "usb_ahb_clk");
-			clk_enable(usb_clk);
-			clk_put(usb_clk);
-
-			usb_clk = clk_get(NULL, "usb_phy1_clk");
-			clk_enable(usb_clk);
-			clk_put(usb_clk);
-		} else {
-			usb_clk = clk_get(NULL, "usb_phy1_clk");
-			clk_disable(usb_clk);
-			clk_put(usb_clk);
-
-			usb_clk = clk_get(NULL, "usb_ahb_clk");
-			clk_disable(usb_clk);
-			clk_put(usb_clk);
-		}
-		return;
-	}
-
 	if (on) {
 		usb_clk = clk_get(NULL, "usb_ahb_clk");
 		clk_enable(usb_clk);
@@ -287,15 +156,11 @@ void __init mx5_usb_dr_init(void)
 #endif
 #ifdef CONFIG_USB_EHCI_ARC_OTG
 	dr_utmi_config.operating_mode = DR_HOST_MODE;
-	dr_utmi_config.wake_up_enable = _host_wakeup_enable;
-	dr_utmi_config.phy_lowpower_suspend = _host_phy_lowpower_suspend;
 	platform_device_add_data(&mxc_usbdr_host_device, &dr_utmi_config, sizeof(dr_utmi_config));
 	platform_device_register(&mxc_usbdr_host_device);
 #endif
 #ifdef CONFIG_USB_GADGET_ARC
 	dr_utmi_config.operating_mode = DR_UDC_MODE;
-	dr_utmi_config.wake_up_enable = _device_wakeup_enable;
-	dr_utmi_config.phy_lowpower_suspend = _device_phy_lowpower_suspend;
 	platform_device_add_data(&mxc_usbdr_udc_device, &dr_utmi_config, sizeof(dr_utmi_config));
 	platform_device_register(&mxc_usbdr_udc_device);
 #endif
diff --git a/arch/arm/mach-mx5/usb_h1.c b/arch/arm/mach-mx5/usb_h1.c
index 3c53ed8901ae..52a2bcafd765 100644
--- a/arch/arm/mach-mx5/usb_h1.c
+++ b/arch/arm/mach-mx5/usb_h1.c
@@ -17,15 +17,13 @@
 #include <linux/clk.h>
 #include <linux/platform_device.h>
 #include <linux/fsl_devices.h>
-#include <asm/delay.h>
 #include <mach/arc_otg.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include "usb.h"
 #include "iomux.h"
 #include "mx51_pins.h"
-//#undef pr_debug
-//#define pr_debug printk
+
 /*
  * USB Host1 HS port
  */
@@ -71,49 +69,13 @@ static void _wake_up_enable(struct fsl_usb2_platform_data *pdata, bool enable)
 {
 	if (enable)
 		USBCTRL |= UCTRL_H1WIE;
-	else {
+	else
 		USBCTRL &= ~UCTRL_H1WIE;
-		/* The interrupt must be disabled for at least 3
-		* cycles of the standby clock(32k Hz) , that is 0.094 ms*/
-		udelay(100);
-	}
-}
-
-static void _phy_lowpower_suspend(bool enable)
-{
-	if (enable) {
-		UH1_PORTSC1 |= PORTSC_PHCD;
-	}else {
-		UH1_PORTSC1 &= ~PORTSC_PHCD;
-	}
 }
 
 static void usbotg_clock_gate(bool on)
 {
 	struct clk *usb_clk;
-	if (cpu_is_mx50()) {
-		if (on) {
-			usb_clk = clk_get(NULL, "usb_ahb_clk");
-			clk_enable(usb_clk);
-			clk_put(usb_clk);
-
-		} else {
-			usb_clk = clk_get(NULL, "usb_ahb_clk");
-			clk_disable(usb_clk);
-			clk_put(usb_clk);
-		}
-		return;
-	}
-	if (cpu_is_mx53()) {
-		usb_clk = clk_get(NULL, "usb_phy2_clk");
-		if (on) {
-			clk_enable(usb_clk);
-		} else {
-			clk_disable(usb_clk);
-		}
-		clk_put(usb_clk);
-	}
-
 	if (on) {
 		usb_clk = clk_get(NULL, "usb_ahb_clk");
 		clk_enable(usb_clk);
@@ -153,7 +115,7 @@ static int fsl_usb_host_init_ext(struct platform_device *pdev)
 		clk_disable(usb_clk);
 		clk_put(usb_clk);
 	} else if (cpu_is_mx50()) {
-		usb_clk = clk_get(NULL, "usb_phy2_clk");
+		usb_clk = clk_get(&pdev->dev, "usb_phy2_clk");
 		clk_enable(usb_clk);
 		clk_put(usb_clk);
 	}
@@ -191,7 +153,7 @@ static void fsl_usb_host_uninit_ext(struct fsl_usb2_platform_data *pdata)
 		clk_disable(usb_clk);
 		clk_put(usb_clk);
 	} else if (cpu_is_mx50()) {
-		usb_clk = clk_get(NULL, "usb_phy2_clk");
+		usb_clk = clk_get(&pdata->pdev->dev, "usb_phy2_clk");
 		clk_disable(usb_clk);
 		clk_put(usb_clk);
 	}
@@ -208,7 +170,6 @@ static struct fsl_usb2_platform_data usbh1_config = {
 	.power_budget = 500,	/* 500 mA max power */
 	.wake_up_enable = _wake_up_enable,
 	.usb_clock_for_pm  = usbotg_clock_gate,
-	.phy_lowpower_suspend = _phy_lowpower_suspend,
 	.transceiver = "utmi",
 };
 
diff --git a/arch/arm/mach-pxa/cpufreq-pxa2xx.c b/arch/arm/mach-pxa/cpufreq-pxa2xx.c
index 3a8ee2272add..983cc8c20081 100644
--- a/arch/arm/mach-pxa/cpufreq-pxa2xx.c
+++ b/arch/arm/mach-pxa/cpufreq-pxa2xx.c
@@ -155,7 +155,7 @@ MODULE_PARM_DESC(pxa255_turbo_table, "Selects the frequency table (0 = run table
 
 static pxa_freqs_t pxa27x_freqs[] = {
 	{104000, 104000, PXA27x_CCCR(1,	 8, 2), 0, CCLKCFG2(1, 0, 1),  900000, 1705000 },
-	{156000, 104000, PXA27x_CCCR(1,	 8, 6), 0, CCLKCFG2(1, 1, 1), 1000000, 1705000 },
+	{156000, 104000, PXA27x_CCCR(1,	 8, 3), 0, CCLKCFG2(1, 0, 1), 1000000, 1705000 },
 	{208000, 208000, PXA27x_CCCR(0, 16, 2), 1, CCLKCFG2(0, 0, 1), 1180000, 1705000 },
 	{312000, 208000, PXA27x_CCCR(1, 16, 3), 1, CCLKCFG2(1, 0, 1), 1250000, 1705000 },
 	{416000, 208000, PXA27x_CCCR(1, 16, 4), 1, CCLKCFG2(1, 0, 1), 1350000, 1705000 },
diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c
index 9cd09465a0e8..110e1f174f25 100644
--- a/arch/arm/mach-pxa/em-x270.c
+++ b/arch/arm/mach-pxa/em-x270.c
@@ -497,16 +497,15 @@ static int em_x270_usb_hub_init(void)
 		goto err_free_vbus_gpio;
 
 	/* USB Hub power-on and reset */
-	gpio_direction_output(usb_hub_reset, 0);
+	gpio_direction_output(usb_hub_reset, 1);
+	gpio_direction_output(GPIO9_USB_VBUS_EN, 0);
 	regulator_enable(em_x270_usb_ldo);
-	gpio_set_value(usb_hub_reset, 1);
 	gpio_set_value(usb_hub_reset, 0);
+	gpio_set_value(usb_hub_reset, 1);
 	regulator_disable(em_x270_usb_ldo);
 	regulator_enable(em_x270_usb_ldo);
-	gpio_set_value(usb_hub_reset, 1);
-
-	/* enable VBUS */
-	gpio_direction_output(GPIO9_USB_VBUS_EN, 1);
+	gpio_set_value(usb_hub_reset, 0);
+	gpio_set_value(GPIO9_USB_VBUS_EN, 1);
 
 	return 0;
 
diff --git a/arch/arm/mach-pxa/sharpsl_pm.c b/arch/arm/mach-pxa/sharpsl_pm.c
index 2546c066cd6e..629e05d1196e 100644
--- a/arch/arm/mach-pxa/sharpsl_pm.c
+++ b/arch/arm/mach-pxa/sharpsl_pm.c
@@ -678,8 +678,8 @@ static int corgi_enter_suspend(unsigned long alarm_time, unsigned int alarm_enab
 		dev_dbg(sharpsl_pm.dev, "User triggered wakeup in offline charger.\n");
 	}
 
-	if ((!sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_LOCK)) || (sharpsl_fatal_check() < 0) )
-	{
+	if ((!sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_LOCK)) ||
+	    (!sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_FATAL)))	{
 		dev_err(sharpsl_pm.dev, "Fatal condition. Suspend.\n");
 		corgi_goto_sleep(alarm_time, alarm_enable, state);
 		return 1;
diff --git a/arch/arm/mm/highmem.c b/arch/arm/mm/highmem.c
index a34954d9df7d..73cae57fa707 100644
--- a/arch/arm/mm/highmem.c
+++ b/arch/arm/mm/highmem.c
@@ -40,11 +40,16 @@ void *kmap_atomic(struct page *page, enum km_type type)
 {
 	unsigned int idx;
 	unsigned long vaddr;
+	void *kmap;
 
 	pagefault_disable();
 	if (!PageHighMem(page))
 		return page_address(page);
 
+	kmap = kmap_high_get(page);
+	if (kmap)
+		return kmap;
+
 	idx = type + KM_TYPE_NR * smp_processor_id();
 	vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx);
 #ifdef CONFIG_DEBUG_HIGHMEM
@@ -80,6 +85,9 @@ void kunmap_atomic(void *kvaddr, enum km_type type)
 #else
 		(void) idx;  /* to kill a warning */
 #endif
+	} else if (vaddr >= PKMAP_ADDR(0) && vaddr < PKMAP_ADDR(LAST_PKMAP)) {
+		/* this address was obtained through kmap_high_get() */
+		kunmap_high(pte_page(pkmap_page_table[PKMAP_NR(vaddr)]));
 	}
 	pagefault_enable();
 }
diff --git a/arch/arm/plat-mxc/clock.c b/arch/arm/plat-mxc/clock.c
index d2b51a1357c1..911908164efb 100644
--- a/arch/arm/plat-mxc/clock.c
+++ b/arch/arm/plat-mxc/clock.c
@@ -4,7 +4,7 @@
  * Copyright (C) 2004 - 2005 Nokia corporation
  * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
  * Modified for omap shared clock framework by Tony Lindgren <tony@atomide.com>
- * Copyright 2007-2010 Freescale Semiconductor, Inc.
+ * Copyright 2007-2010 Freescale Semiconductor, Inc. All Rights Reserved.
  * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
  *
  * This program is free software; you can redistribute it and/or
@@ -173,8 +173,14 @@ int clk_enable(struct clk *clk)
 	if (clk == NULL || IS_ERR(clk))
 		return -EINVAL;
 
+	spin_lock_irqsave(&clockfw_lock, flags);
+
+	ret = __clk_enable(clk);
+
+	spin_unlock_irqrestore(&clockfw_lock, flags);
+
 	if ((clk->flags & CPU_FREQ_TRIG_UPDATE)
-			&& (clk_get_usecount(clk) == 0)) {
+			&& (clk_get_usecount(clk) == 1)) {
 #if (defined(CONFIG_ARCH_MX5) || defined(CONFIG_ARCH_MX37))
 		if (low_freq_bus_used() && !low_bus_freq_mode)
 			set_low_bus_freq();
@@ -194,13 +200,6 @@ int clk_enable(struct clk *clk)
 #endif
 	}
 
-
-	spin_lock_irqsave(&clockfw_lock, flags);
-
-	ret = __clk_enable(clk);
-
-	spin_unlock_irqrestore(&clockfw_lock, flags);
-
 	return ret;
 }
 EXPORT_SYMBOL(clk_enable);
@@ -229,12 +228,12 @@ void clk_disable(struct clk *clk)
 			set_low_bus_freq();
 		else {
 			if (!high_bus_freq_mode) {
-				/* Currently at low or medium set point,
+				/* Currently at ow or medium set point,
 				  * need to set to high setpoint
 				  */
 				set_high_bus_freq(0);
 			} else if (high_bus_freq_mode || low_bus_freq_mode) {
-				/* Currently at low or high set point,
+				/* Currently at ow or high set point,
 				  * need to set to medium setpoint
 				  */
 				set_high_bus_freq(0);
diff --git a/arch/arm/plat-mxc/dvfs_core.c b/arch/arm/plat-mxc/dvfs_core.c
index 143bc07834ed..adb2b1803fc4 100644
--- a/arch/arm/plat-mxc/dvfs_core.c
+++ b/arch/arm/plat-mxc/dvfs_core.c
@@ -188,14 +188,14 @@ static int set_cpu_freq(int wp)
 		}
 		spin_lock_irqsave(&mxc_dvfs_core_lock, flags);
 		/* PLL_RELOCK, set ARM_FREQ_SHIFT_DIVIDER */
-		reg = __raw_readl(ccm_base + dvfs_data->ccm_cdcr_offset);
+		reg = __raw_readl(dvfs_data->ccm_cdcr_reg_addr);
 		reg &= 0xFFFFFFFB;
-		__raw_writel(reg, ccm_base + dvfs_data->ccm_cdcr_offset);
+		__raw_writel(reg, dvfs_data->ccm_cdcr_reg_addr);
 
 		setup_pll();
 		/* START the GPC main control FSM */
 		/* set VINC */
-		reg = __raw_readl(gpc_base + dvfs_data->gpc_vcr_offset);
+		reg = __raw_readl(dvfs_data->gpc_vcr_reg_addr);
 		reg &= ~(MXC_GPCVCR_VINC_MASK | MXC_GPCVCR_VCNTU_MASK |
 			 MXC_GPCVCR_VCNT_MASK);
 
@@ -204,18 +204,17 @@ static int set_cpu_freq(int wp)
 
 		reg |= (1 << MXC_GPCVCR_VCNTU_OFFSET) |
 		       (1 << MXC_GPCVCR_VCNT_OFFSET);
-		__raw_writel(reg, gpc_base + dvfs_data->gpc_vcr_offset);
+		__raw_writel(reg, dvfs_data->gpc_vcr_reg_addr);
 
-		reg = __raw_readl(gpc_base + dvfs_data->gpc_cntr_offset);
+		reg = __raw_readl(dvfs_data->gpc_cntr_reg_addr);
 		reg &= ~(MXC_GPCCNTR_ADU_MASK | MXC_GPCCNTR_FUPD_MASK);
 		reg |= MXC_GPCCNTR_FUPD;
 		reg |= MXC_GPCCNTR_ADU;
-		__raw_writel(reg, gpc_base + dvfs_data->gpc_cntr_offset);
+		__raw_writel(reg, dvfs_data->gpc_cntr_reg_addr);
 
 		reg |= MXC_GPCCNTR_STRT;
-		__raw_writel(reg, gpc_base + dvfs_data->gpc_cntr_offset);
-		while (__raw_readl(gpc_base + dvfs_data->gpc_cntr_offset)
-				& 0x4000)
+		__raw_writel(reg, dvfs_data->gpc_cntr_reg_addr);
+		while (__raw_readl(dvfs_data->gpc_cntr_reg_addr) & 0x4000)
 			udelay(10);
 		spin_unlock_irqrestore(&mxc_dvfs_core_lock, flags);
 
@@ -236,13 +235,13 @@ static int set_cpu_freq(int wp)
 
 		/* Change arm_podf only */
 		/* set ARM_FREQ_SHIFT_DIVIDER */
-		reg = __raw_readl(ccm_base + dvfs_data->ccm_cdcr_offset);
+		reg = __raw_readl(dvfs_data->ccm_cdcr_reg_addr);
 		reg &= 0xFFFFFFFB;
 		reg |= 1 << 2;
-		__raw_writel(reg, ccm_base + dvfs_data->ccm_cdcr_offset);
+		__raw_writel(reg, dvfs_data->ccm_cdcr_reg_addr);
 
 		/* Get ARM_PODF */
-		reg = __raw_readl(ccm_base + dvfs_data->ccm_cacrr_offset);
+		reg = __raw_readl(dvfs_data->ccm_cacrr_reg_addr);
 		arm_podf = reg & 0x07;
 		if (podf == arm_podf) {
 			printk(KERN_DEBUG
@@ -270,38 +269,37 @@ static int set_cpu_freq(int wp)
 		reg &= 0xFFFFFFF8;
 		reg |= arm_podf;
 
-		reg1 = __raw_readl(ccm_base + dvfs_data->ccm_cdhipr_offset);
+		reg1 = __raw_readl(dvfs_data->ccm_cdhipr_reg_addr);
 		if ((reg1 & 0x00010000) == 0)
-			__raw_writel(reg,
-				ccm_base + dvfs_data->ccm_cacrr_offset);
+			__raw_writel(reg, dvfs_data->ccm_cacrr_reg_addr);
 		else {
 			printk(KERN_DEBUG "ARM_PODF still in busy!!!!\n");
 			return 0;
 		}
 
 		/* START the GPC main control FSM */
-		reg = __raw_readl(gpc_base + dvfs_data->gpc_cntr_offset);
+		reg = __raw_readl(dvfs_data->gpc_cntr_reg_addr);
 		reg |= MXC_GPCCNTR_FUPD;
 		/* ADU=1, select ARM domain */
 		reg |= MXC_GPCCNTR_ADU;
-		__raw_writel(reg, gpc_base + dvfs_data->gpc_cntr_offset);
+		__raw_writel(reg, dvfs_data->gpc_cntr_reg_addr);
 		/* set VINC */
-		reg = __raw_readl(gpc_base + dvfs_data->gpc_vcr_offset);
+		reg = __raw_readl(dvfs_data->gpc_vcr_reg_addr);
 		reg &=
 		    ~(MXC_GPCVCR_VINC_MASK | MXC_GPCVCR_VCNTU_MASK |
 		      MXC_GPCVCR_VCNT_MASK);
 		reg |= (1 << MXC_GPCVCR_VCNTU_OFFSET) |
 		    (100 << MXC_GPCVCR_VCNT_OFFSET) |
 		    (vinc << MXC_GPCVCR_VINC_OFFSET);
-		__raw_writel(reg, gpc_base + dvfs_data->gpc_vcr_offset);
+		__raw_writel(reg, dvfs_data->gpc_vcr_reg_addr);
 
-		reg = __raw_readl(gpc_base + dvfs_data->gpc_cntr_offset);
+		reg = __raw_readl(dvfs_data->gpc_cntr_reg_addr);
 		reg &= (~(MXC_GPCCNTR_ADU | MXC_GPCCNTR_FUPD));
 		reg |= MXC_GPCCNTR_ADU | MXC_GPCCNTR_FUPD | MXC_GPCCNTR_STRT;
-		__raw_writel(reg, gpc_base + dvfs_data->gpc_cntr_offset);
+		__raw_writel(reg, dvfs_data->gpc_cntr_reg_addr);
 
 		/* Wait for arm podf Enable */
-		while ((__raw_readl(gpc_base + dvfs_data->gpc_cntr_offset) &
+		while ((__raw_readl(dvfs_data->gpc_cntr_reg_addr) &
 			MXC_GPCCNTR_STRT) == MXC_GPCCNTR_STRT) {
 			printk(KERN_DEBUG "Waiting arm_podf enabled!\n");
 			udelay(10);
@@ -320,9 +318,9 @@ static int set_cpu_freq(int wp)
 
 		propagate_rate(pll1_sw_clk);
 		/* Clear the ARM_FREQ_SHIFT_DIVIDER */
-		reg = __raw_readl(ccm_base + dvfs_data->ccm_cdcr_offset);
+		reg = __raw_readl(dvfs_data->ccm_cdcr_reg_addr);
 		reg &= 0xFFFFFFFB;
-		__raw_writel(reg, ccm_base + dvfs_data->ccm_cdcr_offset);
+		__raw_writel(reg, dvfs_data->ccm_cdcr_reg_addr);
 	}
 #if defined(CONFIG_CPU_FREQ_IMX)
 		cpufreq_trig_needed = 1;
@@ -347,14 +345,14 @@ static int start_dvfs(void)
 	dvfs_load_config(0);
 
 	/* config reg GPC_CNTR */
-	reg = __raw_readl(gpc_base + dvfs_data->gpc_cntr_offset);
+	reg = __raw_readl(dvfs_data->gpc_cntr_reg_addr);
 
 	reg &= ~MXC_GPCCNTR_GPCIRQM;
 	/* GPCIRQ=1, select ARM IRQ */
 	reg |= MXC_GPCCNTR_GPCIRQ_ARM;
 	/* ADU=1, select ARM domain */
 	reg |= MXC_GPCCNTR_ADU;
-	__raw_writel(reg, gpc_base + dvfs_data->gpc_cntr_offset);
+	__raw_writel(reg, dvfs_data->gpc_cntr_reg_addr);
 
 	/* Set PREDIV bits */
 	reg = __raw_readl(dvfs_data->membase + MXC_DVFSCORE_CNTR);
@@ -419,8 +417,8 @@ static irqreturn_t dvfs_irq(int irq, void *dev_id)
 	u32 reg;
 
 	/* Check if DVFS0 (ARM) id requesting for freqency/voltage update */
-	if ((__raw_readl(gpc_base + dvfs_data->gpc_cntr_offset)
-			& MXC_GPCCNTR_DVFS0CR) == 0)
+	if ((__raw_readl(dvfs_data->gpc_cntr_reg_addr) & MXC_GPCCNTR_DVFS0CR) ==
+	    0)
 		return IRQ_NONE;
 
 	/* Mask DVFS irq */
@@ -430,9 +428,9 @@ static irqreturn_t dvfs_irq(int irq, void *dev_id)
 	__raw_writel(reg, dvfs_data->membase + MXC_DVFSCORE_CNTR);
 
 	/* Mask GPC1 irq */
-	reg = __raw_readl(gpc_base + dvfs_data->gpc_cntr_offset);
+	reg = __raw_readl(dvfs_data->gpc_cntr_reg_addr);
 	reg |= MXC_GPCCNTR_GPCIRQM | 0x1000000;
-	__raw_writel(reg, gpc_base + dvfs_data->gpc_cntr_offset);
+	__raw_writel(reg, dvfs_data->gpc_cntr_reg_addr);
 
 	schedule_delayed_work(&dvfs_core_handler, 0);
 	return IRQ_HANDLED;
@@ -537,9 +535,9 @@ END:	/* Set MAXF, MINF */
 	reg |= MXC_DVFSCNTR_LBFL;
 	__raw_writel(reg, dvfs_data->membase + MXC_DVFSCORE_CNTR);
 	/*Unmask GPC1 IRQ */
-	reg = __raw_readl(gpc_base + dvfs_data->gpc_cntr_offset);
+	reg = __raw_readl(dvfs_data->gpc_cntr_reg_addr);
 	reg &= ~MXC_GPCCNTR_GPCIRQM;
-	__raw_writel(reg, gpc_base + dvfs_data->gpc_cntr_offset);
+	__raw_writel(reg, dvfs_data->gpc_cntr_reg_addr);
 
 #if defined(CONFIG_CPU_FREQ_IMX)
 	if (cpufreq_trig_needed == 1) {
@@ -804,6 +802,7 @@ static int __devinit mxc_dvfs_core_probe(struct platform_device *pdev)
 		goto err1;
 	}
 	dvfs_data->membase = ioremap(res->start, res->end - res->start + 1);
+
 	/*
 	 * Request the DVFS interrupt
 	 */
@@ -950,7 +949,6 @@ static void __exit dvfs_cleanup(void)
 	/* Unregister the device structure */
 	platform_driver_unregister(&mxc_dvfs_core_driver);
 
-	iounmap(ccm_base);
 	iounmap(dvfs_data->membase);
 	clk_put(cpu_clk);
 	clk_put(dvfs_clk);
diff --git a/arch/arm/plat-mxc/include/mach/iomux-v3.h b/arch/arm/plat-mxc/include/mach/iomux-v3.h
index 6beaf8cd69b5..7cd84547658f 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-v3.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-v3.h
@@ -68,31 +68,33 @@ struct pad_desc {
 /*
  * Use to set PAD control
  */
+#define PAD_CTL_DRIVE_VOLTAGE_3_3_V	0
+#define PAD_CTL_DRIVE_VOLTAGE_1_8_V	1
 
-#define PAD_CTL_DVS			(1 << 13)
-#define PAD_CTL_HYS			(1 << 8)
+#define PAD_CTL_NO_HYSTERESIS		0
+#define PAD_CTL_HYSTERESIS		1
 
-#define PAD_CTL_PKE			(1 << 7)
-#define PAD_CTL_PUE			(1 << 6)
-#define PAD_CTL_PUS_100K_DOWN		(0 << 4)
-#define PAD_CTL_PUS_360K_DOWN		(0 << 4)
-#define PAD_CTL_PUS_47K_UP		(1 << 4)
-#define PAD_CTL_PUS_75K_UP		(1 << 4)
-#define PAD_CTL_PUS_100K_UP		(2 << 4)
-#define PAD_CTL_PUS_22K_UP		(3 << 4)
+#define PAD_CTL_PULL_DISABLED		0x0
+#define PAD_CTL_PULL_KEEPER		0xa
+#define PAD_CTL_PULL_DOWN_100K		0xc
+#define PAD_CTL_PULL_UP_47K		0xd
+#define PAD_CTL_PULL_UP_100K		0xe
+#define PAD_CTL_PULL_UP_22K		0xf
 
-#define PAD_CTL_ODE			(1 << 3)
+#define PAD_CTL_OUTPUT_CMOS		0
+#define PAD_CTL_OUTPUT_OPEN_DRAIN	1
 
-#define PAD_CTL_DSE_LOW			(0 << 1)
-#define PAD_CTL_DSE_MED			(1 << 1)
-#define PAD_CTL_DSE_HIGH		(2 << 1)
-#define PAD_CTL_DSE_MAX			(3 << 1)
+#define PAD_CTL_DRIVE_STRENGTH_NORM	0
+#define PAD_CTL_DRIVE_STRENGTH_HIGH	1
+#define PAD_CTL_DRIVE_STRENGTH_MAX	2
 
-#define PAD_CTL_SRE_FAST		(1 << 0)
-#define PAD_CTL_SRE_SLOW		(0 << 0)
+#define PAD_CTL_SLEW_RATE_SLOW		0
+#define PAD_CTL_SLEW_RATE_FAST		1
 
 /*
- * setups a single pad in the iomuxer
+ * setups a single pad:
+ * 	- reserves the pad so that it is not claimed by another driver
+ * 	- setups the iomux according to the configuration
  */
 int mxc_iomux_v3_setup_pad(struct pad_desc *pad);
 
@@ -103,9 +105,17 @@ int mxc_iomux_v3_setup_pad(struct pad_desc *pad);
 int mxc_iomux_v3_setup_multiple_pads(struct pad_desc *pad_list, unsigned count);
 
 /*
- * Initialise the iomux controller
+ * releases a single pad:
+ * 	- make it available for a future use by another driver
+ * 	- DOES NOT reconfigure the IOMUX in its reset state
  */
-void mxc_iomux_v3_init(void __iomem *iomux_v3_base);
+void mxc_iomux_v3_release_pad(struct pad_desc *pad);
+
+/*
+ * releases multiple pads
+ * convenvient way to call the above function with tables
+ */
+void mxc_iomux_v3_release_multiple_pads(struct pad_desc *pad_list, int count);
 
 #endif /* __MACH_IOMUX_V3_H__*/
 
diff --git a/arch/arm/plat-mxc/include/mach/mmc.h b/arch/arm/plat-mxc/include/mach/mmc.h
index 7be75bd5756e..d563c157bad7 100644
--- a/arch/arm/plat-mxc/include/mach/mmc.h
+++ b/arch/arm/plat-mxc/include/mach/mmc.h
@@ -40,9 +40,6 @@ struct mxc_mmc_platform_data {
 	unsigned int min_clk;
 	unsigned int max_clk;
 	unsigned int clk_flg;	/* 1 clock enable, 0 not */
-	unsigned int clk_always_on;     /* Needed by SDIO cards and etc */
-	unsigned int dll_override_en;	/* Enable dll override delay line */
-	unsigned int dll_delay_cells;	/* The number of delay cells (0-0x3f) */
 	unsigned int reserved:16;
 	unsigned int card_fixed:1;
 	unsigned int card_inserted_state:1;
diff --git a/arch/arm/plat-mxc/include/mach/mx5x.h b/arch/arm/plat-mxc/include/mach/mx5x.h
index 0e25133736d2..fd3bbefdd292 100644
--- a/arch/arm/plat-mxc/include/mach/mx5x.h
+++ b/arch/arm/plat-mxc/include/mach/mx5x.h
@@ -134,31 +134,6 @@
  */
 #define MX53_SATA_BASE_ADDR 		0x10000000
 
-/*
- * Databahn MX50
- */
-#define MX50_DATABAHN_BASE_ADDR		0x14000000
-#define DATABAHN_CTL_REG19			0x4c
-#define DATABAHN_CTL_REG20			0x50
-#define DATABAHN_CTL_REG21			0x54
-#define DATABAHN_CTL_REG22			0x58
-#define DATABAHN_CTL_REG23			0x5c
-#define DATABAHN_CTL_REG42			0xa8
-#define DATABAHN_CTL_REG43			0xac
-#define DATABAHN_CTL_REG55			0xdc
-#define DATABAHN_CTL_REG63			0xFC
-#define LOWPOWER_CONTROL_MASK	 	0x1F
-#define LOWPOWER_AUTOENABLE_MASK 		0x1F
-#define LOWPOWER_EXTERNAL_CNT_MASK		(0xFFFF << 16)
-#define LOWPOWER_EXTERNAL_CNT_OFFSET	16
-#define LOWPOWER_INTERNAL_CNT_MASK		(0xFFFF << 8)
-#define LOWPOWER_INTERNAL_CNT_OFFSET	8
-#define LOWPOWER_REFRESH_ENABLE_MASK	(3 << 16)
-#define LOWPOWER_REFRESH_ENABLE_OFFSET	16
-#define LOWPOWER_REFRESH_HOLD_MASK		0xFFFF
-#define LOWPOWER_REFRESH_HOLD_OFFSET	0
-
-
 #define DEBUG_BASE_ADDR	0x40000000
 /*MX53 + 0x2000000 */
 #define DEBUG_SIZE		SZ_1M
@@ -171,7 +146,7 @@
 #define CTI3_BASE_ADDR		(DEBUG_BASE_ADDR + 0x00007000)
 #define CORTEX_DBG_BASE_ADDR	(DEBUG_BASE_ADDR + 0x00008000)
 
-#define APBHDMA_BASE_ADDR	(DEBUG_BASE_ADDR + 0x01000000)
+#define ABPHDMA_BASE_ADDR	 (DEBUG_BASE_ADDR + 0x01000000)
 #define OCOTP_CTRL_BASE_ADDR	(DEBUG_BASE_ADDR + 0x01002000)
 #define DIGCTL_BASE_ADDR	(DEBUG_BASE_ADDR + 0x01004000)
 #define GPMI_BASE_ADDR		(DEBUG_BASE_ADDR + 0x01006000)
@@ -262,7 +237,6 @@
 #define MX53_ATA_BASE_ADDR	(AIPS1_BASE_ADDR + 0x000E8000)
 #define I2C3_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000EC000)
 #define UART4_BASE_ADDR	(AIPS1_BASE_ADDR + 0x000F0000)
-#define RNGB_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000F8000) /* MX50 */
 
 #define DVFSCORE_BASE_ADDR 	(GPC_BASE_ADDR + 0x180)
 #define DVFSPER_BASE_ADDR 		(GPC_BASE_ADDR + 0x1C4)
diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h
index 808adf67552d..fc466b1c76c3 100644
--- a/arch/arm/plat-mxc/include/mach/mxc.h
+++ b/arch/arm/plat-mxc/include/mach/mxc.h
@@ -235,7 +235,6 @@ struct mxc_ipu_config {
 	int rev;
 	void (*reset) (void);
 	struct clk *di_clk[2];
-	struct clk *csi_clk[2];
 };
 
 struct mxc_ir_platform_data {
@@ -326,29 +325,6 @@ struct ccwmx51_lcd_pdata {
 	void (*bl_enable) (int, int);
 };
 
-struct mxc_epdc_fb_mode {
-	struct fb_videomode *vmode;
-	int vscan_holdoff;
-	int sdoed_width;
-	int sdoed_delay;
-	int sdoez_width;
-	int sdoez_delay;
-	int gdclk_hp_offs;
-	int gdsp_offs;
-	int gdoe_offs;
-	int gdclk_offs;
-	int num_ce;
-};
-
-struct mxc_epdc_fb_platform_data {
-	struct mxc_epdc_fb_mode *epdc_mode;
-	int num_modes;
-	void (*get_pins) (void);
-	void (*put_pins) (void);
-	void (*enable_pins) (void);
-	void (*disable_pins) (void);
-};
-
 struct mxc_tsc_platform_data {
 	char *vdd_reg;
 	int penup_threshold;
@@ -634,18 +610,6 @@ struct mxc_sim_platform_data {
 	unsigned int detect; /* 1 have detect pin, 0 not */
 };
 
-struct fsl_otp_data {
-	char 		**fuse_name;
-	char		*regulator_name;
-	unsigned int 	fuse_num;
-};
-
-struct mxs_dma_plat_data {
-	unsigned int burst8:1;
-	unsigned int burst:1;
-	unsigned int chan_base;
-	unsigned int chan_num;
-};
 #endif				/* __ASSEMBLY__ */
 
 #define MUX_IO_P		29
diff --git a/arch/arm/plat-mxc/include/mach/mxc_dvfs.h b/arch/arm/plat-mxc/include/mach/mxc_dvfs.h
index 05c6ea4bda77..43bcd2f7043a 100644
--- a/arch/arm/plat-mxc/include/mach/mxc_dvfs.h
+++ b/arch/arm/plat-mxc/include/mach/mxc_dvfs.h
@@ -35,7 +35,6 @@
 #include <linux/device.h>
 
 extern void __iomem *gpc_base;
-extern void __iomem *ccm_base;
 
 #define MXC_GPCCNTR_GPCIRQ2M		(1 << 25)
 #define MXC_GPCCNTR_GPCIRQ2		(1 << 24)
@@ -144,16 +143,16 @@ struct mxc_dvfs_platform_data {
 	void __iomem *membase;
 	/* The interrupt number used by the DVFS core */
 	int irq;
-	/* GPC control reg offset */
-	int gpc_cntr_offset;
-	/* GPC voltage counter reg offset */
-	int gpc_vcr_offset;
-	/* CCM DVFS control reg offset */
-	int ccm_cdcr_offset;
-	/* CCM ARM clock root reg offset */
-	int ccm_cacrr_offset;
-	/* CCM divider handshake in-progress reg offset */
-	int ccm_cdhipr_offset;
+	/* GPC control reg address */
+	void __iomem *gpc_cntr_reg_addr;
+	/* GPC voltage counter reg address */
+	void __iomem *gpc_vcr_reg_addr;
+	/* CCM DVFS control reg address */
+	void __iomem *ccm_cdcr_reg_addr;
+	/* CCM ARM clock root reg address */
+	void __iomem *ccm_cacrr_reg_addr;
+	/* CCM divider handshake in-progree reg address */
+	void __iomem *ccm_cdhipr_reg_addr;
 	/* PREDIV mask */
 	u32 prediv_mask;
 	/* PREDIV offset */
diff --git a/arch/arm/plat-mxc/include/mach/system.h b/arch/arm/plat-mxc/include/mach/system.h
index 604abbc77da0..126bc8713159 100644
--- a/arch/arm/plat-mxc/include/mach/system.h
+++ b/arch/arm/plat-mxc/include/mach/system.h
@@ -1,7 +1,7 @@
 /*
  *  Copyright (C) 1999 ARM Limited
  *  Copyright (C) 2000 Deep Blue Solutions Ltd
- *  Copyright 2004-2010 Freescale Semiconductor, Inc.
+ *  Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -24,6 +24,5 @@
 extern void arch_idle(void);
 
 void arch_reset(char mode, const char *cmd);
-int mxs_reset_block(void __iomem *hwreg, int just_enable);
 
 #endif /* __ASM_ARCH_MXC_SYSTEM_H__ */
diff --git a/arch/arm/plat-mxc/iomux-v3.c b/arch/arm/plat-mxc/iomux-v3.c
index b318c6a222d5..77a078f9513f 100644
--- a/arch/arm/plat-mxc/iomux-v3.c
+++ b/arch/arm/plat-mxc/iomux-v3.c
@@ -29,22 +29,30 @@
 #include <asm/mach/map.h>
 #include <mach/iomux-v3.h>
 
-static void __iomem *base;
+#define IOMUX_BASE	IO_ADDRESS(IOMUXC_BASE_ADDR)
+
+static unsigned long iomux_v3_pad_alloc_map[0x200 / BITS_PER_LONG];
 
 /*
- * setups a single pad in the iomuxer
+ * setups a single pin:
+ * 	- reserves the pin so that it is not claimed by another driver
+ * 	- setups the iomux according to the configuration
  */
 int mxc_iomux_v3_setup_pad(struct pad_desc *pad)
 {
+	unsigned int pad_ofs = pad->pad_ctrl_ofs;
+
+	if (test_and_set_bit(pad_ofs >> 2, iomux_v3_pad_alloc_map))
+		return -EBUSY;
 	if (pad->mux_ctrl_ofs)
-		__raw_writel(pad->mux_mode, base + pad->mux_ctrl_ofs);
+		__raw_writel(pad->mux_mode, IOMUX_BASE + pad->mux_ctrl_ofs);
 
 	if (pad->select_input_ofs)
 		__raw_writel(pad->select_input,
-				base + pad->select_input_ofs);
+				IOMUX_BASE + pad->select_input_ofs);
 
-	if (!(pad->pad_ctrl & NO_PAD_CTRL) && pad->pad_ctrl_ofs)
-		__raw_writel(pad->pad_ctrl, base + pad->pad_ctrl_ofs);
+	if (!(pad->pad_ctrl & NO_PAD_CTRL))
+		__raw_writel(pad->pad_ctrl, IOMUX_BASE + pad->pad_ctrl_ofs);
 	return 0;
 }
 EXPORT_SYMBOL(mxc_iomux_v3_setup_pad);
@@ -58,14 +66,33 @@ int mxc_iomux_v3_setup_multiple_pads(struct pad_desc *pad_list, unsigned count)
 	for (i = 0; i < count; i++) {
 		ret = mxc_iomux_v3_setup_pad(p);
 		if (ret)
-			return ret;
+			goto setup_error;
 		p++;
 	}
 	return 0;
+
+setup_error:
+	mxc_iomux_v3_release_multiple_pads(pad_list, i);
+	return ret;
 }
 EXPORT_SYMBOL(mxc_iomux_v3_setup_multiple_pads);
 
-void mxc_iomux_v3_init(void __iomem *iomux_v3_base)
+void mxc_iomux_v3_release_pad(struct pad_desc *pad)
+{
+	unsigned int pad_ofs = pad->pad_ctrl_ofs;
+
+	clear_bit(pad_ofs >> 2, iomux_v3_pad_alloc_map);
+}
+EXPORT_SYMBOL(mxc_iomux_v3_release_pad);
+
+void mxc_iomux_v3_release_multiple_pads(struct pad_desc *pad_list, int count)
 {
-	base = iomux_v3_base;
+	struct pad_desc *p = pad_list;
+	int i;
+
+	for (i = 0; i < count; i++) {
+		mxc_iomux_v3_release_pad(p);
+		p++;
+	}
 }
+EXPORT_SYMBOL(mxc_iomux_v3_release_multiple_pads);
diff --git a/arch/arm/plat-mxc/usb_common.c b/arch/arm/plat-mxc/usb_common.c
index 71583e465046..af4cf8dc7d98 100644
--- a/arch/arm/plat-mxc/usb_common.c
+++ b/arch/arm/plat-mxc/usb_common.c
@@ -432,7 +432,14 @@ static int usb_register_remote_wakeup(struct platform_device *pdev)
 	int irq;
 
 	pr_debug("%s: pdev=0x%p \n", __func__, pdev);
-	if (!(pdata->wake_up_enable))
+	if (!cpu_is_mx51() && !cpu_is_mx25())
+		return -ECANCELED;
+
+	/* The Host2 USB controller On mx25 platform
+	 * is no path available from internal USB FS
+	 * PHY to FS PHY wake up interrupt, So to
+	 * remove the function of USB Remote Wakeup on Host2 */
+	if (cpu_is_mx25() && (!strcmp("Host 2", pdata->name)))
 		return -ECANCELED;
 
 	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
@@ -800,9 +807,9 @@ int usbotg_init(struct platform_device *pdev)
 	pdata->xcvr_type = xops->xcvr_type;
 	pdata->pdev = pdev;
 
-	if (fsl_check_usbclk() != 0)
-		return -EINVAL;
 	if (!otg_used) {
+		if (fsl_check_usbclk() != 0)
+			return -EINVAL;
 		if (cpu_is_mx50())
 			/* Turn on AHB CLK for OTG*/
 			USB_CLKONOFF_CTRL &= ~OTG_AHBCLK_OFF;
@@ -881,8 +888,8 @@ int usb_host_wakeup_irq(struct device *wkup_dev)
 		wakeup_req = USBCTRL & UCTRL_H1WIR;
 	} else if (!strcmp("DR", pdata->name)) {
 		wakeup_req = USBCTRL & UCTRL_OWIR;
-		/* If not ID wakeup, let udc handle it */
-		if (wakeup_req && (UOG_OTGSC & OTGSC_STS_USB_ID))
+		/* If DR is in device mode, let udc handle it */
+		if (wakeup_req && ((UOG_USBMODE & 0x3) == 0x2))
 			wakeup_req = 0;
 	}
 
diff --git a/arch/arm/plat-mxs/device.c b/arch/arm/plat-mxs/device.c
index e3783d3fe87d..027408950382 100644
--- a/arch/arm/plat-mxs/device.c
+++ b/arch/arm/plat-mxs/device.c
@@ -485,16 +485,6 @@ static struct platform_device mxs_persistent = {
 };
 #endif
 
-#ifdef CONFIG_FSL_OTP
-static struct platform_device otp_device = {
-	.name			= "ocotp",
-	.id			= 0,
-	.dev = {
-		.release = mxs_nop_release,
-		},
-};
-#endif
-
 static inline void mxs_init_busfreq(void)
 {
 	(void)platform_device_register(&busfreq_device);
@@ -576,14 +566,6 @@ static struct mxs_dev_lookup dev_lookup[] = {
 	},
 #endif
 
-#if defined(CONFIG_FSL_OTP)
-	{
-	.name = "ocotp",
-	.size = 1,
-	.pdev = &otp_device,
-	},
-#endif
-
 #if defined(CONFIG_FB_MXS) || defined(CONFIG_FB_MXS_MODULE)
 	{
 	 .name	= "mxs-fb",
diff --git a/arch/arm/plat-mxs/dma-apbx.c b/arch/arm/plat-mxs/dma-apbx.c
index 6d77a6933d98..c27414f8c18d 100644
--- a/arch/arm/plat-mxs/dma-apbx.c
+++ b/arch/arm/plat-mxs/dma-apbx.c
@@ -99,9 +99,6 @@ static void mxs_dma_apbx_info(struct mxs_dma_device *pdev,
 	reg = __raw_readl(pdev->base + HW_APBX_CTRL2);
 	info->status = reg >> chan;
 	info->buf_addr = __raw_readl(pdev->base + HW_APBX_CHn_BAR(chan));
-	reg = __raw_readl(pdev->base + HW_APBX_CHn_CMD(chan));
-	info->xfer_count = (reg & BM_APBX_CHn_CMD_XFER_COUNT) >> \
-		BP_APBX_CHn_CMD_XFER_COUNT;
 }
 
 static int
diff --git a/arch/arm/plat-mxs/dmaengine.c b/arch/arm/plat-mxs/dmaengine.c
index 0c2485b18506..52330d3ea9e3 100644
--- a/arch/arm/plat-mxs/dmaengine.c
+++ b/arch/arm/plat-mxs/dmaengine.c
@@ -127,16 +127,14 @@ int mxs_dma_enable(int channel)
 	if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED))
 		return -EINVAL;
 
-	/*
-	 *  neednot mutex lock, this function will be called in irq context.
-	 *  The mutex may cause process schedule.
-	 */
 	pdma = pchan->dma;
+	mutex_lock(&mxs_dma_mutex);
 	spin_lock_irqsave(&pchan->lock, flags);
 	if (pchan->pending_num && pdma->enable)
 		ret = pdma->enable(pchan, channel - pdma->chan_base);
 	pchan->flags |= MXS_DMA_FLAGS_BUSY;
 	spin_unlock_irqrestore(&pchan->lock, flags);
+	mutex_unlock(&mxs_dma_mutex);
 	return ret;
 }
 EXPORT_SYMBOL(mxs_dma_enable);
@@ -153,11 +151,8 @@ void mxs_dma_disable(int channel)
 		return;
 	if (!(pchan->flags & MXS_DMA_FLAGS_BUSY))
 		return;
-	/*
-	 *  neednot mutex lock, this function will be called in irq context.
-	 *  The mutex may cause process schedule.
-	 */
 	pdma = pchan->dma;
+	mutex_lock(&mxs_dma_mutex);
 	spin_lock_irqsave(&pchan->lock, flags);
 	if (pdma->disable)
 		pdma->disable(pchan, channel - pdma->chan_base);
@@ -166,6 +161,7 @@ void mxs_dma_disable(int channel)
 	pchan->pending_num = 0;
 	list_splice_init(&pchan->active, &pchan->done);
 	spin_unlock_irqrestore(&pchan->lock, flags);
+	mutex_unlock(&mxs_dma_mutex);
 }
 EXPORT_SYMBOL(mxs_dma_disable);
 
diff --git a/arch/arm/plat-mxs/include/mach/device.h b/arch/arm/plat-mxs/include/mach/device.h
index 199ec1e62963..9598ccdaa718 100644
--- a/arch/arm/plat-mxs/include/mach/device.h
+++ b/arch/arm/plat-mxs/include/mach/device.h
@@ -54,12 +54,6 @@ struct mxs_dma_plat_data {
 	unsigned int chan_num;
 };
 
-struct fsl_otp_data {
-	char 		**fuse_name;
-	char		*regulator_name;
-	unsigned int 	fuse_num;
-};
-
 struct mxs_i2c_plat_data {
 	unsigned int pioqueue_mode:1;
 };
diff --git a/arch/arm/plat-mxs/include/mach/dmaengine.h b/arch/arm/plat-mxs/include/mach/dmaengine.h
index cdf6b1e32a43..eecd260ac5b4 100644
--- a/arch/arm/plat-mxs/include/mach/dmaengine.h
+++ b/arch/arm/plat-mxs/include/mach/dmaengine.h
@@ -106,7 +106,6 @@ struct mxs_dma_info {
 #define MXS_DMA_INFO_ERR       0x00000001
 #define MXS_DMA_INFO_ERR_STAT  0x00010000
 	unsigned int buf_addr;
-	unsigned int xfer_count;
 };
 
 /**
diff --git a/arch/arm/plat-mxs/include/mach/timex.h b/arch/arm/plat-mxs/include/mach/timex.h
index d622dda141f2..9db3d688223a 100644
--- a/arch/arm/plat-mxs/include/mach/timex.h
+++ b/arch/arm/plat-mxs/include/mach/timex.h
@@ -20,4 +20,4 @@
 /*
  * System time clock is sourced from the 32k clock
  */
-#define CLOCK_TICK_RATE		32000
+#define CLOCK_TICK_RATE		32768
diff --git a/arch/arm/plat-mxs/timer-nomatch.c b/arch/arm/plat-mxs/timer-nomatch.c
index db8906192f16..66c488c99b42 100644
--- a/arch/arm/plat-mxs/timer-nomatch.c
+++ b/arch/arm/plat-mxs/timer-nomatch.c
@@ -21,7 +21,6 @@
 #include <linux/clocksource.h>
 #include <linux/clockchips.h>
 #include <linux/io.h>
-#include <linux/clk.h>
 #include <linux/irq.h>
 #include <linux/interrupt.h>
 
@@ -120,9 +119,9 @@ void mxs_nomatch_timer_init(struct mxs_sys_timer *timer)
 
 	online_timer = timer;
 
-	cksrc_mxs_nomatch.mult = clocksource_hz2mult(clk_get_rate(timer->clk),
+	cksrc_mxs_nomatch.mult = clocksource_hz2mult(CLOCK_TICK_RATE,
 				cksrc_mxs_nomatch.shift);
-	ckevt_timrot.mult = div_sc(clk_get_rate(timer->clk), NSEC_PER_SEC,
+	ckevt_timrot.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC,
 				ckevt_timrot.shift);
 	ckevt_timrot.min_delta_ns = clockevent_delta2ns(2, &ckevt_timrot);
 	ckevt_timrot.max_delta_ns = clockevent_delta2ns(0xFFF, &ckevt_timrot);
@@ -146,7 +145,7 @@ void mxs_nomatch_timer_init(struct mxs_sys_timer *timer)
 		BM_TIMROT_TIMCTRLn_IRQ_EN,
 			online_timer->base + HW_TIMROT_TIMCTRLn(1));
 
-	__raw_writel(clk_get_rate(timer->clk) / HZ - 1,
+	__raw_writel(CLOCK_TICK_RATE / HZ - 1,
 			online_timer->base + HW_TIMROT_TIMCOUNTn(0));
 	__raw_writel(0xFFFF, online_timer->base + HW_TIMROT_TIMCOUNTn(1));
 
@@ -182,7 +181,7 @@ void mxs_nomatch_resume_timer(void)
 		BM_TIMROT_TIMCTRLn_UPDATE |
 		BM_TIMROT_TIMCTRLn_IRQ_EN,
 			online_timer->base  + HW_TIMROT_TIMCTRLn(1));
-	__raw_writel(clk_get_rate(online_timer->clk) / HZ - 1,
+	__raw_writel(CLOCK_TICK_RATE / HZ - 1,
 			online_timer->base  + HW_TIMROT_TIMCOUNTn(0));
 	__raw_writel(0xFFFF, online_timer->base  + HW_TIMROT_TIMCOUNTn(1));
 }
diff --git a/arch/arm/plat-mxs/usb_common.c b/arch/arm/plat-mxs/usb_common.c
index 23134489472e..5d8d0b6d9285 100644
--- a/arch/arm/plat-mxs/usb_common.c
+++ b/arch/arm/plat-mxs/usb_common.c
@@ -264,16 +264,13 @@ int usbotg_init(struct platform_device *pdev)
 	pdata->xcvr_type = xops->xcvr_type;
 	pdata->pdev = pdev;
 
+	otg_used = 0;
 	if (!otg_used) {
 		pr_debug("%s: grab pins\n", __func__);
 		if (xops->init)
 			xops->init(xops);
 		usb_phy_enable(pdata);
 	}
-	/* Enable internal Phy clock */
-	tmp = __raw_readl(pdata->regs + UOG_PORTSC1);
-	tmp &= ~PORTSC_PHCD;
-	__raw_writel(tmp, pdata->regs + UOG_PORTSC1);
 
 	if (pdata->operating_mode == FSL_USB2_DR_HOST) {
 		/* enable FS/LS device */
@@ -291,22 +288,11 @@ EXPORT_SYMBOL(usbotg_init);
 
 void usbotg_uninit(struct fsl_usb2_platform_data *pdata)
 {
-	int tmp;
-	struct clk *usb_clk;
 	pr_debug("%s\n", __func__);
 
 	if (pdata->xcvr_ops && pdata->xcvr_ops->uninit)
 		pdata->xcvr_ops->uninit(pdata->xcvr_ops);
 
-	/* Disable internal Phy clock */
-	tmp = __raw_readl(pdata->regs + UOG_PORTSC1);
-	tmp |= PORTSC_PHCD;
-	__raw_writel(tmp, pdata->regs + UOG_PORTSC1);
-
-	usb_clk = clk_get(NULL, "usb_clk0");
-	clk_disable(usb_clk);
-	clk_put(usb_clk);
-
 	pdata->regs = NULL;
 	otg_used--;
 }
@@ -345,16 +331,11 @@ EXPORT_SYMBOL(fsl_usb_host_init);
 
 void fsl_usb_host_uninit(struct fsl_usb2_platform_data *pdata)
 {
-	struct clk *usb_clk;
 	pr_debug("%s\n", __func__);
 
 	if (pdata->xcvr_ops && pdata->xcvr_ops->uninit)
 		pdata->xcvr_ops->uninit(pdata->xcvr_ops);
 
-	usb_clk = clk_get(NULL, "usb_clk1");
-	clk_disable(usb_clk);
-	clk_put(usb_clk);
-
 	pdata->regs = NULL;
 }
 EXPORT_SYMBOL(fsl_usb_host_uninit);
diff --git a/arch/arm/plat-mxs/utmixc.c b/arch/arm/plat-mxs/utmixc.c
index 8e842840e87a..8ad6bd4f3654 100644
--- a/arch/arm/plat-mxs/utmixc.c
+++ b/arch/arm/plat-mxs/utmixc.c
@@ -80,7 +80,7 @@ static void __exit utmixc_exit(void)
 #ifdef CONFIG_MXS_VBUS_CURRENT_DRAW
 	fs_initcall(utmixc_init);
 #else
-	subsys_initcall(utmixc_init);
+	module_init(utmixc_init);
 #endif
 module_exit(utmixc_exit);
 
diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types
index 817425c8e732..0fa7f761dd1d 100644
--- a/arch/arm/tools/mach-types
+++ b/arch/arm/tools/mach-types
@@ -2594,7 +2594,6 @@ spacecom1		MACH_SPACECOM1		SPACECOM1		2604
 pingu920		MACH_PINGU920		PINGU920		2605
 bravoc			MACH_BRAVOC		BRAVOC			2606
 cybo2440		MACH_CYBO2440		CYBO2440		2607
-mx50_arm2       MACH_MX50_ARM2          MX50_ARM2               2955
-mx50_rdp		MACH_MX50_RDP		MX50_RDP		2988
+mx50_arm2               MACH_MX50_ARM2          MX50_ARM2               2955
 
 
diff --git a/arch/cris/Makefile b/arch/cris/Makefile
index 71e17d3eeddb..29c2ceb38a76 100644
--- a/arch/cris/Makefile
+++ b/arch/cris/Makefile
@@ -42,8 +42,6 @@ LD = $(CROSS_COMPILE)ld -mcrislinux
 
 OBJCOPYFLAGS := -O binary -R .note -R .comment -S
 
-CPPFLAGS_vmlinux.lds = -DDRAM_VIRTUAL_BASE=0x$(CONFIG_ETRAX_DRAM_VIRTUAL_BASE)
-
 KBUILD_AFLAGS += -mlinux -march=$(arch-y) $(inc)
 KBUILD_CFLAGS += -mlinux -march=$(arch-y) -pipe $(inc)
 KBUILD_CPPFLAGS += $(inc)
diff --git a/arch/cris/kernel/Makefile b/arch/cris/kernel/Makefile
index ee7bcd4d20b2..b45640b3e600 100644
--- a/arch/cris/kernel/Makefile
+++ b/arch/cris/kernel/Makefile
@@ -3,6 +3,7 @@
 # Makefile for the linux kernel.
 #
 
+CPPFLAGS_vmlinux.lds := -DDRAM_VIRTUAL_BASE=0x$(CONFIG_ETRAX_DRAM_VIRTUAL_BASE)
 extra-y	:= vmlinux.lds
 
 obj-y   := process.o traps.o irq.o ptrace.o setup.o time.o sys_cris.o
diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig
index fb87c08c6b57..2de41c051147 100644
--- a/arch/m68k/Kconfig
+++ b/arch/m68k/Kconfig
@@ -555,7 +555,7 @@ config HPAPCI
 
 config MVME147_SCC
 	bool "SCC support for MVME147 serial ports"
-	depends on MVME147
+	depends on MVME147 && BROKEN
 	help
 	  This is the driver for the serial ports on the Motorola MVME147
 	  boards.  Everyone using one of these boards should say Y here.
@@ -570,14 +570,14 @@ config SERIAL167
 
 config MVME162_SCC
 	bool "SCC support for MVME162 serial ports"
-	depends on MVME16x
+	depends on MVME16x && BROKEN
 	help
 	  This is the driver for the serial ports on the Motorola MVME162 and
 	  172 boards.  Everyone using one of these boards should say Y here.
 
 config BVME6000_SCC
 	bool "SCC support for BVME6000 serial ports"
-	depends on BVME6000
+	depends on BVME6000 && BROKEN
 	help
 	  This is the driver for the serial ports on the BVME4000 and BVME6000
 	  boards from BVM Ltd.  Everyone using one of these boards should say
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 861da514a468..7d651d582007 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -615,16 +615,6 @@ endif
 cflags-y			+= -I$(srctree)/arch/mips/include/asm/mach-generic
 drivers-$(CONFIG_PCI)		+= arch/mips/pci/
 
-ifdef CONFIG_32BIT
-ifdef CONFIG_CPU_LITTLE_ENDIAN
-JIFFIES			= jiffies_64
-else
-JIFFIES			= jiffies_64 + 4
-endif
-else
-JIFFIES			= jiffies_64
-endif
-
 #
 # Automatically detect the build format. By default we choose
 # the elf format according to the load address.
@@ -648,8 +638,9 @@ ifdef CONFIG_64BIT
 endif
 
 KBUILD_AFLAGS	+= $(cflags-y)
-KBUILD_CFLAGS	+= $(cflags-y) \
-			-D"VMLINUX_LOAD_ADDRESS=$(load-y)"
+KBUILD_CFLAGS	+= $(cflags-y)
+KBUILD_CPPFLAGS += -D"VMLINUX_LOAD_ADDRESS=$(load-y)"
+KBUILD_CPPFLAGS += -D"DATAOFFSET=$(if $(dataoffset-y),$(dataoffset-y),0)"
 
 LDFLAGS			+= -m $(ld-emul)
 
@@ -664,18 +655,6 @@ endif
 
 OBJCOPYFLAGS		+= --remove-section=.reginfo
 
-#
-# Choosing incompatible machines durings configuration will result in
-# error messages during linking.  Select a default linkscript if
-# none has been choosen above.
-#
-
-CPPFLAGS_vmlinux.lds := \
-	$(KBUILD_CFLAGS) \
-	-D"LOADADDR=$(load-y)" \
-	-D"JIFFIES=$(JIFFIES)" \
-	-D"DATAOFFSET=$(if $(dataoffset-y),$(dataoffset-y),0)"
-
 head-y := arch/mips/kernel/head.o arch/mips/kernel/init_task.o
 
 libs-y			+= arch/mips/lib/
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index e96122159928..eecd2a9f155c 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -2,6 +2,8 @@
 # Makefile for the Linux/MIPS kernel.
 #
 
+CPPFLAGS_vmlinux.lds := $(KBUILD_CFLAGS)
+
 extra-y		:= head.o init_task.o vmlinux.lds
 
 obj-y		+= cpu-probe.o branch.o entry.o genex.o irq.o process.o \
diff --git a/arch/mips/kernel/vmlinux.lds.S b/arch/mips/kernel/vmlinux.lds.S
index 58738c8d754f..b245f4663fa1 100644
--- a/arch/mips/kernel/vmlinux.lds.S
+++ b/arch/mips/kernel/vmlinux.lds.S
@@ -9,7 +9,16 @@ PHDRS {
 	text PT_LOAD FLAGS(7);	/* RWX */
 	note PT_NOTE FLAGS(4);	/* R__ */
 }
-jiffies = JIFFIES;
+
+#ifdef CONFIG_32BIT
+	#ifdef CONFIG_CPU_LITTLE_ENDIAN
+		jiffies  = jiffies_64;
+	#else
+		jiffies  = jiffies_64 + 4;
+	#endif
+#else
+	jiffies  = jiffies_64;
+#endif
 
 SECTIONS
 {
@@ -28,7 +37,7 @@ SECTIONS
 	/* . = 0xa800000000300000; */
 	. = 0xffffffff80300000;
 #endif
-	. = LOADADDR;
+	. = VMLINUX_LOAD_ADDRESS;
 	/* read-only */
 	_text = .;	/* Text and read-only data */
 	.text : {
diff --git a/arch/powerpc/Makefile b/arch/powerpc/Makefile
index bc35f4e2b81c..39d44f7ff390 100644
--- a/arch/powerpc/Makefile
+++ b/arch/powerpc/Makefile
@@ -158,8 +158,6 @@ drivers-$(CONFIG_OPROFILE)	+= arch/powerpc/oprofile/
 # Default to zImage, override when needed
 all: zImage
 
-CPPFLAGS_vmlinux.lds	:= -Upowerpc
-
 BOOT_TARGETS = zImage zImage.initrd uImage zImage% dtbImage% treeImage.% cuImage.% simpleImage.%
 
 PHONY += $(BOOT_TARGETS)
diff --git a/arch/powerpc/include/asm/elf.h b/arch/powerpc/include/asm/elf.h
index 014a624f4c8e..56985023a47d 100644
--- a/arch/powerpc/include/asm/elf.h
+++ b/arch/powerpc/include/asm/elf.h
@@ -236,14 +236,10 @@ typedef elf_vrregset_t elf_fpxregset_t;
 #ifdef __powerpc64__
 # define SET_PERSONALITY(ex)					\
 do {								\
-	unsigned long new_flags = 0;				\
 	if ((ex).e_ident[EI_CLASS] == ELFCLASS32)		\
-		new_flags = _TIF_32BIT;				\
-	if ((current_thread_info()->flags & _TIF_32BIT)		\
-	    != new_flags)					\
-		set_thread_flag(TIF_ABI_PENDING);		\
+		set_thread_flag(TIF_32BIT);			\
 	else							\
-		clear_thread_flag(TIF_ABI_PENDING);		\
+		clear_thread_flag(TIF_32BIT);			\
 	if (personality(current->personality) != PER_LINUX32)	\
 		set_personality(PER_LINUX |			\
 			(current->personality & (~PER_MASK)));	\
diff --git a/arch/powerpc/include/asm/kmap_types.h b/arch/powerpc/include/asm/kmap_types.h
index b6bac6f61c16..916369575c97 100644
--- a/arch/powerpc/include/asm/kmap_types.h
+++ b/arch/powerpc/include/asm/kmap_types.h
@@ -29,5 +29,16 @@ enum km_type {
 	KM_TYPE_NR
 };
 
+/*
+ * This is a temporary build fix that (so they say on lkml....) should no longer
+ * be required after 2.6.33, because of changes planned to the kmap code.
+ * Let's try to remove this cruft then.
+ */
+#ifdef CONFIG_DEBUG_HIGHMEM
+#define KM_NMI		(-1)
+#define KM_NMI_PTE	(-1)
+#define KM_IRQ_PTE	(-1)
+#endif
+
 #endif	/* __KERNEL__ */
 #endif	/* _ASM_POWERPC_KMAP_TYPES_H */
diff --git a/arch/powerpc/include/asm/mmu-hash64.h b/arch/powerpc/include/asm/mmu-hash64.h
index 98c104a09961..edab67ee8e53 100644
--- a/arch/powerpc/include/asm/mmu-hash64.h
+++ b/arch/powerpc/include/asm/mmu-hash64.h
@@ -41,6 +41,7 @@ extern char initial_stab[];
 
 #define SLB_NUM_BOLTED		3
 #define SLB_CACHE_ENTRIES	8
+#define SLB_MIN_SIZE		32
 
 /* Bits in the SLB ESID word */
 #define SLB_ESID_V		ASM_CONST(0x0000000008000000) /* valid */
@@ -296,6 +297,7 @@ extern void slb_flush_and_rebolt(void);
 extern void stab_initialize(unsigned long stab);
 
 extern void slb_vmalloc_update(void);
+extern void slb_set_size(u16 size);
 #endif /* __ASSEMBLY__ */
 
 /*
diff --git a/arch/powerpc/include/asm/pmc.h b/arch/powerpc/include/asm/pmc.h
index d6a616a1b3ea..ccc68b50d05d 100644
--- a/arch/powerpc/include/asm/pmc.h
+++ b/arch/powerpc/include/asm/pmc.h
@@ -27,10 +27,22 @@ extern perf_irq_t perf_irq;
 
 int reserve_pmc_hardware(perf_irq_t new_perf_irq);
 void release_pmc_hardware(void);
+void ppc_enable_pmcs(void);
 
 #ifdef CONFIG_PPC64
-void power4_enable_pmcs(void);
-void pasemi_enable_pmcs(void);
+#include <asm/lppaca.h>
+
+static inline void ppc_set_pmu_inuse(int inuse)
+{
+	get_lppaca()->pmcregs_in_use = inuse;
+}
+
+extern void power4_enable_pmcs(void);
+
+#else /* CONFIG_PPC64 */
+
+static inline void ppc_set_pmu_inuse(int inuse) { }
+
 #endif
 
 #endif /* __KERNEL__ */
diff --git a/arch/powerpc/include/asm/pte-common.h b/arch/powerpc/include/asm/pte-common.h
index a7e210b6b48c..0cd2e3433e1c 100644
--- a/arch/powerpc/include/asm/pte-common.h
+++ b/arch/powerpc/include/asm/pte-common.h
@@ -176,7 +176,7 @@ extern unsigned long bad_call_to_PMD_PAGE_SIZE(void);
 #define HAVE_PAGE_AGP
 
 /* Advertise support for _PAGE_SPECIAL */
-#ifdef _PAGE_SPECIAL
+#if _PAGE_SPECIAL != 0
 #define __HAVE_ARCH_PTE_SPECIAL
 #endif
 
diff --git a/arch/powerpc/include/asm/thread_info.h b/arch/powerpc/include/asm/thread_info.h
index c8b329255678..aa9d383a1c09 100644
--- a/arch/powerpc/include/asm/thread_info.h
+++ b/arch/powerpc/include/asm/thread_info.h
@@ -111,7 +111,6 @@ static inline struct thread_info *current_thread_info(void)
 #define TIF_NOTIFY_RESUME	13	/* callback before returning to user */
 #define TIF_FREEZE		14	/* Freezing for suspend */
 #define TIF_RUNLATCH		15	/* Is the runlatch enabled? */
-#define TIF_ABI_PENDING		16	/* 32/64 bit switch needed */
 
 /* as above, but as bit values */
 #define _TIF_SYSCALL_TRACE	(1<<TIF_SYSCALL_TRACE)
@@ -129,7 +128,6 @@ static inline struct thread_info *current_thread_info(void)
 #define _TIF_NOTIFY_RESUME	(1<<TIF_NOTIFY_RESUME)
 #define _TIF_FREEZE		(1<<TIF_FREEZE)
 #define _TIF_RUNLATCH		(1<<TIF_RUNLATCH)
-#define _TIF_ABI_PENDING	(1<<TIF_ABI_PENDING)
 #define _TIF_SYSCALL_T_OR_A	(_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT|_TIF_SECCOMP)
 
 #define _TIF_USER_WORK_MASK	(_TIF_SIGPENDING | _TIF_NEED_RESCHED | \
diff --git a/arch/powerpc/kernel/lparcfg.c b/arch/powerpc/kernel/lparcfg.c
index 2419cc706ff1..ed0ac4e4b8d8 100644
--- a/arch/powerpc/kernel/lparcfg.c
+++ b/arch/powerpc/kernel/lparcfg.c
@@ -35,6 +35,7 @@
 #include <asm/prom.h>
 #include <asm/vdso_datapage.h>
 #include <asm/vio.h>
+#include <asm/mmu.h>
 
 #define MODULE_VERS "1.8"
 #define MODULE_NAME "lparcfg"
@@ -537,6 +538,8 @@ static int pseries_lparcfg_data(struct seq_file *m, void *v)
 
 	seq_printf(m, "shared_processor_mode=%d\n", lppaca[0].shared_proc);
 
+	seq_printf(m, "slb_size=%d\n", mmu_slb_size);
+
 	return 0;
 }
 
diff --git a/arch/powerpc/kernel/perf_counter.c b/arch/powerpc/kernel/perf_counter.c
index 70e1f57f7dd8..7ceefaf3a7f5 100644
--- a/arch/powerpc/kernel/perf_counter.c
+++ b/arch/powerpc/kernel/perf_counter.c
@@ -32,6 +32,9 @@ struct cpu_hw_counters {
 	unsigned long mmcr[3];
 	struct perf_counter *limited_counter[MAX_LIMITED_HWCOUNTERS];
 	u8  limited_hwidx[MAX_LIMITED_HWCOUNTERS];
+	u64 alternatives[MAX_HWCOUNTERS][MAX_EVENT_ALTERNATIVES];
+	unsigned long amasks[MAX_HWCOUNTERS][MAX_EVENT_ALTERNATIVES];
+	unsigned long avalues[MAX_HWCOUNTERS][MAX_EVENT_ALTERNATIVES];
 };
 DEFINE_PER_CPU(struct cpu_hw_counters, cpu_hw_counters);
 
@@ -62,7 +65,6 @@ static inline unsigned long perf_ip_adjust(struct pt_regs *regs)
 {
 	return 0;
 }
-static inline void perf_set_pmu_inuse(int inuse) { }
 static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp) { }
 static inline u32 perf_get_misc_flags(struct pt_regs *regs)
 {
@@ -93,11 +95,6 @@ static inline unsigned long perf_ip_adjust(struct pt_regs *regs)
 	return 0;
 }
 
-static inline void perf_set_pmu_inuse(int inuse)
-{
-	get_lppaca()->pmcregs_in_use = inuse;
-}
-
 /*
  * The user wants a data address recorded.
  * If we're not doing instruction sampling, give them the SDAR
@@ -245,13 +242,11 @@ static void write_pmc(int idx, unsigned long val)
  * and see if any combination of alternative codes is feasible.
  * The feasible set is returned in event[].
  */
-static int power_check_constraints(u64 event[], unsigned int cflags[],
+static int power_check_constraints(struct cpu_hw_counters *cpuhw,
+				   u64 event[], unsigned int cflags[],
 				   int n_ev)
 {
 	unsigned long mask, value, nv;
-	u64 alternatives[MAX_HWCOUNTERS][MAX_EVENT_ALTERNATIVES];
-	unsigned long amasks[MAX_HWCOUNTERS][MAX_EVENT_ALTERNATIVES];
-	unsigned long avalues[MAX_HWCOUNTERS][MAX_EVENT_ALTERNATIVES];
 	unsigned long smasks[MAX_HWCOUNTERS], svalues[MAX_HWCOUNTERS];
 	int n_alt[MAX_HWCOUNTERS], choice[MAX_HWCOUNTERS];
 	int i, j;
@@ -266,21 +261,23 @@ static int power_check_constraints(u64 event[], unsigned int cflags[],
 		if ((cflags[i] & PPMU_LIMITED_PMC_REQD)
 		    && !ppmu->limited_pmc_event(event[i])) {
 			ppmu->get_alternatives(event[i], cflags[i],
-					       alternatives[i]);
-			event[i] = alternatives[i][0];
+					       cpuhw->alternatives[i]);
+			event[i] = cpuhw->alternatives[i][0];
 		}
-		if (ppmu->get_constraint(event[i], &amasks[i][0],
-					 &avalues[i][0]))
+		if (ppmu->get_constraint(event[i], &cpuhw->amasks[i][0],
+					 &cpuhw->avalues[i][0]))
 			return -1;
 	}
 	value = mask = 0;
 	for (i = 0; i < n_ev; ++i) {
-		nv = (value | avalues[i][0]) + (value & avalues[i][0] & addf);
+		nv = (value | cpuhw->avalues[i][0]) +
+			(value & cpuhw->avalues[i][0] & addf);
 		if ((((nv + tadd) ^ value) & mask) != 0 ||
-		    (((nv + tadd) ^ avalues[i][0]) & amasks[i][0]) != 0)
+		    (((nv + tadd) ^ cpuhw->avalues[i][0]) &
+		     cpuhw->amasks[i][0]) != 0)
 			break;
 		value = nv;
-		mask |= amasks[i][0];
+		mask |= cpuhw->amasks[i][0];
 	}
 	if (i == n_ev)
 		return 0;	/* all OK */
@@ -291,10 +288,11 @@ static int power_check_constraints(u64 event[], unsigned int cflags[],
 	for (i = 0; i < n_ev; ++i) {
 		choice[i] = 0;
 		n_alt[i] = ppmu->get_alternatives(event[i], cflags[i],
-						  alternatives[i]);
+						  cpuhw->alternatives[i]);
 		for (j = 1; j < n_alt[i]; ++j)
-			ppmu->get_constraint(alternatives[i][j],
-					     &amasks[i][j], &avalues[i][j]);
+			ppmu->get_constraint(cpuhw->alternatives[i][j],
+					     &cpuhw->amasks[i][j],
+					     &cpuhw->avalues[i][j]);
 	}
 
 	/* enumerate all possibilities and see if any will work */
@@ -313,11 +311,11 @@ static int power_check_constraints(u64 event[], unsigned int cflags[],
 		 * where k > j, will satisfy the constraints.
 		 */
 		while (++j < n_alt[i]) {
-			nv = (value | avalues[i][j]) +
-				(value & avalues[i][j] & addf);
+			nv = (value | cpuhw->avalues[i][j]) +
+				(value & cpuhw->avalues[i][j] & addf);
 			if ((((nv + tadd) ^ value) & mask) == 0 &&
-			    (((nv + tadd) ^ avalues[i][j])
-			     & amasks[i][j]) == 0)
+			    (((nv + tadd) ^ cpuhw->avalues[i][j])
+			     & cpuhw->amasks[i][j]) == 0)
 				break;
 		}
 		if (j >= n_alt[i]) {
@@ -339,7 +337,7 @@ static int power_check_constraints(u64 event[], unsigned int cflags[],
 			svalues[i] = value;
 			smasks[i] = mask;
 			value = nv;
-			mask |= amasks[i][j];
+			mask |= cpuhw->amasks[i][j];
 			++i;
 			j = -1;
 		}
@@ -347,7 +345,7 @@ static int power_check_constraints(u64 event[], unsigned int cflags[],
 
 	/* OK, we have a feasible combination, tell the caller the solution */
 	for (i = 0; i < n_ev; ++i)
-		event[i] = alternatives[i][choice[i]];
+		event[i] = cpuhw->alternatives[i][choice[i]];
 	return 0;
 }
 
@@ -531,8 +529,7 @@ void hw_perf_disable(void)
 		 * Check if we ever enabled the PMU on this cpu.
 		 */
 		if (!cpuhw->pmcs_enabled) {
-			if (ppc_md.enable_pmcs)
-				ppc_md.enable_pmcs();
+			ppc_enable_pmcs();
 			cpuhw->pmcs_enabled = 1;
 		}
 
@@ -594,7 +591,7 @@ void hw_perf_enable(void)
 		mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE);
 		mtspr(SPRN_MMCR1, cpuhw->mmcr[1]);
 		if (cpuhw->n_counters == 0)
-			perf_set_pmu_inuse(0);
+			ppc_set_pmu_inuse(0);
 		goto out_enable;
 	}
 
@@ -627,7 +624,7 @@ void hw_perf_enable(void)
 	 * bit set and set the hardware counters to their initial values.
 	 * Then unfreeze the counters.
 	 */
-	perf_set_pmu_inuse(1);
+	ppc_set_pmu_inuse(1);
 	mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE);
 	mtspr(SPRN_MMCR1, cpuhw->mmcr[1]);
 	mtspr(SPRN_MMCR0, (cpuhw->mmcr[0] & ~(MMCR0_PMC1CE | MMCR0_PMCjCE))
@@ -752,7 +749,7 @@ int hw_perf_group_sched_in(struct perf_counter *group_leader,
 		return -EAGAIN;
 	if (check_excludes(cpuhw->counter, cpuhw->flags, n0, n))
 		return -EAGAIN;
-	i = power_check_constraints(cpuhw->events, cpuhw->flags, n + n0);
+	i = power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n + n0);
 	if (i < 0)
 		return -EAGAIN;
 	cpuhw->n_counters = n0 + n;
@@ -807,7 +804,7 @@ static int power_pmu_enable(struct perf_counter *counter)
 	cpuhw->flags[n0] = counter->hw.counter_base;
 	if (check_excludes(cpuhw->counter, cpuhw->flags, n0, 1))
 		goto out;
-	if (power_check_constraints(cpuhw->events, cpuhw->flags, n0 + 1))
+	if (power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n0 + 1))
 		goto out;
 
 	counter->hw.config = cpuhw->events[n0];
@@ -1012,6 +1009,7 @@ const struct pmu *hw_perf_counter_init(struct perf_counter *counter)
 	unsigned int cflags[MAX_HWCOUNTERS];
 	int n;
 	int err;
+	struct cpu_hw_counters *cpuhw;
 
 	if (!ppmu)
 		return ERR_PTR(-ENXIO);
@@ -1090,7 +1088,11 @@ const struct pmu *hw_perf_counter_init(struct perf_counter *counter)
 	cflags[n] = flags;
 	if (check_excludes(ctrs, cflags, n, 1))
 		return ERR_PTR(-EINVAL);
-	if (power_check_constraints(events, cflags, n + 1))
+
+	cpuhw = &get_cpu_var(cpu_hw_counters);
+	err = power_check_constraints(cpuhw, events, cflags, n + 1);
+	put_cpu_var(cpu_hw_counters);
+	if (err)
 		return ERR_PTR(-EINVAL);
 
 	counter->hw.config = events[n];
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index 892a9f2e6d76..1ea56fdccef4 100644
--- a/arch/powerpc/kernel/process.c
+++ b/arch/powerpc/kernel/process.c
@@ -554,18 +554,6 @@ void exit_thread(void)
 
 void flush_thread(void)
 {
-#ifdef CONFIG_PPC64
-	struct thread_info *t = current_thread_info();
-
-	if (test_ti_thread_flag(t, TIF_ABI_PENDING)) {
-		clear_ti_thread_flag(t, TIF_ABI_PENDING);
-		if (test_ti_thread_flag(t, TIF_32BIT))
-			clear_ti_thread_flag(t, TIF_32BIT);
-		else
-			set_ti_thread_flag(t, TIF_32BIT);
-	}
-#endif
-
 	discard_lazy_cpu_state();
 
 	if (current->thread.dabr) {
diff --git a/arch/powerpc/kernel/rtas.c b/arch/powerpc/kernel/rtas.c
index c434823b8c83..bf90361bb70f 100644
--- a/arch/powerpc/kernel/rtas.c
+++ b/arch/powerpc/kernel/rtas.c
@@ -39,6 +39,7 @@
 #include <asm/smp.h>
 #include <asm/atomic.h>
 #include <asm/time.h>
+#include <asm/mmu.h>
 
 struct rtas_t rtas = {
 	.lock = __RAW_SPIN_LOCK_UNLOCKED
@@ -713,6 +714,7 @@ static void rtas_percpu_suspend_me(void *info)
 {
 	long rc = H_SUCCESS;
 	unsigned long msr_save;
+	u16 slb_size = mmu_slb_size;
 	int cpu;
 	struct rtas_suspend_me_data *data =
 		(struct rtas_suspend_me_data *)info;
@@ -735,13 +737,16 @@ static void rtas_percpu_suspend_me(void *info)
 		/* All other cpus are in H_JOIN, this cpu does
 		 * the suspend.
 		 */
+		slb_set_size(SLB_MIN_SIZE);
 		printk(KERN_DEBUG "calling ibm,suspend-me on cpu %i\n",
 		       smp_processor_id());
 		data->error = rtas_call(data->token, 0, 1, NULL);
 
-		if (data->error)
+		if (data->error) {
 			printk(KERN_DEBUG "ibm,suspend-me returned %d\n",
 			       data->error);
+			slb_set_size(slb_size);
+		}
 	} else {
 		printk(KERN_ERR "H_JOIN on cpu %i failed with rc = %ld\n",
 		       smp_processor_id(), rc);
diff --git a/arch/powerpc/kernel/sysfs.c b/arch/powerpc/kernel/sysfs.c
index f41aec85aa49..956ab33fd73f 100644
--- a/arch/powerpc/kernel/sysfs.c
+++ b/arch/powerpc/kernel/sysfs.c
@@ -17,6 +17,7 @@
 #include <asm/prom.h>
 #include <asm/machdep.h>
 #include <asm/smp.h>
+#include <asm/pmc.h>
 
 #include "cacheinfo.h"
 
@@ -123,6 +124,8 @@ static DEFINE_PER_CPU(char, pmcs_enabled);
 
 void ppc_enable_pmcs(void)
 {
+	ppc_set_pmu_inuse(1);
+
 	/* Only need to enable them once */
 	if (__get_cpu_var(pmcs_enabled))
 		return;
diff --git a/arch/powerpc/kernel/vector.S b/arch/powerpc/kernel/vector.S
index ea4d64644d02..419f492cb586 100644
--- a/arch/powerpc/kernel/vector.S
+++ b/arch/powerpc/kernel/vector.S
@@ -58,7 +58,7 @@ _GLOBAL(load_up_altivec)
 	 * all 1's
 	 */
 	mfspr	r4,SPRN_VRSAVE
-	cmpdi	0,r4,0
+	cmpwi	0,r4,0
 	bne+	1f
 	li	r4,-1
 	mtspr	SPRN_VRSAVE,r4
diff --git a/arch/powerpc/mm/pgtable.c b/arch/powerpc/mm/pgtable.c
index 627767d6169b..d8e672567f7e 100644
--- a/arch/powerpc/mm/pgtable.c
+++ b/arch/powerpc/mm/pgtable.c
@@ -30,6 +30,8 @@
 #include <asm/tlbflush.h>
 #include <asm/tlb.h>
 
+#include "mmu_decl.h"
+
 static DEFINE_PER_CPU(struct pte_freelist_batch *, pte_freelist_cur);
 static unsigned long pte_freelist_forced_free;
 
@@ -119,7 +121,7 @@ void pte_free_finish(void)
 /*
  * Handle i/d cache flushing, called from set_pte_at() or ptep_set_access_flags()
  */
-static pte_t do_dcache_icache_coherency(pte_t pte)
+static pte_t do_dcache_icache_coherency(pte_t pte, unsigned long addr)
 {
 	unsigned long pfn = pte_pfn(pte);
 	struct page *page;
@@ -128,6 +130,17 @@ static pte_t do_dcache_icache_coherency(pte_t pte)
 		return pte;
 	page = pfn_to_page(pfn);
 
+#ifdef CONFIG_8xx
+       /* On 8xx, cache control instructions (particularly
+        * "dcbst" from flush_dcache_icache) fault as write
+        * operation if there is an unpopulated TLB entry
+        * for the address in question. To workaround that,
+        * we invalidate the TLB here, thus avoiding dcbst
+        * misbehaviour.
+        */
+       _tlbil_va(addr, 0 /* 8xx doesn't care about PID */);
+#endif
+
 	if (!PageReserved(page) && !test_bit(PG_arch_1, &page->flags)) {
 		pr_devel("do_dcache_icache_coherency... flushing\n");
 		flush_dcache_icache_page(page);
@@ -198,7 +211,7 @@ void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep, pte_t pte
 	 */
 	pte = __pte(pte_val(pte) & ~_PAGE_HPTEFLAGS);
 	if (pte_need_exec_flush(pte, 1))
-		pte = do_dcache_icache_coherency(pte);
+		pte = do_dcache_icache_coherency(pte, addr);
 
 	/* Perform the setting of the PTE */
 	__set_pte_at(mm, addr, ptep, pte, 0);
@@ -216,7 +229,7 @@ int ptep_set_access_flags(struct vm_area_struct *vma, unsigned long address,
 {
 	int changed;
 	if (!dirty && pte_need_exec_flush(entry, 0))
-		entry = do_dcache_icache_coherency(entry);
+		entry = do_dcache_icache_coherency(entry, address);
 	changed = !pte_same(*(ptep), entry);
 	if (changed) {
 		if (!(vma->vm_flags & VM_HUGETLB))
diff --git a/arch/powerpc/mm/slb.c b/arch/powerpc/mm/slb.c
index 5b7038f248b6..deb619323f84 100644
--- a/arch/powerpc/mm/slb.c
+++ b/arch/powerpc/mm/slb.c
@@ -240,14 +240,22 @@ void switch_slb(struct task_struct *tsk, struct mm_struct *mm)
 static inline void patch_slb_encoding(unsigned int *insn_addr,
 				      unsigned int immed)
 {
-	/* Assume the instruction had a "0" immediate value, just
-	 * "or" in the new value
-	 */
-	*insn_addr |= immed;
+	*insn_addr = (*insn_addr & 0xffff0000) | immed;
 	flush_icache_range((unsigned long)insn_addr, 4+
 			   (unsigned long)insn_addr);
 }
 
+void slb_set_size(u16 size)
+{
+	extern unsigned int *slb_compare_rr_to_size;
+
+	if (mmu_slb_size == size)
+		return;
+
+	mmu_slb_size = size;
+	patch_slb_encoding(slb_compare_rr_to_size, mmu_slb_size);
+}
+
 void slb_initialize(void)
 {
 	unsigned long linear_llp, vmalloc_llp, io_llp;
diff --git a/arch/powerpc/platforms/powermac/cpufreq_32.c b/arch/powerpc/platforms/powermac/cpufreq_32.c
index 65c585b8b00d..08d94e4cedd3 100644
--- a/arch/powerpc/platforms/powermac/cpufreq_32.c
+++ b/arch/powerpc/platforms/powermac/cpufreq_32.c
@@ -44,14 +44,6 @@
  */
 #undef DEBUG_FREQ
 
-/*
- * There is a problem with the core cpufreq code on SMP kernels,
- * it won't recalculate the Bogomips properly
- */
-#ifdef CONFIG_SMP
-#warning "WARNING, CPUFREQ not recommended on SMP kernels"
-#endif
-
 extern void low_choose_7447a_dfs(int dfs);
 extern void low_choose_750fx_pll(int pll);
 extern void low_sleep_handler(void);
diff --git a/arch/powerpc/platforms/powermac/low_i2c.c b/arch/powerpc/platforms/powermac/low_i2c.c
index 21226b74c9b2..414ca9849f23 100644
--- a/arch/powerpc/platforms/powermac/low_i2c.c
+++ b/arch/powerpc/platforms/powermac/low_i2c.c
@@ -540,8 +540,11 @@ static struct pmac_i2c_host_kw *__init kw_i2c_host_init(struct device_node *np)
 	/* Make sure IRQ is disabled */
 	kw_write_reg(reg_ier, 0);
 
-	/* Request chip interrupt */
-	if (request_irq(host->irq, kw_i2c_irq, 0, "keywest i2c", host))
+	/* Request chip interrupt. We set IRQF_TIMER because we don't
+	 * want that interrupt disabled between the 2 passes of driver
+	 * suspend or we'll have issues running the pfuncs
+	 */
+	if (request_irq(host->irq, kw_i2c_irq, IRQF_TIMER, "keywest i2c", host))
 		host->irq = NO_IRQ;
 
 	printk(KERN_INFO "KeyWest i2c @0x%08x irq %d %s\n",
diff --git a/arch/powerpc/platforms/powermac/pci.c b/arch/powerpc/platforms/powermac/pci.c
index 04cdd32624d4..e81403b245b5 100644
--- a/arch/powerpc/platforms/powermac/pci.c
+++ b/arch/powerpc/platforms/powermac/pci.c
@@ -1286,3 +1286,64 @@ static void fixup_k2_sata(struct pci_dev* dev)
 }
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, 0x0240, fixup_k2_sata);
 
+/*
+ * On U4 (aka CPC945) the PCIe root complex "P2P" bridge resource ranges aren't
+ * configured by the firmware. The bridge itself seems to ignore them but it
+ * causes problems with Linux which then re-assigns devices below the bridge,
+ * thus changing addresses of those devices from what was in the device-tree,
+ * which sucks when those are video cards using offb
+ *
+ * We could just mark it transparent but I prefer fixing up the resources to
+ * properly show what's going on here, as I have some doubts about having them
+ * badly configured potentially being an issue for DMA.
+ *
+ * We leave PIO alone, it seems to be fine
+ *
+ * Oh and there's another funny bug. The OF properties advertize the region
+ * 0xf1000000..0xf1ffffff as being forwarded as memory space. But that's
+ * actually not true, this region is the memory mapped config space. So we
+ * also need to filter it out or we'll map things in the wrong place.
+ */
+static void fixup_u4_pcie(struct pci_dev* dev)
+{
+	struct pci_controller *host = pci_bus_to_host(dev->bus);
+	struct resource *region = NULL;
+	u32 reg;
+	int i;
+
+	/* Only do that on PowerMac */
+	if (!machine_is(powermac))
+		return;
+
+	/* Find the largest MMIO region */
+	for (i = 0; i < 3; i++) {
+		struct resource *r = &host->mem_resources[i];
+		if (!(r->flags & IORESOURCE_MEM))
+			continue;
+		/* Skip the 0xf0xxxxxx..f2xxxxxx regions, we know they
+		 * are reserved by HW for other things
+		 */
+		if (r->start >= 0xf0000000 && r->start < 0xf3000000)
+			continue;
+		if (!region || (r->end - r->start) >
+		    (region->end - region->start))
+			region = r;
+	}
+	/* Nothing found, bail */
+	if (region == 0)
+		return;
+
+	/* Print things out */
+	printk(KERN_INFO "PCI: Fixup U4 PCIe bridge range: %pR\n", region);
+
+	/* Fixup bridge config space. We know it's a Mac, resource aren't
+	 * offset so let's just blast them as-is. We also know that they
+	 * fit in 32 bits
+	 */
+	reg = ((region->start >> 16) & 0xfff0) | (region->end & 0xfff00000);
+	pci_write_config_dword(dev, PCI_MEMORY_BASE, reg);
+	pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0);
+	pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0);
+	pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0);
+}
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_U4_PCIE, fixup_u4_pcie);
diff --git a/arch/powerpc/platforms/powermac/smp.c b/arch/powerpc/platforms/powermac/smp.c
index 6d4da7b46b41..937a38e73178 100644
--- a/arch/powerpc/platforms/powermac/smp.c
+++ b/arch/powerpc/platforms/powermac/smp.c
@@ -408,7 +408,7 @@ static void __init smp_psurge_setup_cpu(int cpu_nr)
 	/* reset the entry point so if we get another intr we won't
 	 * try to startup again */
 	out_be32(psurge_start, 0x100);
-	if (setup_irq(30, &psurge_irqaction))
+	if (setup_irq(irq_create_mapping(NULL, 30), &psurge_irqaction))
 		printk(KERN_ERR "Couldn't get primary IPI interrupt");
 }
 
diff --git a/arch/powerpc/platforms/pseries/msi.c b/arch/powerpc/platforms/pseries/msi.c
index bf2e1ac41308..1164c3430f2c 100644
--- a/arch/powerpc/platforms/pseries/msi.c
+++ b/arch/powerpc/platforms/pseries/msi.c
@@ -432,8 +432,6 @@ static int rtas_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
 		/* Read config space back so we can restore after reset */
 		read_msi_msg(virq, &msg);
 		entry->msg = msg;
-
-		unmask_msi_irq(virq);
 	}
 
 	return 0;
diff --git a/arch/powerpc/platforms/pseries/reconfig.c b/arch/powerpc/platforms/pseries/reconfig.c
index b6f1b137d427..2e2bbe120b90 100644
--- a/arch/powerpc/platforms/pseries/reconfig.c
+++ b/arch/powerpc/platforms/pseries/reconfig.c
@@ -20,6 +20,7 @@
 #include <asm/machdep.h>
 #include <asm/uaccess.h>
 #include <asm/pSeries_reconfig.h>
+#include <asm/mmu.h>
 
 
 
@@ -439,9 +440,15 @@ static int do_update_property(char *buf, size_t bufsize)
 	if (!newprop)
 		return -ENOMEM;
 
+	if (!strcmp(name, "slb-size") || !strcmp(name, "ibm,slb-size"))
+		slb_set_size(*(int *)value);
+
 	oldprop = of_find_property(np, name,NULL);
-	if (!oldprop)
+	if (!oldprop) {
+		if (strlen(name))
+			return prom_add_property(np, newprop);
 		return -ENODEV;
+	}
 
 	rc = prom_update_property(np, newprop, oldprop);
 	if (rc)
diff --git a/arch/powerpc/platforms/pseries/setup.c b/arch/powerpc/platforms/pseries/setup.c
index 8d75ea21296f..ca5f2e10972c 100644
--- a/arch/powerpc/platforms/pseries/setup.c
+++ b/arch/powerpc/platforms/pseries/setup.c
@@ -223,10 +223,6 @@ static void pseries_lpar_enable_pmcs(void)
 	set = 1UL << 63;
 	reset = 0;
 	plpar_hcall_norets(H_PERFMON, set, reset);
-
-	/* instruct hypervisor to maintain PMCs */
-	if (firmware_has_feature(FW_FEATURE_SPLPAR))
-		get_lppaca()->pmcregs_in_use = 1;
 }
 
 static void __init pseries_discover_pic(void)
diff --git a/arch/powerpc/platforms/pseries/xics.c b/arch/powerpc/platforms/pseries/xics.c
index 419f8a637ffe..b9bf0eedccf2 100644
--- a/arch/powerpc/platforms/pseries/xics.c
+++ b/arch/powerpc/platforms/pseries/xics.c
@@ -18,6 +18,7 @@
 #include <linux/init.h>
 #include <linux/radix-tree.h>
 #include <linux/cpu.h>
+#include <linux/msi.h>
 #include <linux/of.h>
 
 #include <asm/firmware.h>
@@ -219,6 +220,14 @@ static void xics_unmask_irq(unsigned int virq)
 
 static unsigned int xics_startup(unsigned int virq)
 {
+	/*
+	 * The generic MSI code returns with the interrupt disabled on the
+	 * card, using the MSI mask bits. Firmware doesn't appear to unmask
+	 * at that level, so we do it here by hand.
+	 */
+	if (irq_to_desc(virq)->msi_desc)
+		unmask_msi_irq(virq);
+
 	/* unmask it */
 	xics_unmask_irq(virq);
 	return 0;
diff --git a/arch/s390/include/asm/kvm.h b/arch/s390/include/asm/kvm.h
index 0b2f829f6d50..1e313567d1ee 100644
--- a/arch/s390/include/asm/kvm.h
+++ b/arch/s390/include/asm/kvm.h
@@ -1,6 +1,5 @@
 #ifndef __LINUX_KVM_S390_H
 #define __LINUX_KVM_S390_H
-
 /*
  * asm-s390/kvm.h - KVM s390 specific structures and definitions
  *
@@ -24,6 +23,8 @@ struct kvm_ioapic_state {
 	/* no IOAPIC for s390 */
 };
 
+#define __KVM_S390
+
 /* for KVM_GET_REGS and KVM_SET_REGS */
 struct kvm_regs {
 	/* general purpose regs for s390 */
diff --git a/arch/s390/kvm/kvm-s390.c b/arch/s390/kvm/kvm-s390.c
index 90d9d1ba258b..475fc2986a46 100644
--- a/arch/s390/kvm/kvm-s390.c
+++ b/arch/s390/kvm/kvm-s390.c
@@ -115,10 +115,16 @@ long kvm_arch_dev_ioctl(struct file *filp,
 
 int kvm_dev_ioctl_check_extension(long ext)
 {
+	int r;
+
 	switch (ext) {
+	case KVM_CAP_S390_PSW:
+		r = 1;
+		break;
 	default:
-		return 0;
+		r = 0;
 	}
+	return r;
 }
 
 /* Section: vm related */
@@ -422,8 +428,10 @@ static int kvm_arch_vcpu_ioctl_set_initial_psw(struct kvm_vcpu *vcpu, psw_t psw)
 	vcpu_load(vcpu);
 	if (atomic_read(&vcpu->arch.sie_block->cpuflags) & CPUSTAT_RUNNING)
 		rc = -EBUSY;
-	else
-		vcpu->arch.sie_block->gpsw = psw;
+	else {
+		vcpu->run->psw_mask = psw.mask;
+		vcpu->run->psw_addr = psw.addr;
+	}
 	vcpu_put(vcpu);
 	return rc;
 }
@@ -505,9 +513,6 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
 
 	switch (kvm_run->exit_reason) {
 	case KVM_EXIT_S390_SIEIC:
-		vcpu->arch.sie_block->gpsw.mask = kvm_run->s390_sieic.mask;
-		vcpu->arch.sie_block->gpsw.addr = kvm_run->s390_sieic.addr;
-		break;
 	case KVM_EXIT_UNKNOWN:
 	case KVM_EXIT_S390_RESET:
 		break;
@@ -515,6 +520,9 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
 		BUG();
 	}
 
+	vcpu->arch.sie_block->gpsw.mask = kvm_run->psw_mask;
+	vcpu->arch.sie_block->gpsw.addr = kvm_run->psw_addr;
+
 	might_fault();
 
 	do {
@@ -529,8 +537,6 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
 		/* intercept cannot be handled in-kernel, prepare kvm-run */
 		kvm_run->exit_reason         = KVM_EXIT_S390_SIEIC;
 		kvm_run->s390_sieic.icptcode = vcpu->arch.sie_block->icptcode;
-		kvm_run->s390_sieic.mask     = vcpu->arch.sie_block->gpsw.mask;
-		kvm_run->s390_sieic.addr     = vcpu->arch.sie_block->gpsw.addr;
 		kvm_run->s390_sieic.ipa      = vcpu->arch.sie_block->ipa;
 		kvm_run->s390_sieic.ipb      = vcpu->arch.sie_block->ipb;
 		rc = 0;
@@ -542,6 +548,9 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
 		rc = 0;
 	}
 
+	kvm_run->psw_mask     = vcpu->arch.sie_block->gpsw.mask;
+	kvm_run->psw_addr     = vcpu->arch.sie_block->gpsw.addr;
+
 	if (vcpu->sigset_active)
 		sigprocmask(SIG_SETMASK, &sigsaved, NULL);
 
diff --git a/arch/sh/kernel/process_64.c b/arch/sh/kernel/process_64.c
index 24de74214940..54a5abf123f3 100644
--- a/arch/sh/kernel/process_64.c
+++ b/arch/sh/kernel/process_64.c
@@ -367,7 +367,7 @@ void exit_thread(void)
 void flush_thread(void)
 {
 
-	/* Called by fs/exec.c (flush_old_exec) to remove traces of a
+	/* Called by fs/exec.c (setup_new_exec) to remove traces of a
 	 * previously running executable. */
 #ifdef CONFIG_SH_FPU
 	if (last_task_used_math == current) {
diff --git a/arch/sparc/Makefile b/arch/sparc/Makefile
index 2003ded054c2..ef9a6b02235f 100644
--- a/arch/sparc/Makefile
+++ b/arch/sparc/Makefile
@@ -27,11 +27,11 @@ AS             := $(AS) -32
 LDFLAGS        := -m elf32_sparc
 CHECKFLAGS     += -D__sparc__
 export BITS    := 32
+UTS_MACHINE    := sparc
 
 #KBUILD_CFLAGS += -g -pipe -fcall-used-g5 -fcall-used-g7
 KBUILD_CFLAGS += -m32 -pipe -mno-fpu -fcall-used-g5 -fcall-used-g7
 KBUILD_AFLAGS += -m32
-CPPFLAGS_vmlinux.lds += -m32
 
 #LDFLAGS_vmlinux = -N -Ttext 0xf0004000
 #  Since 2.5.40, the first stage is left not btfix-ed.
@@ -49,11 +49,9 @@ else
 
 CHECKFLAGS      += -D__sparc__ -D__sparc_v9__ -D__arch64__ -m64
 
-# Undefine sparc when processing vmlinux.lds - it is used
-# And teach CPP we are doing 64 bit builds (for this case)
-CPPFLAGS_vmlinux.lds += -m64 -Usparc
 LDFLAGS              := -m elf64_sparc
 export BITS          := 64
+UTS_MACHINE          := sparc64
 
 KBUILD_CFLAGS += -m64 -pipe -mno-fpu -mcpu=ultrasparc -mcmodel=medlow   \
                  -ffixed-g4 -ffixed-g5 -fcall-used-g7 -Wno-sign-compare \
diff --git a/arch/sparc/include/asm/elf_64.h b/arch/sparc/include/asm/elf_64.h
index d42e393078c4..996808587914 100644
--- a/arch/sparc/include/asm/elf_64.h
+++ b/arch/sparc/include/asm/elf_64.h
@@ -196,17 +196,10 @@ static inline unsigned int sparc64_elf_hwcap(void)
 #define ELF_PLATFORM	(NULL)
 
 #define SET_PERSONALITY(ex)				\
-do {	unsigned long new_flags = current_thread_info()->flags; \
-	new_flags &= _TIF_32BIT;			\
-	if ((ex).e_ident[EI_CLASS] == ELFCLASS32)	\
-		new_flags |= _TIF_32BIT;		\
+do {	if ((ex).e_ident[EI_CLASS] == ELFCLASS32)	\
+		set_thread_flag(TIF_32BIT);		\
 	else						\
-		new_flags &= ~_TIF_32BIT;		\
-	if ((current_thread_info()->flags & _TIF_32BIT) \
-	    != new_flags)				\
-		set_thread_flag(TIF_ABI_PENDING);	\
-	else						\
-		clear_thread_flag(TIF_ABI_PENDING);	\
+		clear_thread_flag(TIF_32BIT);		\
 	/* flush_thread will update pgd cache */	\
 	if (personality(current->personality) != PER_LINUX32)	\
 		set_personality(PER_LINUX |		\
diff --git a/arch/sparc/include/asm/thread_info_64.h b/arch/sparc/include/asm/thread_info_64.h
index 1b45a7bbe407..f78ad9a1b497 100644
--- a/arch/sparc/include/asm/thread_info_64.h
+++ b/arch/sparc/include/asm/thread_info_64.h
@@ -227,12 +227,11 @@ register struct thread_info *current_thread_info_reg asm("g6");
 /* flag bit 8 is available */
 #define TIF_SECCOMP		9	/* secure computing */
 #define TIF_SYSCALL_AUDIT	10	/* syscall auditing active */
-/* flag bit 11 is available */
 /* NOTE: Thread flags >= 12 should be ones we have no interest
  *       in using in assembly, else we can't use the mask as
  *       an immediate value in instructions such as andcc.
  */
-#define TIF_ABI_PENDING		12
+/* flag bit 12 is available */
 #define TIF_MEMDIE		13
 #define TIF_POLLING_NRFLAG	14
 #define TIF_FREEZE		15	/* is freezing for suspend */
@@ -246,7 +245,6 @@ register struct thread_info *current_thread_info_reg asm("g6");
 #define _TIF_32BIT		(1<<TIF_32BIT)
 #define _TIF_SECCOMP		(1<<TIF_SECCOMP)
 #define _TIF_SYSCALL_AUDIT	(1<<TIF_SYSCALL_AUDIT)
-#define _TIF_ABI_PENDING	(1<<TIF_ABI_PENDING)
 #define _TIF_POLLING_NRFLAG	(1<<TIF_POLLING_NRFLAG)
 #define _TIF_FREEZE		(1<<TIF_FREEZE)
 
diff --git a/arch/sparc/kernel/Makefile b/arch/sparc/kernel/Makefile
index 475ce4696acd..cbf5d0b541dd 100644
--- a/arch/sparc/kernel/Makefile
+++ b/arch/sparc/kernel/Makefile
@@ -7,7 +7,11 @@ ccflags-y := -Werror
 
 extra-y     := head_$(BITS).o
 extra-y     += init_task.o
-extra-y     += vmlinux.lds
+
+# Undefine sparc when processing vmlinux.lds - it is used
+# And teach CPP we are doing $(BITS) builds (for this case)
+CPPFLAGS_vmlinux.lds := -Usparc -m$(BITS)
+extra-y              += vmlinux.lds
 
 obj-$(CONFIG_SPARC32)   += entry.o wof.o wuf.o
 obj-$(CONFIG_SPARC32)   += etrap_32.o
diff --git a/arch/sparc/kernel/ldc.c b/arch/sparc/kernel/ldc.c
index adf5f273868a..e0ba898e30cf 100644
--- a/arch/sparc/kernel/ldc.c
+++ b/arch/sparc/kernel/ldc.c
@@ -1242,13 +1242,13 @@ int ldc_bind(struct ldc_channel *lp, const char *name)
 	snprintf(lp->tx_irq_name, LDC_IRQ_NAME_MAX, "%s TX", name);
 
 	err = request_irq(lp->cfg.rx_irq, ldc_rx,
-			  IRQF_SAMPLE_RANDOM | IRQF_SHARED,
+			  IRQF_SAMPLE_RANDOM | IRQF_DISABLED,
 			  lp->rx_irq_name, lp);
 	if (err)
 		return err;
 
 	err = request_irq(lp->cfg.tx_irq, ldc_tx,
-			  IRQF_SAMPLE_RANDOM | IRQF_SHARED,
+			  IRQF_SAMPLE_RANDOM | IRQF_DISABLED,
 			  lp->tx_irq_name, lp);
 	if (err) {
 		free_irq(lp->cfg.rx_irq, lp);
diff --git a/arch/sparc/kernel/of_device_64.c b/arch/sparc/kernel/of_device_64.c
index 881947e59e95..0a6f2d1798d1 100644
--- a/arch/sparc/kernel/of_device_64.c
+++ b/arch/sparc/kernel/of_device_64.c
@@ -104,9 +104,19 @@ static int of_bus_pci_map(u32 *addr, const u32 *range,
 	int i;
 
 	/* Check address type match */
-	if ((addr[0] ^ range[0]) & 0x03000000)
-		return -EINVAL;
+	if (!((addr[0] ^ range[0]) & 0x03000000))
+		goto type_match;
+
+	/* Special exception, we can map a 64-bit address into
+	 * a 32-bit range.
+	 */
+	if ((addr[0] & 0x03000000) == 0x03000000 &&
+	    (range[0] & 0x03000000) == 0x02000000)
+		goto type_match;
+
+	return -EINVAL;
 
+type_match:
 	if (of_out_of_range(addr + 1, range + 1, range + na + pna,
 			    na - 1, ns))
 		return -EINVAL;
diff --git a/arch/sparc/kernel/process_64.c b/arch/sparc/kernel/process_64.c
index 4041f94e7724..3714fdb5b16b 100644
--- a/arch/sparc/kernel/process_64.c
+++ b/arch/sparc/kernel/process_64.c
@@ -365,14 +365,6 @@ void flush_thread(void)
 	struct thread_info *t = current_thread_info();
 	struct mm_struct *mm;
 
-	if (test_ti_thread_flag(t, TIF_ABI_PENDING)) {
-		clear_ti_thread_flag(t, TIF_ABI_PENDING);
-		if (test_ti_thread_flag(t, TIF_32BIT))
-			clear_ti_thread_flag(t, TIF_32BIT);
-		else
-			set_ti_thread_flag(t, TIF_32BIT);
-	}
-
 	mm = t->task->mm;
 	if (mm)
 		tsb_context_switch(mm);
diff --git a/arch/sparc/kernel/prom_common.c b/arch/sparc/kernel/prom_common.c
index 0fb5789d43c8..7b4adbc63b4c 100644
--- a/arch/sparc/kernel/prom_common.c
+++ b/arch/sparc/kernel/prom_common.c
@@ -76,6 +76,7 @@ int of_set_property(struct device_node *dp, const char *name, void *val, int len
 
 	err = -ENODEV;
 
+	mutex_lock(&of_set_property_mutex);
 	write_lock(&devtree_lock);
 	prevp = &dp->properties;
 	while (*prevp) {
@@ -85,9 +86,7 @@ int of_set_property(struct device_node *dp, const char *name, void *val, int len
 			void *old_val = prop->value;
 			int ret;
 
-			mutex_lock(&of_set_property_mutex);
 			ret = prom_setprop(dp->node, name, val, len);
-			mutex_unlock(&of_set_property_mutex);
 
 			err = -EINVAL;
 			if (ret >= 0) {
@@ -106,6 +105,7 @@ int of_set_property(struct device_node *dp, const char *name, void *val, int len
 		prevp = &(*prevp)->next;
 	}
 	write_unlock(&devtree_lock);
+	mutex_unlock(&of_set_property_mutex);
 
 	/* XXX Upate procfs if necessary... */
 
diff --git a/arch/sparc/kernel/setup_32.c b/arch/sparc/kernel/setup_32.c
index 998cadb4e7f2..0ace49b6396b 100644
--- a/arch/sparc/kernel/setup_32.c
+++ b/arch/sparc/kernel/setup_32.c
@@ -263,8 +263,6 @@ void __init setup_arch(char **cmdline_p)
 
 #ifdef CONFIG_DUMMY_CONSOLE
 	conswitchp = &dummy_con;
-#elif defined(CONFIG_PROM_CONSOLE)
-	conswitchp = &prom_con;
 #endif
 	boot_flags_init(*cmdline_p);
 
diff --git a/arch/sparc/kernel/setup_64.c b/arch/sparc/kernel/setup_64.c
index f2bcfd2967d7..21180339cb09 100644
--- a/arch/sparc/kernel/setup_64.c
+++ b/arch/sparc/kernel/setup_64.c
@@ -295,8 +295,6 @@ void __init setup_arch(char **cmdline_p)
 
 #ifdef CONFIG_DUMMY_CONSOLE
 	conswitchp = &dummy_con;
-#elif defined(CONFIG_PROM_CONSOLE)
-	conswitchp = &prom_con;
 #endif
 
 	idprom_init();
diff --git a/arch/sparc/kernel/visemul.c b/arch/sparc/kernel/visemul.c
index b956fd71c131..d231cbd5c526 100644
--- a/arch/sparc/kernel/visemul.c
+++ b/arch/sparc/kernel/visemul.c
@@ -617,7 +617,7 @@ static void pmul(struct pt_regs *regs, unsigned int insn, unsigned int opf)
 		rs2 = fps_regval(f, RS2(insn));
 
 		rd_val = 0;
-		src2 = (rs2 >> (opf == FMUL8x16AU_OPF) ? 16 : 0);
+		src2 = rs2 >> (opf == FMUL8x16AU_OPF ? 16 : 0);
 		for (byte = 0; byte < 4; byte++) {
 			u16 src1 = (rs1 >> (byte * 8)) & 0x00ff;
 			u32 prod = src1 * src2;
diff --git a/arch/sparc/lib/mcount.S b/arch/sparc/lib/mcount.S
index 7ce9c65f3592..24b8b12deed2 100644
--- a/arch/sparc/lib/mcount.S
+++ b/arch/sparc/lib/mcount.S
@@ -64,8 +64,9 @@ mcount:
 2:	 sethi		%hi(softirq_stack), %g3
 	or		%g3, %lo(softirq_stack), %g3
 	ldx		[%g3 + %g1], %g7
+	sub		%g7, STACK_BIAS, %g7
 	cmp		%sp, %g7
-	bleu,pt		%xcc, 2f
+	bleu,pt		%xcc, 3f
 	 sethi		%hi(THREAD_SIZE), %g3
 	add		%g7, %g3, %g7
 	cmp		%sp, %g7
@@ -75,7 +76,7 @@ mcount:
 	 * again, we are already trying to output the stack overflow
 	 * message.
 	 */
-	sethi		%hi(ovstack), %g7		! cant move to panic stack fast enough
+3:	sethi		%hi(ovstack), %g7		! cant move to panic stack fast enough
 	 or		%g7, %lo(ovstack), %g7
 	add		%g7, OVSTACKSIZE, %g3
 	sub		%g3, STACK_BIAS + 192, %g3
diff --git a/arch/sparc/mm/init_64.h b/arch/sparc/mm/init_64.h
index c2f772dbd556..77d1b313e344 100644
--- a/arch/sparc/mm/init_64.h
+++ b/arch/sparc/mm/init_64.h
@@ -45,7 +45,7 @@ extern void free_initmem(void);
 #define VMEMMAP_ALIGN(x)	(((x)+VMEMMAP_CHUNK-1UL)&VMEMMAP_CHUNK_MASK)
 
 #define VMEMMAP_SIZE	((((1UL << MAX_PHYSADDR_BITS) >> PAGE_SHIFT) * \
-			  sizeof(struct page *)) >> VMEMMAP_CHUNK_SHIFT)
+			  sizeof(struct page)) >> VMEMMAP_CHUNK_SHIFT)
 extern unsigned long vmemmap_table[VMEMMAP_SIZE];
 #endif
 
diff --git a/arch/um/Makefile b/arch/um/Makefile
index 0728def32234..fc633dbacf84 100644
--- a/arch/um/Makefile
+++ b/arch/um/Makefile
@@ -96,11 +96,10 @@ CFLAGS_NO_HARDENING := $(call cc-option, -fno-PIC,) $(call cc-option, -fno-pic,)
 	$(call cc-option, -fno-stack-protector,) \
 	$(call cc-option, -fno-stack-protector-all,)
 
-CONFIG_KERNEL_STACK_ORDER ?= 2
-STACK_SIZE := $(shell echo $$[ 4096 * (1 << $(CONFIG_KERNEL_STACK_ORDER)) ] )
-
-CPPFLAGS_vmlinux.lds = -U$(SUBARCH) -DSTART=$(START) -DELF_ARCH=$(ELF_ARCH) \
-	-DELF_FORMAT="$(ELF_FORMAT)" -DKERNEL_STACK_SIZE=$(STACK_SIZE)
+# Options used by linker script
+export LDS_START      := $(START)
+export LDS_ELF_ARCH   := $(ELF_ARCH)
+export LDS_ELF_FORMAT := $(ELF_FORMAT)
 
 # The wrappers will select whether using "malloc" or the kernel allocator.
 LINK_WRAPS = -Wl,--wrap,malloc -Wl,--wrap,free -Wl,--wrap,calloc
diff --git a/arch/um/kernel/Makefile b/arch/um/kernel/Makefile
index 388ec0a3ea9b..1119233597a1 100644
--- a/arch/um/kernel/Makefile
+++ b/arch/um/kernel/Makefile
@@ -3,6 +3,9 @@
 # Licensed under the GPL
 #
 
+CPPFLAGS_vmlinux.lds := -U$(SUBARCH) -DSTART=$(LDS_START) \
+                        -DELF_ARCH=$(LDS_ELF_ARCH)        \
+                        -DELF_FORMAT=$(LDS_ELF_FORMAT)
 extra-y := vmlinux.lds
 clean-files :=
 
diff --git a/arch/um/kernel/vmlinux.lds.S b/arch/um/kernel/vmlinux.lds.S
index f8aeb448aab6..16e49bfa2b42 100644
--- a/arch/um/kernel/vmlinux.lds.S
+++ b/arch/um/kernel/vmlinux.lds.S
@@ -1,3 +1,6 @@
+
+KERNEL_STACK_SIZE = 4096 * (1 << CONFIG_KERNEL_STACK_ORDER);
+
 #ifdef CONFIG_LD_SCRIPT_STATIC
 #include "uml.lds.S"
 #else
diff --git a/arch/x86/ia32/ia32_aout.c b/arch/x86/ia32/ia32_aout.c
index 2a4d073d2cf1..14531abdd0ce 100644
--- a/arch/x86/ia32/ia32_aout.c
+++ b/arch/x86/ia32/ia32_aout.c
@@ -308,14 +308,15 @@ static int load_aout_binary(struct linux_binprm *bprm, struct pt_regs *regs)
 	if (retval)
 		return retval;
 
-	regs->cs = __USER32_CS;
-	regs->r8 = regs->r9 = regs->r10 = regs->r11 = regs->r12 =
-		regs->r13 = regs->r14 = regs->r15 = 0;
-
 	/* OK, This is the point of no return */
 	set_personality(PER_LINUX);
 	set_thread_flag(TIF_IA32);
-	clear_thread_flag(TIF_ABI_PENDING);
+
+	setup_new_exec(bprm);
+
+	regs->cs = __USER32_CS;
+	regs->r8 = regs->r9 = regs->r10 = regs->r11 = regs->r12 =
+		regs->r13 = regs->r14 = regs->r15 = 0;
 
 	current->mm->end_code = ex.a_text +
 		(current->mm->start_code = N_TXTADDR(ex));
@@ -326,7 +327,6 @@ static int load_aout_binary(struct linux_binprm *bprm, struct pt_regs *regs)
 	current->mm->free_area_cache = TASK_UNMAPPED_BASE;
 	current->mm->cached_hole_size = 0;
 
-	current->mm->mmap = NULL;
 	install_exec_creds(bprm);
 	current->flags &= ~PF_FORKNOEXEC;
 
diff --git a/arch/x86/ia32/ia32entry.S b/arch/x86/ia32/ia32entry.S
index e590261ba059..b09502da8d3f 100644
--- a/arch/x86/ia32/ia32entry.S
+++ b/arch/x86/ia32/ia32entry.S
@@ -21,8 +21,8 @@
 #define __AUDIT_ARCH_LE	   0x40000000
 
 #ifndef CONFIG_AUDITSYSCALL
-#define sysexit_audit int_ret_from_sys_call
-#define sysretl_audit int_ret_from_sys_call
+#define sysexit_audit ia32_ret_from_sys_call
+#define sysretl_audit ia32_ret_from_sys_call
 #endif
 
 #define IA32_NR_syscalls ((ia32_syscall_end - ia32_sys_call_table)/8)
@@ -39,12 +39,12 @@
 	.endm 
 
 	/* clobbers %eax */	
-	.macro  CLEAR_RREGS _r9=rax
+	.macro  CLEAR_RREGS offset=0, _r9=rax
 	xorl 	%eax,%eax
-	movq	%rax,R11(%rsp)
-	movq	%rax,R10(%rsp)
-	movq	%\_r9,R9(%rsp)
-	movq	%rax,R8(%rsp)
+	movq	%rax,\offset+R11(%rsp)
+	movq	%rax,\offset+R10(%rsp)
+	movq	%\_r9,\offset+R9(%rsp)
+	movq	%rax,\offset+R8(%rsp)
 	.endm
 
 	/*
@@ -172,6 +172,10 @@ sysexit_from_sys_call:
 	movl	RIP-R11(%rsp),%edx		/* User %eip */
 	CFI_REGISTER rip,rdx
 	RESTORE_ARGS 1,24,1,1,1,1
+	xorq	%r8,%r8
+	xorq	%r9,%r9
+	xorq	%r10,%r10
+	xorq	%r11,%r11
 	popfq
 	CFI_ADJUST_CFA_OFFSET -8
 	/*CFI_RESTORE rflags*/
@@ -200,9 +204,9 @@ sysexit_from_sys_call:
 	movl RDI-ARGOFFSET(%rsp),%r8d	/* reload 5th syscall arg */
 	.endm
 
-	.macro auditsys_exit exit,ebpsave=RBP
+	.macro auditsys_exit exit
 	testl $(_TIF_ALLWORK_MASK & ~_TIF_SYSCALL_AUDIT),TI_flags(%r10)
-	jnz int_ret_from_sys_call
+	jnz ia32_ret_from_sys_call
 	TRACE_IRQS_ON
 	sti
 	movl %eax,%esi		/* second arg, syscall return value */
@@ -213,13 +217,13 @@ sysexit_from_sys_call:
 	call audit_syscall_exit
 	GET_THREAD_INFO(%r10)
 	movl RAX-ARGOFFSET(%rsp),%eax	/* reload syscall return value */
-	movl \ebpsave-ARGOFFSET(%rsp),%ebp /* reload user register value */
 	movl $(_TIF_ALLWORK_MASK & ~_TIF_SYSCALL_AUDIT),%edi
 	cli
 	TRACE_IRQS_OFF
 	testl %edi,TI_flags(%r10)
-	jnz int_with_check
-	jmp \exit
+	jz \exit
+	CLEAR_RREGS -ARGOFFSET
+	jmp int_with_check
 	.endm
 
 sysenter_auditsys:
@@ -329,6 +333,9 @@ sysretl_from_sys_call:
 	CFI_REGISTER rip,rcx
 	movl EFLAGS-ARGOFFSET(%rsp),%r11d	
 	/*CFI_REGISTER rflags,r11*/
+	xorq	%r10,%r10
+	xorq	%r9,%r9
+	xorq	%r8,%r8
 	TRACE_IRQS_ON
 	movl RSP-ARGOFFSET(%rsp),%esp
 	CFI_RESTORE rsp
@@ -343,7 +350,7 @@ cstar_auditsys:
 	jmp cstar_dispatch
 
 sysretl_audit:
-	auditsys_exit sysretl_from_sys_call, RCX /* user %ebp in RCX slot */
+	auditsys_exit sysretl_from_sys_call
 #endif
 
 cstar_tracesys:
@@ -353,7 +360,7 @@ cstar_tracesys:
 #endif
 	xchgl %r9d,%ebp
 	SAVE_REST
-	CLEAR_RREGS r9
+	CLEAR_RREGS 0, r9
 	movq $-ENOSYS,RAX(%rsp)	/* ptrace can change this for a bad syscall */
 	movq %rsp,%rdi        /* &pt_regs -> arg1 */
 	call syscall_trace_enter
@@ -425,6 +432,8 @@ ia32_do_call:
 	call *ia32_sys_call_table(,%rax,8) # xxx: rip relative
 ia32_sysret:
 	movq %rax,RAX-ARGOFFSET(%rsp)
+ia32_ret_from_sys_call:
+	CLEAR_RREGS -ARGOFFSET
 	jmp int_ret_from_sys_call 
 
 ia32_tracesys:			 
@@ -442,8 +451,8 @@ END(ia32_syscall)
 
 ia32_badsys:
 	movq $0,ORIG_RAX-ARGOFFSET(%rsp)
-	movq $-ENOSYS,RAX-ARGOFFSET(%rsp)
-	jmp int_ret_from_sys_call
+	movq $-ENOSYS,%rax
+	jmp ia32_sysret
 
 quiet_ni_syscall:
 	movq $-ENOSYS,%rax
diff --git a/arch/x86/include/asm/amd_iommu.h b/arch/x86/include/asm/amd_iommu.h
index bdf96f119f06..9dbd4030f0cd 100644
--- a/arch/x86/include/asm/amd_iommu.h
+++ b/arch/x86/include/asm/amd_iommu.h
@@ -30,6 +30,7 @@ extern irqreturn_t amd_iommu_int_handler(int irq, void *data);
 extern void amd_iommu_flush_all_domains(void);
 extern void amd_iommu_flush_all_devices(void);
 extern void amd_iommu_shutdown(void);
+extern void amd_iommu_apply_erratum_63(u16 devid);
 #else
 static inline int amd_iommu_init(void) { return -ENODEV; }
 static inline void amd_iommu_detect(void) { }
diff --git a/arch/x86/include/asm/checksum_32.h b/arch/x86/include/asm/checksum_32.h
index 7c5ef8b14d92..46fc474fd819 100644
--- a/arch/x86/include/asm/checksum_32.h
+++ b/arch/x86/include/asm/checksum_32.h
@@ -161,7 +161,8 @@ static inline __sum16 csum_ipv6_magic(const struct in6_addr *saddr,
 	    "adcl $0, %0	;\n"
 	    : "=&r" (sum)
 	    : "r" (saddr), "r" (daddr),
-	      "r" (htonl(len)), "r" (htonl(proto)), "0" (sum));
+	      "r" (htonl(len)), "r" (htonl(proto)), "0" (sum)
+	    : "memory");
 
 	return csum_fold(sum);
 }
diff --git a/arch/x86/include/asm/elf.h b/arch/x86/include/asm/elf.h
index 83c1bc8d2e8a..8ac9d9ae129e 100644
--- a/arch/x86/include/asm/elf.h
+++ b/arch/x86/include/asm/elf.h
@@ -197,14 +197,8 @@ do {							\
 	set_fs(USER_DS);				\
 } while (0)
 
-#define COMPAT_SET_PERSONALITY(ex)			\
-do {							\
-	if (test_thread_flag(TIF_IA32))			\
-		clear_thread_flag(TIF_ABI_PENDING);	\
-	else						\
-		set_thread_flag(TIF_ABI_PENDING);	\
-	current->personality |= force_personality32;	\
-} while (0)
+void set_personality_ia32(void);
+#define COMPAT_SET_PERSONALITY(ex) set_personality_ia32()
 
 #define COMPAT_ELF_PLATFORM			("i686")
 
@@ -299,6 +293,8 @@ do {									\
 
 #ifdef CONFIG_X86_32
 
+#define STACK_RND_MASK (0x7ff)
+
 #define VDSO_HIGH_BASE		(__fix_to_virt(FIX_VDSO))
 
 #define ARCH_DLINFO		ARCH_DLINFO_IA32(vdso_enabled)
diff --git a/arch/x86/include/asm/fixmap.h b/arch/x86/include/asm/fixmap.h
index 7b2d71df39a6..ebd010795555 100644
--- a/arch/x86/include/asm/fixmap.h
+++ b/arch/x86/include/asm/fixmap.h
@@ -82,6 +82,9 @@ enum fixed_addresses {
 #endif
 	FIX_DBGP_BASE,
 	FIX_EARLYCON_MEM_BASE,
+#ifdef CONFIG_PROVIDE_OHCI1394_DMA_INIT
+	FIX_OHCI1394_BASE,
+#endif
 #ifdef CONFIG_X86_LOCAL_APIC
 	FIX_APIC_BASE,	/* local (CPU) APIC) -- required for SMP or not */
 #endif
@@ -126,9 +129,6 @@ enum fixed_addresses {
 	FIX_BTMAP_END = __end_of_permanent_fixed_addresses + 256 -
 			(__end_of_permanent_fixed_addresses & 255),
 	FIX_BTMAP_BEGIN = FIX_BTMAP_END + NR_FIX_BTMAPS*FIX_BTMAPS_SLOTS - 1,
-#ifdef CONFIG_PROVIDE_OHCI1394_DMA_INIT
-	FIX_OHCI1394_BASE,
-#endif
 #ifdef CONFIG_X86_32
 	FIX_WP_TEST,
 #endif
diff --git a/arch/x86/include/asm/io_apic.h b/arch/x86/include/asm/io_apic.h
index 330ee807f89e..e9e97a371ed4 100644
--- a/arch/x86/include/asm/io_apic.h
+++ b/arch/x86/include/asm/io_apic.h
@@ -159,6 +159,7 @@ extern int io_apic_get_redir_entries(int ioapic);
 struct io_apic_irq_attr;
 extern int io_apic_set_pci_routing(struct device *dev, int irq,
 		 struct io_apic_irq_attr *irq_attr);
+void setup_IO_APIC_irq_extra(u32 gsi);
 extern int (*ioapic_renumber_irq)(int ioapic, int irq);
 extern void ioapic_init_mappings(void);
 extern void ioapic_insert_resources(void);
diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h
index eabdc1cfab5c..68d16d2650a2 100644
--- a/arch/x86/include/asm/kvm_host.h
+++ b/arch/x86/include/asm/kvm_host.h
@@ -618,6 +618,7 @@ void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr);
 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code);
 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long cr2,
 			   u32 error_code);
+bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl);
 
 int kvm_pic_set_irq(void *opaque, int irq, int level);
 
diff --git a/arch/x86/include/asm/kvm_x86_emulate.h b/arch/x86/include/asm/kvm_x86_emulate.h
index b7ed2c423116..7c18e1230f54 100644
--- a/arch/x86/include/asm/kvm_x86_emulate.h
+++ b/arch/x86/include/asm/kvm_x86_emulate.h
@@ -129,7 +129,7 @@ struct decode_cache {
 	u8 seg_override;
 	unsigned int d;
 	unsigned long regs[NR_VCPU_REGS];
-	unsigned long eip;
+	unsigned long eip, eip_orig;
 	/* modrm */
 	u8 modrm;
 	u8 modrm_mod;
diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
index 5cdd8d100ec9..1d16c972e2a0 100644
--- a/arch/x86/include/asm/mce.h
+++ b/arch/x86/include/asm/mce.h
@@ -214,5 +214,11 @@ void mce_log_therm_throt_event(__u64 status);
 static inline void mce_log_therm_throt_event(__u64 status) {}
 #endif
 
+#ifdef CONFIG_X86_THERMAL_VECTOR
+extern void mcheck_intel_therm_init(void);
+#else
+static inline void mcheck_intel_therm_init(void) { }
+#endif
+
 #endif /* __KERNEL__ */
 #endif /* _ASM_X86_MCE_H */
diff --git a/arch/x86/include/asm/paravirt.h b/arch/x86/include/asm/paravirt.h
index 4fb37c8a0832..43b8adba7d41 100644
--- a/arch/x86/include/asm/paravirt.h
+++ b/arch/x86/include/asm/paravirt.h
@@ -528,10 +528,11 @@ int paravirt_disable_iospace(void);
 #define EXTRA_CLOBBERS
 #define VEXTRA_CLOBBERS
 #else  /* CONFIG_X86_64 */
+/* [re]ax isn't an arg, but the return val */
 #define PVOP_VCALL_ARGS					\
 	unsigned long __edi = __edi, __esi = __esi,	\
-		__edx = __edx, __ecx = __ecx
-#define PVOP_CALL_ARGS		PVOP_VCALL_ARGS, __eax
+		__edx = __edx, __ecx = __ecx, __eax = __eax
+#define PVOP_CALL_ARGS		PVOP_VCALL_ARGS
 
 #define PVOP_CALL_ARG1(x)		"D" ((unsigned long)(x))
 #define PVOP_CALL_ARG2(x)		"S" ((unsigned long)(x))
@@ -543,6 +544,7 @@ int paravirt_disable_iospace(void);
 				"=c" (__ecx)
 #define PVOP_CALL_CLOBBERS	PVOP_VCALL_CLOBBERS, "=a" (__eax)
 
+/* void functions are still allowed [re]ax for scratch */
 #define PVOP_VCALLEE_CLOBBERS	"=a" (__eax)
 #define PVOP_CALLEE_CLOBBERS	PVOP_VCALLEE_CLOBBERS
 
@@ -617,8 +619,8 @@ int paravirt_disable_iospace(void);
 		       VEXTRA_CLOBBERS,					\
 		       pre, post, ##__VA_ARGS__)
 
-#define __PVOP_VCALLEESAVE(rettype, op, pre, post, ...)			\
-	____PVOP_CALL(rettype, op.func, CLBR_RET_REG,			\
+#define __PVOP_VCALLEESAVE(op, pre, post, ...)				\
+	____PVOP_VCALL(op.func, CLBR_RET_REG,				\
 		      PVOP_VCALLEE_CLOBBERS, ,				\
 		      pre, post, ##__VA_ARGS__)
 
@@ -1565,42 +1567,22 @@ extern struct paravirt_patch_site __parainstructions[],
 
 static inline unsigned long __raw_local_save_flags(void)
 {
-	unsigned long f;
-
-	asm volatile(paravirt_alt(PARAVIRT_CALL)
-		     : "=a"(f)
-		     : paravirt_type(pv_irq_ops.save_fl),
-		       paravirt_clobber(CLBR_EAX)
-		     : "memory", "cc");
-	return f;
+	return PVOP_CALLEE0(unsigned long, pv_irq_ops.save_fl);
 }
 
 static inline void raw_local_irq_restore(unsigned long f)
 {
-	asm volatile(paravirt_alt(PARAVIRT_CALL)
-		     : "=a"(f)
-		     : PV_FLAGS_ARG(f),
-		       paravirt_type(pv_irq_ops.restore_fl),
-		       paravirt_clobber(CLBR_EAX)
-		     : "memory", "cc");
+	PVOP_VCALLEE1(pv_irq_ops.restore_fl, f);
 }
 
 static inline void raw_local_irq_disable(void)
 {
-	asm volatile(paravirt_alt(PARAVIRT_CALL)
-		     :
-		     : paravirt_type(pv_irq_ops.irq_disable),
-		       paravirt_clobber(CLBR_EAX)
-		     : "memory", "eax", "cc");
+	PVOP_VCALLEE0(pv_irq_ops.irq_disable);
 }
 
 static inline void raw_local_irq_enable(void)
 {
-	asm volatile(paravirt_alt(PARAVIRT_CALL)
-		     :
-		     : paravirt_type(pv_irq_ops.irq_enable),
-		       paravirt_clobber(CLBR_EAX)
-		     : "memory", "eax", "cc");
+	PVOP_VCALLEE0(pv_irq_ops.irq_enable);
 }
 
 static inline unsigned long __raw_local_irq_save(void)
diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index c7768269b1cf..70c6a939031b 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -179,7 +179,7 @@ static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
 				unsigned int *ecx, unsigned int *edx)
 {
 	/* ecx is often an input as well as an output. */
-	asm("cpuid"
+	asm volatile("cpuid"
 	    : "=a" (*eax),
 	      "=b" (*ebx),
 	      "=c" (*ecx),
@@ -403,7 +403,17 @@ extern unsigned long kernel_eflags;
 extern asmlinkage void ignore_sysret(void);
 #else	/* X86_64 */
 #ifdef CONFIG_CC_STACKPROTECTOR
-DECLARE_PER_CPU(unsigned long, stack_canary);
+/*
+ * Make sure stack canary segment base is cached-aligned:
+ *   "For Intel Atom processors, avoid non zero segment base address
+ *    that is not aligned to cache line boundary at all cost."
+ * (Optim Ref Manual Assembly/Compiler Coding Rule 15.)
+ */
+struct stack_canary {
+	char __pad[20];		/* canary at %gs:20 */
+	unsigned long canary;
+};
+DECLARE_PER_CPU(struct stack_canary, stack_canary) ____cacheline_aligned;
 #endif
 #endif	/* X86_64 */
 
diff --git a/arch/x86/include/asm/stackprotector.h b/arch/x86/include/asm/stackprotector.h
index c2d742c6e15f..decad975e024 100644
--- a/arch/x86/include/asm/stackprotector.h
+++ b/arch/x86/include/asm/stackprotector.h
@@ -78,14 +78,14 @@ static __always_inline void boot_init_stack_canary(void)
 #ifdef CONFIG_X86_64
 	percpu_write(irq_stack_union.stack_canary, canary);
 #else
-	percpu_write(stack_canary, canary);
+	percpu_write(stack_canary.canary, canary);
 #endif
 }
 
 static inline void setup_stack_canary_segment(int cpu)
 {
 #ifdef CONFIG_X86_32
-	unsigned long canary = (unsigned long)&per_cpu(stack_canary, cpu) - 20;
+	unsigned long canary = (unsigned long)&per_cpu(stack_canary, cpu);
 	struct desc_struct *gdt_table = get_cpu_gdt_table(cpu);
 	struct desc_struct desc;
 
diff --git a/arch/x86/include/asm/system.h b/arch/x86/include/asm/system.h
index 643c59b4bc6e..5bd119be1142 100644
--- a/arch/x86/include/asm/system.h
+++ b/arch/x86/include/asm/system.h
@@ -31,7 +31,7 @@ void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p,
 	"movl %P[task_canary](%[next]), %%ebx\n\t"			\
 	"movl %%ebx, "__percpu_arg([stack_canary])"\n\t"
 #define __switch_canary_oparam						\
-	, [stack_canary] "=m" (per_cpu_var(stack_canary))
+	, [stack_canary] "=m" (per_cpu_var(stack_canary.canary))
 #define __switch_canary_iparam						\
 	, [task_canary] "i" (offsetof(struct task_struct, stack_canary))
 #else	/* CC_STACKPROTECTOR */
diff --git a/arch/x86/include/asm/thread_info.h b/arch/x86/include/asm/thread_info.h
index fad7d40b75f8..e4bcf0c00268 100644
--- a/arch/x86/include/asm/thread_info.h
+++ b/arch/x86/include/asm/thread_info.h
@@ -86,7 +86,6 @@ struct thread_info {
 #define TIF_NOTSC		16	/* TSC is not accessible in userland */
 #define TIF_IA32		17	/* 32bit process */
 #define TIF_FORK		18	/* ret_from_fork */
-#define TIF_ABI_PENDING		19
 #define TIF_MEMDIE		20
 #define TIF_DEBUG		21	/* uses debug registers */
 #define TIF_IO_BITMAP		22	/* uses I/O bitmap */
@@ -110,7 +109,6 @@ struct thread_info {
 #define _TIF_NOTSC		(1 << TIF_NOTSC)
 #define _TIF_IA32		(1 << TIF_IA32)
 #define _TIF_FORK		(1 << TIF_FORK)
-#define _TIF_ABI_PENDING	(1 << TIF_ABI_PENDING)
 #define _TIF_DEBUG		(1 << TIF_DEBUG)
 #define _TIF_IO_BITMAP		(1 << TIF_IO_BITMAP)
 #define _TIF_FREEZE		(1 << TIF_FREEZE)
diff --git a/arch/x86/include/asm/uv/uv_hub.h b/arch/x86/include/asm/uv/uv_hub.h
index 77a68505419a..ca1fe396ec0d 100644
--- a/arch/x86/include/asm/uv/uv_hub.h
+++ b/arch/x86/include/asm/uv/uv_hub.h
@@ -18,6 +18,8 @@
 #include <asm/types.h>
 #include <asm/percpu.h>
 #include <asm/uv/uv_mmrs.h>
+#include <asm/irq_vectors.h>
+#include <asm/io_apic.h>
 
 
 /*
@@ -420,9 +422,14 @@ static inline void uv_set_cpu_scir_bits(int cpu, unsigned char value)
 static inline void uv_hub_send_ipi(int pnode, int apicid, int vector)
 {
 	unsigned long val;
+	unsigned long dmode = dest_Fixed;
+
+	if (vector == NMI_VECTOR)
+		dmode = dest_NMI;
 
 	val = (1UL << UVH_IPI_INT_SEND_SHFT) |
-			((apicid & 0x3f) << UVH_IPI_INT_APIC_ID_SHFT) |
+			((apicid) << UVH_IPI_INT_APIC_ID_SHFT) |
+			(dmode << UVH_IPI_INT_DELIVERY_MODE_SHFT) |
 			(vector << UVH_IPI_INT_VECTOR_SHFT);
 	uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
 }
diff --git a/arch/x86/kernel/acpi/boot.c b/arch/x86/kernel/acpi/boot.c
index 6b8ca3a0285d..36411c325b8c 100644
--- a/arch/x86/kernel/acpi/boot.c
+++ b/arch/x86/kernel/acpi/boot.c
@@ -446,6 +446,12 @@ void __init acpi_pic_sci_set_trigger(unsigned int irq, u16 trigger)
 int acpi_gsi_to_irq(u32 gsi, unsigned int *irq)
 {
 	*irq = gsi;
+
+#ifdef CONFIG_X86_IO_APIC
+	if (acpi_irq_model == ACPI_IRQ_MODEL_IOAPIC)
+		setup_IO_APIC_irq_extra(gsi);
+#endif
+
 	return 0;
 }
 
@@ -473,7 +479,8 @@ int acpi_register_gsi(struct device *dev, u32 gsi, int trigger, int polarity)
 		plat_gsi = mp_register_gsi(dev, gsi, trigger, polarity);
 	}
 #endif
-	acpi_gsi_to_irq(plat_gsi, &irq);
+	irq = plat_gsi;
+
 	return irq;
 }
 
diff --git a/arch/x86/kernel/acpi/cstate.c b/arch/x86/kernel/acpi/cstate.c
index 8c44c232efcb..2e837f5080fe 100644
--- a/arch/x86/kernel/acpi/cstate.c
+++ b/arch/x86/kernel/acpi/cstate.c
@@ -48,7 +48,7 @@ void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flags,
 	 * P4, Core and beyond CPUs
 	 */
 	if (c->x86_vendor == X86_VENDOR_INTEL &&
-	    (c->x86 > 0x6 || (c->x86 == 6 && c->x86_model >= 14)))
+	    (c->x86 > 0xf || (c->x86 == 6 && c->x86_model >= 0x0f)))
 			flags->bm_control = 0;
 }
 EXPORT_SYMBOL(acpi_processor_power_init_bm_check);
diff --git a/arch/x86/kernel/acpi/processor.c b/arch/x86/kernel/acpi/processor.c
index d296f4a195c9..d85d1b2432ba 100644
--- a/arch/x86/kernel/acpi/processor.c
+++ b/arch/x86/kernel/acpi/processor.c
@@ -79,7 +79,8 @@ void arch_acpi_processor_init_pdc(struct acpi_processor *pr)
 	struct cpuinfo_x86 *c = &cpu_data(pr->id);
 
 	pr->pdc = NULL;
-	if (c->x86_vendor == X86_VENDOR_INTEL)
+	if (c->x86_vendor == X86_VENDOR_INTEL ||
+	    c->x86_vendor == X86_VENDOR_CENTAUR)
 		init_intel_pdc(pr, c);
 
 	return;
diff --git a/arch/x86/kernel/amd_iommu.c b/arch/x86/kernel/amd_iommu.c
index 6c99f5037801..d7be38c297b0 100644
--- a/arch/x86/kernel/amd_iommu.c
+++ b/arch/x86/kernel/amd_iommu.c
@@ -485,8 +485,6 @@ void amd_iommu_flush_all_devices(void)
 	int i;
 
 	for (i = 0; i <= amd_iommu_last_bdf; ++i) {
-		if (amd_iommu_pd_table[i] == NULL)
-			continue;
 
 		iommu = amd_iommu_rlookup_table[i];
 		if (!iommu)
@@ -1114,6 +1112,8 @@ static void __detach_device(struct protection_domain *domain, u16 devid)
 	amd_iommu_dev_table[devid].data[1] = 0;
 	amd_iommu_dev_table[devid].data[2] = 0;
 
+	amd_iommu_apply_erratum_63(devid);
+
 	/* decrease reference counter */
 	domain->dev_cnt -= 1;
 
@@ -1873,10 +1873,10 @@ static void prealloc_protection_domains(void)
 	struct pci_dev *dev = NULL;
 	struct dma_ops_domain *dma_dom;
 	struct amd_iommu *iommu;
-	u16 devid;
+	u16 devid, __devid;
 
 	while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
-		devid = calc_devid(dev->bus->number, dev->devfn);
+		__devid = devid = calc_devid(dev->bus->number, dev->devfn);
 		if (devid > amd_iommu_last_bdf)
 			continue;
 		devid = amd_iommu_alias_table[devid];
@@ -1891,6 +1891,10 @@ static void prealloc_protection_domains(void)
 		init_unity_mappings_for_device(dma_dom, devid);
 		dma_dom->target_dev = devid;
 
+		attach_device(iommu, &dma_dom->domain, devid);
+		if (__devid != devid)
+			attach_device(iommu, &dma_dom->domain, __devid);
+
 		list_add_tail(&dma_dom->list, &iommu_pd_list);
 	}
 }
diff --git a/arch/x86/kernel/amd_iommu_init.c b/arch/x86/kernel/amd_iommu_init.c
index c1b17e97252e..ecd90502899c 100644
--- a/arch/x86/kernel/amd_iommu_init.c
+++ b/arch/x86/kernel/amd_iommu_init.c
@@ -240,7 +240,7 @@ static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit)
 	writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
 }
 
-static void __init iommu_feature_disable(struct amd_iommu *iommu, u8 bit)
+static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit)
 {
 	u32 ctrl;
 
@@ -509,6 +509,26 @@ static void set_dev_entry_bit(u16 devid, u8 bit)
 	amd_iommu_dev_table[devid].data[i] |= (1 << _bit);
 }
 
+static int get_dev_entry_bit(u16 devid, u8 bit)
+{
+	int i = (bit >> 5) & 0x07;
+	int _bit = bit & 0x1f;
+
+	return (amd_iommu_dev_table[devid].data[i] & (1 << _bit)) >> _bit;
+}
+
+
+void amd_iommu_apply_erratum_63(u16 devid)
+{
+	int sysmgt;
+
+	sysmgt = get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1) |
+		 (get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2) << 1);
+
+	if (sysmgt == 0x01)
+		set_dev_entry_bit(devid, DEV_ENTRY_IW);
+}
+
 /* Writes the specific IOMMU for a device into the rlookup table */
 static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid)
 {
@@ -537,6 +557,8 @@ static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu,
 	if (flags & ACPI_DEVFLAG_LINT1)
 		set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS);
 
+	amd_iommu_apply_erratum_63(devid);
+
 	set_iommu_for_device(iommu, devid);
 }
 
@@ -893,7 +915,7 @@ static int __init init_iommu_all(struct acpi_table_header *table)
  *
  ****************************************************************************/
 
-static int __init iommu_setup_msi(struct amd_iommu *iommu)
+static int iommu_setup_msi(struct amd_iommu *iommu)
 {
 	int r;
 
diff --git a/arch/x86/kernel/apic/apic_flat_64.c b/arch/x86/kernel/apic/apic_flat_64.c
index d0c99abc26c3..873f81f0bbd8 100644
--- a/arch/x86/kernel/apic/apic_flat_64.c
+++ b/arch/x86/kernel/apic/apic_flat_64.c
@@ -240,6 +240,11 @@ static int physflat_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
 		printk(KERN_DEBUG "system APIC only can use physical flat");
 		return 1;
 	}
+
+	if (!strncmp(oem_id, "IBM", 3) && !strncmp(oem_table_id, "EXA", 3)) {
+		printk(KERN_DEBUG "IBM Summit detected, will use apic physical");
+		return 1;
+	}
 #endif
 
 	return 0;
diff --git a/arch/x86/kernel/apic/es7000_32.c b/arch/x86/kernel/apic/es7000_32.c
index 8952a5890281..89174f847b49 100644
--- a/arch/x86/kernel/apic/es7000_32.c
+++ b/arch/x86/kernel/apic/es7000_32.c
@@ -167,7 +167,7 @@ static int es7000_apic_is_cluster(void)
 {
 	/* MPENTIUMIII */
 	if (boot_cpu_data.x86 == 6 &&
-	    (boot_cpu_data.x86_model >= 7 || boot_cpu_data.x86_model <= 11))
+	    (boot_cpu_data.x86_model >= 7 && boot_cpu_data.x86_model <= 11))
 		return 1;
 
 	return 0;
diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c
index d2ed6c5ddc80..938b69d54a25 100644
--- a/arch/x86/kernel/apic/io_apic.c
+++ b/arch/x86/kernel/apic/io_apic.c
@@ -1558,6 +1558,56 @@ static void __init setup_IO_APIC_irqs(void)
 }
 
 /*
+ * for the gsit that is not in first ioapic
+ * but could not use acpi_register_gsi()
+ * like some special sci in IBM x3330
+ */
+void setup_IO_APIC_irq_extra(u32 gsi)
+{
+	int apic_id = 0, pin, idx, irq;
+	int node = cpu_to_node(boot_cpu_id);
+	struct irq_desc *desc;
+	struct irq_cfg *cfg;
+
+	/*
+	 * Convert 'gsi' to 'ioapic.pin'.
+	 */
+	apic_id = mp_find_ioapic(gsi);
+	if (apic_id < 0)
+		return;
+
+	pin = mp_find_ioapic_pin(apic_id, gsi);
+	idx = find_irq_entry(apic_id, pin, mp_INT);
+	if (idx == -1)
+		return;
+
+	irq = pin_2_irq(idx, apic_id, pin);
+#ifdef CONFIG_SPARSE_IRQ
+	desc = irq_to_desc(irq);
+	if (desc)
+		return;
+#endif
+	desc = irq_to_desc_alloc_node(irq, node);
+	if (!desc) {
+		printk(KERN_INFO "can not get irq_desc for %d\n", irq);
+		return;
+	}
+
+	cfg = desc->chip_data;
+	add_pin_to_irq_node(cfg, node, apic_id, pin);
+
+	if (test_bit(pin, mp_ioapic_routing[apic_id].pin_programmed)) {
+		pr_debug("Pin %d-%d already programmed\n",
+			 mp_ioapics[apic_id].apicid, pin);
+		return;
+	}
+	set_bit(pin, mp_ioapic_routing[apic_id].pin_programmed);
+
+	setup_IO_APIC_irq(apic_id, pin, irq, desc,
+			irq_trigger(idx), irq_polarity(idx));
+}
+
+/*
  * Set up the timer pin, possibly with the 8259A-master behind.
  */
 static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin,
diff --git a/arch/x86/kernel/apic/x2apic_uv_x.c b/arch/x86/kernel/apic/x2apic_uv_x.c
index 601159374e87..055e3947bf28 100644
--- a/arch/x86/kernel/apic/x2apic_uv_x.c
+++ b/arch/x86/kernel/apic/x2apic_uv_x.c
@@ -352,14 +352,14 @@ static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
 
 	for (i = 0; i < ARRAY_SIZE(redir_addrs); i++) {
 		alias.v = uv_read_local_mmr(redir_addrs[i].alias);
-		if (alias.s.base == 0) {
+		if (alias.s.enable && alias.s.base == 0) {
 			*size = (1UL << alias.s.m_alias);
 			redirect.v = uv_read_local_mmr(redir_addrs[i].redirect);
 			*base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
 			return;
 		}
 	}
-	BUG();
+	*base = *size = 0;
 }
 
 enum map_type {map_wb, map_uc};
@@ -609,12 +609,12 @@ void __init uv_system_init(void)
 		uv_cpu_hub_info(cpu)->lowmem_remap_base = lowmem_redir_base;
 		uv_cpu_hub_info(cpu)->lowmem_remap_top = lowmem_redir_size;
 		uv_cpu_hub_info(cpu)->m_val = m_val;
-		uv_cpu_hub_info(cpu)->n_val = m_val;
+		uv_cpu_hub_info(cpu)->n_val = n_val;
 		uv_cpu_hub_info(cpu)->numa_blade_id = blade;
 		uv_cpu_hub_info(cpu)->blade_processor_id = lcpu;
 		uv_cpu_hub_info(cpu)->pnode = pnode;
 		uv_cpu_hub_info(cpu)->pnode_mask = pnode_mask;
-		uv_cpu_hub_info(cpu)->gpa_mask = (1 << (m_val + n_val)) - 1;
+		uv_cpu_hub_info(cpu)->gpa_mask = (1UL << (m_val + n_val)) - 1;
 		uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper;
 		uv_cpu_hub_info(cpu)->gnode_extra = gnode_extra;
 		uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base;
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 5ce60a88027b..e338b5cfe0b0 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -1043,7 +1043,7 @@ DEFINE_PER_CPU(struct orig_ist, orig_ist);
 #else	/* CONFIG_X86_64 */
 
 #ifdef CONFIG_CC_STACKPROTECTOR
-DEFINE_PER_CPU(unsigned long, stack_canary);
+DEFINE_PER_CPU(struct stack_canary, stack_canary) ____cacheline_aligned;
 #endif
 
 /* Make sure %fs and %gs are initialized properly in idle threads */
diff --git a/arch/x86/kernel/cpu/cpufreq/powernow-k8.c b/arch/x86/kernel/cpu/cpufreq/powernow-k8.c
index 2a50ef891000..8cbfb42cbef2 100644
--- a/arch/x86/kernel/cpu/cpufreq/powernow-k8.c
+++ b/arch/x86/kernel/cpu/cpufreq/powernow-k8.c
@@ -605,9 +605,10 @@ static int check_pst_table(struct powernow_k8_data *data, struct pst_s *pst,
 	return 0;
 }
 
-static void invalidate_entry(struct powernow_k8_data *data, unsigned int entry)
+static void invalidate_entry(struct cpufreq_frequency_table *powernow_table,
+		unsigned int entry)
 {
-	data->powernow_table[entry].frequency = CPUFREQ_ENTRY_INVALID;
+	powernow_table[entry].frequency = CPUFREQ_ENTRY_INVALID;
 }
 
 static void print_basics(struct powernow_k8_data *data)
@@ -914,13 +915,13 @@ static int fill_powernow_table_pstate(struct powernow_k8_data *data,
 					"bad value %d.\n", i, index);
 			printk(KERN_ERR PFX "Please report to BIOS "
 					"manufacturer\n");
-			invalidate_entry(data, i);
+			invalidate_entry(powernow_table, i);
 			continue;
 		}
 		rdmsr(MSR_PSTATE_DEF_BASE + index, lo, hi);
 		if (!(hi & HW_PSTATE_VALID_MASK)) {
 			dprintk("invalid pstate %d, ignoring\n", index);
-			invalidate_entry(data, i);
+			invalidate_entry(powernow_table, i);
 			continue;
 		}
 
@@ -970,7 +971,7 @@ static int fill_powernow_table_fidvid(struct powernow_k8_data *data,
 		/* verify frequency is OK */
 		if ((freq > (MAX_FREQ * 1000)) || (freq < (MIN_FREQ * 1000))) {
 			dprintk("invalid freq %u kHz, ignoring\n", freq);
-			invalidate_entry(data, i);
+			invalidate_entry(powernow_table, i);
 			continue;
 		}
 
@@ -978,7 +979,7 @@ static int fill_powernow_table_fidvid(struct powernow_k8_data *data,
 		 * BIOSs are using "off" to indicate invalid */
 		if (vid == VID_OFF) {
 			dprintk("invalid vid %u, ignoring\n", vid);
-			invalidate_entry(data, i);
+			invalidate_entry(powernow_table, i);
 			continue;
 		}
 
@@ -997,7 +998,7 @@ static int fill_powernow_table_fidvid(struct powernow_k8_data *data,
 
 				dprintk("double low frequency table entry, "
 						"ignoring it.\n");
-				invalidate_entry(data, i);
+				invalidate_entry(powernow_table, i);
 				continue;
 			} else
 				cntlofreq = i;
@@ -1009,7 +1010,7 @@ static int fill_powernow_table_fidvid(struct powernow_k8_data *data,
 				(unsigned int)
 				(data->acpi_data.states[i].core_frequency
 				 * 1000));
-			invalidate_entry(data, i);
+			invalidate_entry(powernow_table, i);
 			continue;
 		}
 	}
@@ -1371,6 +1372,7 @@ static int __devexit powernowk8_cpu_exit(struct cpufreq_policy *pol)
 
 	kfree(data->powernow_table);
 	kfree(data);
+	per_cpu(powernow_data, pol->cpu) = NULL;
 
 	return 0;
 }
@@ -1390,7 +1392,7 @@ static unsigned int powernowk8_get(unsigned int cpu)
 	int err;
 
 	if (!data)
-		return -EINVAL;
+		return 0;
 
 	smp_call_function_single(cpu, query_values_on_cpu, &err, true);
 	if (err)
diff --git a/arch/x86/kernel/cpu/cpufreq/speedstep-ich.c b/arch/x86/kernel/cpu/cpufreq/speedstep-ich.c
index 6911e91fb4f6..3ae5a7a3a500 100644
--- a/arch/x86/kernel/cpu/cpufreq/speedstep-ich.c
+++ b/arch/x86/kernel/cpu/cpufreq/speedstep-ich.c
@@ -232,28 +232,23 @@ static unsigned int speedstep_detect_chipset(void)
 	return 0;
 }
 
-struct get_freq_data {
-	unsigned int speed;
-	unsigned int processor;
-};
-
-static void get_freq_data(void *_data)
+static void get_freq_data(void *_speed)
 {
-	struct get_freq_data *data = _data;
+	unsigned int *speed = _speed;
 
-	data->speed = speedstep_get_frequency(data->processor);
+	*speed = speedstep_get_frequency(speedstep_processor);
 }
 
 static unsigned int speedstep_get(unsigned int cpu)
 {
-	struct get_freq_data data = { .processor = cpu };
+	unsigned int speed;
 
 	/* You're supposed to ensure CPU is online. */
-	if (smp_call_function_single(cpu, get_freq_data, &data, 1) != 0)
+	if (smp_call_function_single(cpu, get_freq_data, &speed, 1) != 0)
 		BUG();
 
-	dprintk("detected %u kHz as current frequency\n", data.speed);
-	return data.speed;
+	dprintk("detected %u kHz as current frequency\n", speed);
+	return speed;
 }
 
 /**
diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
index 789efe217e1a..781130fd31fc 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -93,7 +93,7 @@ static const struct _cache_table __cpuinitconst cache_table[] =
 	{ 0xd1, LVL_3,    1024 },	/* 4-way set assoc, 64 byte line size */
 	{ 0xd2, LVL_3,    2048 },	/* 4-way set assoc, 64 byte line size */
 	{ 0xd6, LVL_3,    1024 },	/* 8-way set assoc, 64 byte line size */
-	{ 0xd7, LVL_3,    2038 },	/* 8-way set assoc, 64 byte line size */
+	{ 0xd7, LVL_3,    2048 },	/* 8-way set assoc, 64 byte line size */
 	{ 0xd8, LVL_3,    4096 },	/* 12-way set assoc, 64 byte line size */
 	{ 0xdc, LVL_3,    2048 },	/* 12-way set assoc, 64 byte line size */
 	{ 0xdd, LVL_3,    4096 },	/* 12-way set assoc, 64 byte line size */
@@ -101,6 +101,9 @@ static const struct _cache_table __cpuinitconst cache_table[] =
 	{ 0xe2, LVL_3,    2048 },	/* 16-way set assoc, 64 byte line size */
 	{ 0xe3, LVL_3,    4096 },	/* 16-way set assoc, 64 byte line size */
 	{ 0xe4, LVL_3,    8192 },	/* 16-way set assoc, 64 byte line size */
+	{ 0xea, LVL_3,    12288 },	/* 24-way set assoc, 64 byte line size */
+	{ 0xeb, LVL_3,    18432 },	/* 24-way set assoc, 64 byte line size */
+	{ 0xec, LVL_3,    24576 },	/* 24-way set assoc, 64 byte line size */
 	{ 0x00, 0, 0}
 };
 
diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index 01213048f62f..4192c500317e 100644
--- a/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@ -1327,13 +1327,14 @@ static void mce_init_timer(void)
 	struct timer_list *t = &__get_cpu_var(mce_timer);
 	int *n = &__get_cpu_var(next_interval);
 
+	setup_timer(t, mcheck_timer, smp_processor_id());
+
 	if (mce_ignore_ce)
 		return;
 
 	*n = check_interval * HZ;
 	if (!*n)
 		return;
-	setup_timer(t, mcheck_timer, smp_processor_id());
 	t->expires = round_jiffies(jiffies + *n);
 	add_timer_on(t, smp_processor_id());
 }
diff --git a/arch/x86/kernel/cpu/mcheck/therm_throt.c b/arch/x86/kernel/cpu/mcheck/therm_throt.c
index 5957a93e5173..a14a45194076 100644
--- a/arch/x86/kernel/cpu/mcheck/therm_throt.c
+++ b/arch/x86/kernel/cpu/mcheck/therm_throt.c
@@ -34,20 +34,33 @@
 /* How long to wait between reporting thermal events */
 #define CHECK_INTERVAL		(300 * HZ)
 
-static DEFINE_PER_CPU(__u64, next_check) = INITIAL_JIFFIES;
-static DEFINE_PER_CPU(unsigned long, thermal_throttle_count);
-static DEFINE_PER_CPU(bool, thermal_throttle_active);
+/*
+ * Current thermal throttling state:
+ */
+struct thermal_state {
+	bool			is_throttled;
+
+	u64			next_check;
+	unsigned long		throttle_count;
+	unsigned long		last_throttle_count;
+};
+
+static DEFINE_PER_CPU(struct thermal_state, thermal_state);
 
-static atomic_t therm_throt_en		= ATOMIC_INIT(0);
+static atomic_t therm_throt_en	= ATOMIC_INIT(0);
+
+static u32 lvtthmr_init __read_mostly;
 
 #ifdef CONFIG_SYSFS
 #define define_therm_throt_sysdev_one_ro(_name)				\
 	static SYSDEV_ATTR(_name, 0444, therm_throt_sysdev_show_##_name, NULL)
 
 #define define_therm_throt_sysdev_show_func(name)			\
-static ssize_t therm_throt_sysdev_show_##name(struct sys_device *dev,	\
-					struct sysdev_attribute *attr,	\
-					      char *buf)		\
+									\
+static ssize_t therm_throt_sysdev_show_##name(				\
+			struct sys_device *dev,				\
+			struct sysdev_attribute *attr,			\
+			char *buf)					\
 {									\
 	unsigned int cpu = dev->id;					\
 	ssize_t ret;							\
@@ -55,7 +68,7 @@ static ssize_t therm_throt_sysdev_show_##name(struct sys_device *dev,	\
 	preempt_disable();	/* CPU hotplug */			\
 	if (cpu_online(cpu))						\
 		ret = sprintf(buf, "%lu\n",				\
-			      per_cpu(thermal_throttle_##name, cpu));	\
+			      per_cpu(thermal_state, cpu).name);	\
 	else								\
 		ret = 0;						\
 	preempt_enable();						\
@@ -63,11 +76,11 @@ static ssize_t therm_throt_sysdev_show_##name(struct sys_device *dev,	\
 	return ret;							\
 }
 
-define_therm_throt_sysdev_show_func(count);
-define_therm_throt_sysdev_one_ro(count);
+define_therm_throt_sysdev_show_func(throttle_count);
+define_therm_throt_sysdev_one_ro(throttle_count);
 
 static struct attribute *thermal_throttle_attrs[] = {
-	&attr_count.attr,
+	&attr_throttle_count.attr,
 	NULL
 };
 
@@ -93,33 +106,39 @@ static struct attribute_group thermal_throttle_attr_group = {
  *          1 : Event should be logged further, and a message has been
  *              printed to the syslog.
  */
-static int therm_throt_process(int curr)
+static int therm_throt_process(bool is_throttled)
 {
-	unsigned int cpu = smp_processor_id();
-	__u64 tmp_jiffs = get_jiffies_64();
-	bool was_throttled = __get_cpu_var(thermal_throttle_active);
-	bool is_throttled = __get_cpu_var(thermal_throttle_active) = curr;
+	struct thermal_state *state;
+	unsigned int this_cpu;
+	bool was_throttled;
+	u64 now;
+
+	this_cpu = smp_processor_id();
+	now = get_jiffies_64();
+	state = &per_cpu(thermal_state, this_cpu);
+
+	was_throttled = state->is_throttled;
+	state->is_throttled = is_throttled;
 
 	if (is_throttled)
-		__get_cpu_var(thermal_throttle_count)++;
+		state->throttle_count++;
 
-	if (!(was_throttled ^ is_throttled) &&
-	    time_before64(tmp_jiffs, __get_cpu_var(next_check)))
+	if (time_before64(now, state->next_check) &&
+			state->throttle_count != state->last_throttle_count)
 		return 0;
 
-	__get_cpu_var(next_check) = tmp_jiffs + CHECK_INTERVAL;
+	state->next_check = now + CHECK_INTERVAL;
+	state->last_throttle_count = state->throttle_count;
 
 	/* if we just entered the thermal event */
 	if (is_throttled) {
-		printk(KERN_CRIT "CPU%d: Temperature above threshold, "
-		       "cpu clock throttled (total events = %lu)\n",
-		       cpu, __get_cpu_var(thermal_throttle_count));
+		printk(KERN_CRIT "CPU%d: Temperature above threshold, cpu clock throttled (total events = %lu)\n", this_cpu, state->throttle_count);
 
 		add_taint(TAINT_MACHINE_CHECK);
 		return 1;
 	}
 	if (was_throttled) {
-		printk(KERN_INFO "CPU%d: Temperature/speed normal\n", cpu);
+		printk(KERN_INFO "CPU%d: Temperature/speed normal\n", this_cpu);
 		return 1;
 	}
 
@@ -213,7 +232,7 @@ static void intel_thermal_interrupt(void)
 	__u64 msr_val;
 
 	rdmsrl(MSR_IA32_THERM_STATUS, msr_val);
-	if (therm_throt_process(msr_val & THERM_STATUS_PROCHOT))
+	if (therm_throt_process((msr_val & THERM_STATUS_PROCHOT) != 0))
 		mce_log_therm_throt_event(msr_val);
 }
 
@@ -237,6 +256,18 @@ asmlinkage void smp_thermal_interrupt(struct pt_regs *regs)
 	ack_APIC_irq();
 }
 
+void __init mcheck_intel_therm_init(void)
+{
+	/*
+	 * This function is only called on boot CPU. Save the init thermal
+	 * LVT value on BSP and use that value to restore APs' thermal LVT
+	 * entry BIOS programmed later
+	 */
+	if (cpu_has(&boot_cpu_data, X86_FEATURE_ACPI) &&
+		cpu_has(&boot_cpu_data, X86_FEATURE_ACC))
+		lvtthmr_init = apic_read(APIC_LVTTHMR);
+}
+
 void intel_init_thermal(struct cpuinfo_x86 *c)
 {
 	unsigned int cpu = smp_processor_id();
@@ -253,7 +284,20 @@ void intel_init_thermal(struct cpuinfo_x86 *c)
 	 * since it might be delivered via SMI already:
 	 */
 	rdmsr(MSR_IA32_MISC_ENABLE, l, h);
-	h = apic_read(APIC_LVTTHMR);
+
+	/*
+	 * The initial value of thermal LVT entries on all APs always reads
+	 * 0x10000 because APs are woken up by BSP issuing INIT-SIPI-SIPI
+	 * sequence to them and LVT registers are reset to 0s except for
+	 * the mask bits which are set to 1s when APs receive INIT IPI.
+	 * Always restore the value that BIOS has programmed on AP based on
+	 * BSP's info we saved since BIOS is always setting the same value
+	 * for all threads/cores
+	 */
+	apic_write(APIC_LVTTHMR, lvtthmr_init);
+
+	h = lvtthmr_init;
+
 	if ((l & MSR_IA32_MISC_ENABLE_TM1) && (h & APIC_DM_SMI)) {
 		printk(KERN_DEBUG
 		       "CPU%d: Thermal monitoring handled by SMI\n", cpu);
diff --git a/arch/x86/kernel/cpu/perfctr-watchdog.c b/arch/x86/kernel/cpu/perfctr-watchdog.c
index e60ed740d2b3..d23746ec8796 100644
--- a/arch/x86/kernel/cpu/perfctr-watchdog.c
+++ b/arch/x86/kernel/cpu/perfctr-watchdog.c
@@ -711,7 +711,7 @@ static void probe_nmi_watchdog(void)
 	switch (boot_cpu_data.x86_vendor) {
 	case X86_VENDOR_AMD:
 		if (boot_cpu_data.x86 != 6 && boot_cpu_data.x86 != 15 &&
-		    boot_cpu_data.x86 != 16)
+		    boot_cpu_data.x86 != 16 && boot_cpu_data.x86 != 17)
 			return;
 		wd_ops = &k7_wd_ops;
 		break;
diff --git a/arch/x86/kernel/e820.c b/arch/x86/kernel/e820.c
index 5cb5725b2bae..0bc204d1166b 100644
--- a/arch/x86/kernel/e820.c
+++ b/arch/x86/kernel/e820.c
@@ -1378,8 +1378,8 @@ static unsigned long ram_alignment(resource_size_t pos)
 	if (mb < 16)
 		return 1024*1024;
 
-	/* To 32MB for anything above that */
-	return 32*1024*1024;
+	/* To 64MB for anything above that */
+	return 64*1024*1024;
 }
 
 #define MAX_RESOURCE_SIZE ((resource_size_t)-1)
diff --git a/arch/x86/kernel/head_32.S b/arch/x86/kernel/head_32.S
index cc827ac9e8d3..7ffec6b3b331 100644
--- a/arch/x86/kernel/head_32.S
+++ b/arch/x86/kernel/head_32.S
@@ -439,7 +439,6 @@ is386:	movl $2,%ecx		# set MP
 	jne 1f
 	movl $per_cpu__gdt_page,%eax
 	movl $per_cpu__stack_canary,%ecx
-	subl $20, %ecx
 	movw %cx, 8 * GDT_ENTRY_STACK_CANARY + 2(%eax)
 	shrl $16, %ecx
 	movb %cl, 8 * GDT_ENTRY_STACK_CANARY + 4(%eax)
diff --git a/arch/x86/kernel/i8253.c b/arch/x86/kernel/i8253.c
index 5cf36c053ac4..da890f03d078 100644
--- a/arch/x86/kernel/i8253.c
+++ b/arch/x86/kernel/i8253.c
@@ -21,8 +21,10 @@ EXPORT_SYMBOL(i8253_lock);
 
 #ifdef CONFIG_X86_32
 static void pit_disable_clocksource(void);
+static void pit_enable_clocksource(void);
 #else
 static inline void pit_disable_clocksource(void) { }
+static inline void pit_enable_clocksource(void) { }
 #endif
 
 /*
@@ -67,7 +69,7 @@ static void init_pit_timer(enum clock_event_mode mode,
 		break;
 
 	case CLOCK_EVT_MODE_RESUME:
-		/* Nothing to do here */
+		pit_enable_clocksource();
 		break;
 	}
 	spin_unlock(&i8253_lock);
@@ -200,19 +202,27 @@ static struct clocksource pit_cs = {
 	.shift		= 20,
 };
 
+int pit_cs_registered;
 static void pit_disable_clocksource(void)
 {
-	/*
-	 * Use mult to check whether it is registered or not
-	 */
-	if (pit_cs.mult) {
+	if (pit_cs_registered) {
 		clocksource_unregister(&pit_cs);
-		pit_cs.mult = 0;
+		pit_cs_registered = 0;
+	}
+}
+
+static void pit_enable_clocksource(void)
+{
+	if (!pit_cs_registered && !clocksource_register(&pit_cs)) {
+		pit_cs_registered = 1;
 	}
 }
 
+
+
 static int __init init_pit_clocksource(void)
 {
+	int ret;
 	 /*
 	  * Several reasons not to register PIT as a clocksource:
 	  *
@@ -226,7 +236,10 @@ static int __init init_pit_clocksource(void)
 
 	pit_cs.mult = clocksource_hz2mult(CLOCK_TICK_RATE, pit_cs.shift);
 
-	return clocksource_register(&pit_cs);
+	ret = clocksource_register(&pit_cs);
+	if (!ret)
+		pit_cs_registered = 1;
+	return ret;
 }
 arch_initcall(init_pit_clocksource);
 
diff --git a/arch/x86/kernel/kvm.c b/arch/x86/kernel/kvm.c
index c664d515f613..63b0ec8d3d4a 100644
--- a/arch/x86/kernel/kvm.c
+++ b/arch/x86/kernel/kvm.c
@@ -34,7 +34,6 @@
 struct kvm_para_state {
 	u8 mmu_queue[MMU_QUEUE_SIZE];
 	int mmu_queue_len;
-	enum paravirt_lazy_mode mode;
 };
 
 static DEFINE_PER_CPU(struct kvm_para_state, para_state);
@@ -77,7 +76,7 @@ static void kvm_deferred_mmu_op(void *buffer, int len)
 {
 	struct kvm_para_state *state = kvm_para_state();
 
-	if (state->mode != PARAVIRT_LAZY_MMU) {
+	if (paravirt_get_lazy_mode() != PARAVIRT_LAZY_MMU) {
 		kvm_mmu_op(buffer, len);
 		return;
 	}
@@ -185,10 +184,7 @@ static void kvm_release_pt(unsigned long pfn)
 
 static void kvm_enter_lazy_mmu(void)
 {
-	struct kvm_para_state *state = kvm_para_state();
-
 	paravirt_enter_lazy_mmu();
-	state->mode = paravirt_get_lazy_mode();
 }
 
 static void kvm_leave_lazy_mmu(void)
@@ -197,7 +193,6 @@ static void kvm_leave_lazy_mmu(void)
 
 	mmu_queue_flush(state);
 	paravirt_leave_lazy_mmu();
-	state->mode = paravirt_get_lazy_mode();
 }
 
 static void __init paravirt_ops_setup(void)
diff --git a/arch/x86/kernel/kvmclock.c b/arch/x86/kernel/kvmclock.c
index 223af43f1526..e5efcdcca31b 100644
--- a/arch/x86/kernel/kvmclock.c
+++ b/arch/x86/kernel/kvmclock.c
@@ -50,8 +50,8 @@ static unsigned long kvm_get_wallclock(void)
 	struct timespec ts;
 	int low, high;
 
-	low = (int)__pa(&wall_clock);
-	high = ((u64)__pa(&wall_clock) >> 32);
+	low = (int)__pa_symbol(&wall_clock);
+	high = ((u64)__pa_symbol(&wall_clock) >> 32);
 	native_write_msr(MSR_KVM_WALL_CLOCK, low, high);
 
 	vcpu_time = &get_cpu_var(hv_clock);
diff --git a/arch/x86/kernel/microcode_core.c b/arch/x86/kernel/microcode_core.c
index 9371448290ac..0511035f3b84 100644
--- a/arch/x86/kernel/microcode_core.c
+++ b/arch/x86/kernel/microcode_core.c
@@ -210,8 +210,8 @@ static ssize_t microcode_write(struct file *file, const char __user *buf,
 {
 	ssize_t ret = -EINVAL;
 
-	if ((len >> PAGE_SHIFT) > num_physpages) {
-		pr_err("microcode: too much data (max %ld pages)\n", num_physpages);
+	if ((len >> PAGE_SHIFT) > totalram_pages) {
+		pr_err("microcode: too much data (max %ld pages)\n", totalram_pages);
 		return ret;
 	}
 
diff --git a/arch/x86/kernel/pci-calgary_64.c b/arch/x86/kernel/pci-calgary_64.c
index 971a3bec47a8..e6ec8a2df1c3 100644
--- a/arch/x86/kernel/pci-calgary_64.c
+++ b/arch/x86/kernel/pci-calgary_64.c
@@ -318,13 +318,15 @@ static inline struct iommu_table *find_iommu_table(struct device *dev)
 
 	pdev = to_pci_dev(dev);
 
+	/* search up the device tree for an iommu */
 	pbus = pdev->bus;
-
-	/* is the device behind a bridge? Look for the root bus */
-	while (pbus->parent)
+	do {
+		tbl = pci_iommu(pbus);
+		if (tbl && tbl->it_busno == pbus->number)
+			break;
+		tbl = NULL;
 		pbus = pbus->parent;
-
-	tbl = pci_iommu(pbus);
+	} while (pbus);
 
 	BUG_ON(tbl && (tbl->it_busno != pbus->number));
 
diff --git a/arch/x86/kernel/pci-dma.c b/arch/x86/kernel/pci-dma.c
index 1a041bcf506b..953667c7487f 100644
--- a/arch/x86/kernel/pci-dma.c
+++ b/arch/x86/kernel/pci-dma.c
@@ -203,7 +203,7 @@ static __init int iommu_setup(char *p)
 		if (!strncmp(p, "allowdac", 8))
 			forbid_dac = 0;
 		if (!strncmp(p, "nodac", 5))
-			forbid_dac = -1;
+			forbid_dac = 1;
 		if (!strncmp(p, "usedac", 6)) {
 			forbid_dac = -1;
 			return 1;
diff --git a/arch/x86/kernel/pci-gart_64.c b/arch/x86/kernel/pci-gart_64.c
index d2e56b8f48e7..6f711b3a84d7 100644
--- a/arch/x86/kernel/pci-gart_64.c
+++ b/arch/x86/kernel/pci-gart_64.c
@@ -856,7 +856,7 @@ void __init gart_parse_options(char *p)
 #endif
 	if (isdigit(*p) && get_option(&p, &arg))
 		iommu_size = arg;
-	if (!strncmp(p, "fullflush", 8))
+	if (!strncmp(p, "fullflush", 9))
 		iommu_fullflush = 1;
 	if (!strncmp(p, "nofullflush", 11))
 		iommu_fullflush = 0;
diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c
index 071166a4ba83..a35fcbd9fe38 100644
--- a/arch/x86/kernel/process.c
+++ b/arch/x86/kernel/process.c
@@ -94,18 +94,6 @@ void flush_thread(void)
 {
 	struct task_struct *tsk = current;
 
-#ifdef CONFIG_X86_64
-	if (test_tsk_thread_flag(tsk, TIF_ABI_PENDING)) {
-		clear_tsk_thread_flag(tsk, TIF_ABI_PENDING);
-		if (test_tsk_thread_flag(tsk, TIF_IA32)) {
-			clear_tsk_thread_flag(tsk, TIF_IA32);
-		} else {
-			set_tsk_thread_flag(tsk, TIF_IA32);
-			current_thread_info()->status |= TS_COMPAT;
-		}
-	}
-#endif
-
 	clear_tsk_thread_flag(tsk, TIF_DEBUG);
 
 	tsk->thread.debugreg0 = 0;
diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c
index ebefb5407b9d..80c2372ec3cb 100644
--- a/arch/x86/kernel/process_64.c
+++ b/arch/x86/kernel/process_64.c
@@ -534,6 +534,17 @@ sys_clone(unsigned long clone_flags, unsigned long newsp,
 	return do_fork(clone_flags, newsp, regs, 0, parent_tid, child_tid);
 }
 
+void set_personality_ia32(void)
+{
+	/* inherit personality from parent */
+
+	/* Make sure to be in 32bit mode */
+	set_thread_flag(TIF_IA32);
+
+	/* Prepare the first "return" to user space */
+	current_thread_info()->status |= TS_COMPAT;
+}
+
 unsigned long get_wchan(struct task_struct *p)
 {
 	unsigned long stack;
diff --git a/arch/x86/kernel/ptrace.c b/arch/x86/kernel/ptrace.c
index 09ecbde91c13..96e2a86ac86a 100644
--- a/arch/x86/kernel/ptrace.c
+++ b/arch/x86/kernel/ptrace.c
@@ -417,14 +417,14 @@ static int genregs_get(struct task_struct *target,
 {
 	if (kbuf) {
 		unsigned long *k = kbuf;
-		while (count > 0) {
+		while (count >= sizeof(*k)) {
 			*k++ = getreg(target, pos);
 			count -= sizeof(*k);
 			pos += sizeof(*k);
 		}
 	} else {
 		unsigned long __user *u = ubuf;
-		while (count > 0) {
+		while (count >= sizeof(*u)) {
 			if (__put_user(getreg(target, pos), u++))
 				return -EFAULT;
 			count -= sizeof(*u);
@@ -443,14 +443,14 @@ static int genregs_set(struct task_struct *target,
 	int ret = 0;
 	if (kbuf) {
 		const unsigned long *k = kbuf;
-		while (count > 0 && !ret) {
+		while (count >= sizeof(*k) && !ret) {
 			ret = putreg(target, pos, *k++);
 			count -= sizeof(*k);
 			pos += sizeof(*k);
 		}
 	} else {
 		const unsigned long  __user *u = ubuf;
-		while (count > 0 && !ret) {
+		while (count >= sizeof(*u) && !ret) {
 			unsigned long word;
 			ret = __get_user(word, u++);
 			if (ret)
@@ -1223,14 +1223,14 @@ static int genregs32_get(struct task_struct *target,
 {
 	if (kbuf) {
 		compat_ulong_t *k = kbuf;
-		while (count > 0) {
+		while (count >= sizeof(*k)) {
 			getreg32(target, pos, k++);
 			count -= sizeof(*k);
 			pos += sizeof(*k);
 		}
 	} else {
 		compat_ulong_t __user *u = ubuf;
-		while (count > 0) {
+		while (count >= sizeof(*u)) {
 			compat_ulong_t word;
 			getreg32(target, pos, &word);
 			if (__put_user(word, u++))
@@ -1251,14 +1251,14 @@ static int genregs32_set(struct task_struct *target,
 	int ret = 0;
 	if (kbuf) {
 		const compat_ulong_t *k = kbuf;
-		while (count > 0 && !ret) {
+		while (count >= sizeof(*k) && !ret) {
 			ret = putreg32(target, pos, *k++);
 			count -= sizeof(*k);
 			pos += sizeof(*k);
 		}
 	} else {
 		const compat_ulong_t __user *u = ubuf;
-		while (count > 0 && !ret) {
+		while (count >= sizeof(*u) && !ret) {
 			compat_ulong_t word;
 			ret = __get_user(word, u++);
 			if (ret)
diff --git a/arch/x86/kernel/reboot.c b/arch/x86/kernel/reboot.c
index a06e8d101844..df1e1cb8fe4d 100644
--- a/arch/x86/kernel/reboot.c
+++ b/arch/x86/kernel/reboot.c
@@ -257,6 +257,14 @@ static struct dmi_system_id __initdata reboot_dmi_table[] = {
 			DMI_MATCH(DMI_PRODUCT_NAME, "SBC-FITPC2"),
 		},
 	},
+	{       /* Handle problems with rebooting on ASUS P4S800 */
+		.callback = set_bios_reboot,
+		.ident = "ASUS P4S800",
+		.matches = {
+			DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
+			DMI_MATCH(DMI_BOARD_NAME, "P4S800"),
+		},
+	},
 	{ }
 };
 
diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c
index 63f32d220ef2..860ed56aa4c4 100644
--- a/arch/x86/kernel/setup.c
+++ b/arch/x86/kernel/setup.c
@@ -107,6 +107,7 @@
 #ifdef CONFIG_X86_64
 #include <asm/numa_64.h>
 #endif
+#include <asm/mce.h>
 
 #ifndef ARCH_SETUP
 #define ARCH_SETUP
@@ -1030,6 +1031,8 @@ void __init setup_arch(char **cmdline_p)
 	conswitchp = &dummy_con;
 #endif
 #endif
+
+	mcheck_intel_therm_init();
 }
 
 #ifdef CONFIG_X86_32
diff --git a/arch/x86/kernel/tlb_uv.c b/arch/x86/kernel/tlb_uv.c
index 77b9689f8edb..9848980dbbc0 100644
--- a/arch/x86/kernel/tlb_uv.c
+++ b/arch/x86/kernel/tlb_uv.c
@@ -843,8 +843,8 @@ static int __init uv_bau_init(void)
 				       GFP_KERNEL, cpu_to_node(cur_cpu));
 
 	uv_bau_retry_limit = 1;
-	uv_nshift = uv_hub_info->n_val;
-	uv_mmask = (1UL << uv_hub_info->n_val) - 1;
+	uv_nshift = uv_hub_info->m_val;
+	uv_mmask = (1UL << uv_hub_info->m_val) - 1;
 	nblades = uv_num_possible_blades();
 
 	uv_bau_table_bases = (struct bau_control **)
diff --git a/arch/x86/kvm/i8254.c b/arch/x86/kvm/i8254.c
index 21f68e00524f..5c8bffff6bd7 100644
--- a/arch/x86/kvm/i8254.c
+++ b/arch/x86/kvm/i8254.c
@@ -116,7 +116,7 @@ static s64 __kpit_elapsed(struct kvm *kvm)
 	 * itself with the initial count and continues counting
 	 * from there.
 	 */
-	remaining = hrtimer_expires_remaining(&ps->pit_timer.timer);
+	remaining = hrtimer_get_remaining(&ps->pit_timer.timer);
 	elapsed = ps->pit_timer.period - ktime_to_ns(remaining);
 	elapsed = mod_64(elapsed, ps->pit_timer.period);
 
diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
index ae99d83f81a3..9a65123b798e 100644
--- a/arch/x86/kvm/lapic.c
+++ b/arch/x86/kvm/lapic.c
@@ -464,7 +464,7 @@ static u32 apic_get_tmcct(struct kvm_lapic *apic)
 	if (apic_get_reg(apic, APIC_TMICT) == 0)
 		return 0;
 
-	remaining = hrtimer_expires_remaining(&apic->lapic_timer.timer);
+	remaining = hrtimer_get_remaining(&apic->lapic_timer.timer);
 	if (ktime_to_ns(remaining) < 0)
 		remaining = ktime_set(0, 0);
 
@@ -567,12 +567,21 @@ static void start_apic_timer(struct kvm_lapic *apic)
 {
 	ktime_t now = apic->lapic_timer.timer.base->get_time();
 
-	apic->lapic_timer.period = apic_get_reg(apic, APIC_TMICT) *
+	apic->lapic_timer.period = (u64)apic_get_reg(apic, APIC_TMICT) *
 		    APIC_BUS_CYCLE_NS * apic->divide_count;
 	atomic_set(&apic->lapic_timer.pending, 0);
 
 	if (!apic->lapic_timer.period)
 		return;
+	/*
+	 * Do not allow the guest to program periodic timers with small
+	 * interval, since the hrtimers are not throttled by the host
+	 * scheduler.
+	 */
+	if (apic_lvtt_period(apic)) {
+		if (apic->lapic_timer.period < NSEC_PER_MSEC/2)
+			apic->lapic_timer.period = NSEC_PER_MSEC/2;
+	}
 
 	hrtimer_start(&apic->lapic_timer.timer,
 		      ktime_add_ns(now, apic->lapic_timer.period),
diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c
index 0ef5bb2b4043..47122930a8bb 100644
--- a/arch/x86/kvm/mmu.c
+++ b/arch/x86/kvm/mmu.c
@@ -2633,7 +2633,8 @@ EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt);
 
 void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu)
 {
-	while (vcpu->kvm->arch.n_free_mmu_pages < KVM_REFILL_PAGES) {
+	while (vcpu->kvm->arch.n_free_mmu_pages < KVM_REFILL_PAGES &&
+	       !list_empty(&vcpu->kvm->arch.active_mmu_pages)) {
 		struct kvm_mmu_page *sp;
 
 		sp = container_of(vcpu->kvm->arch.active_mmu_pages.prev,
@@ -2712,12 +2713,6 @@ static int alloc_mmu_pages(struct kvm_vcpu *vcpu)
 
 	ASSERT(vcpu);
 
-	if (vcpu->kvm->arch.n_requested_mmu_pages)
-		vcpu->kvm->arch.n_free_mmu_pages =
-					vcpu->kvm->arch.n_requested_mmu_pages;
-	else
-		vcpu->kvm->arch.n_free_mmu_pages =
-					vcpu->kvm->arch.n_alloc_mmu_pages;
 	/*
 	 * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64.
 	 * Therefore we need to allocate shadow page tables in the first
diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
index b1f658ad2f06..4ac68999c7b0 100644
--- a/arch/x86/kvm/svm.c
+++ b/arch/x86/kvm/svm.c
@@ -709,6 +709,8 @@ static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 		rdtscll(tsc_this);
 		delta = vcpu->arch.host_tsc - tsc_this;
 		svm->vmcb->control.tsc_offset += delta;
+		if (is_nested(svm))
+			svm->hsave->control.tsc_offset += delta;
 		vcpu->cpu = cpu;
 		kvm_migrate_timers(vcpu);
 		svm->asid_generation = 0;
@@ -1954,10 +1956,14 @@ static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
 
 	switch (ecx) {
 	case MSR_IA32_TIME_STAMP_COUNTER: {
-		u64 tsc;
+		u64 tsc_offset;
 
-		rdtscll(tsc);
-		*data = svm->vmcb->control.tsc_offset + tsc;
+		if (is_nested(svm))
+			tsc_offset = svm->hsave->control.tsc_offset;
+		else
+			tsc_offset = svm->vmcb->control.tsc_offset;
+
+		*data = tsc_offset + native_read_tsc();
 		break;
 	}
 	case MSR_K6_STAR:
@@ -2044,10 +2050,17 @@ static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
 
 	switch (ecx) {
 	case MSR_IA32_TIME_STAMP_COUNTER: {
-		u64 tsc;
+		u64 tsc_offset = data - native_read_tsc();
+		u64 g_tsc_offset = 0;
+
+		if (is_nested(svm)) {
+			g_tsc_offset = svm->vmcb->control.tsc_offset -
+				       svm->hsave->control.tsc_offset;
+			svm->hsave->control.tsc_offset = tsc_offset;
+		}
+
+		svm->vmcb->control.tsc_offset = tsc_offset + g_tsc_offset;
 
-		rdtscll(tsc);
-		svm->vmcb->control.tsc_offset = data - tsc;
 		break;
 	}
 	case MSR_K6_STAR:
diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index 29f912927a58..ff72e4d85696 100644
--- a/arch/x86/kvm/vmx.c
+++ b/arch/x86/kvm/vmx.c
@@ -661,7 +661,7 @@ static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 	if (vcpu->cpu != cpu) {
 		vcpu_clear(vmx);
 		kvm_migrate_timers(vcpu);
-		vpid_sync_vcpu_all(vmx);
+		set_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests);
 		local_irq_disable();
 		list_add(&vmx->local_vcpus_link,
 			 &per_cpu(vcpus_on_cpu, cpu));
@@ -1217,12 +1217,9 @@ static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
 	if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
 		/* CR3 accesses and invlpg don't need to cause VM Exits when EPT
 		   enabled */
-		min &= ~(CPU_BASED_CR3_LOAD_EXITING |
-			 CPU_BASED_CR3_STORE_EXITING |
-			 CPU_BASED_INVLPG_EXITING);
-		if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
-					&_cpu_based_exec_control) < 0)
-			return -EIO;
+		_cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
+					     CPU_BASED_CR3_STORE_EXITING |
+					     CPU_BASED_INVLPG_EXITING);
 		rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
 		      vmx_capability.ept, vmx_capability.vpid);
 	}
@@ -1572,7 +1569,6 @@ static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
 		vcpu->arch.cr0 = cr0;
 		vmx_set_cr4(vcpu, vcpu->arch.cr4);
 		*hw_cr0 |= X86_CR0_PE | X86_CR0_PG;
-		*hw_cr0 &= ~X86_CR0_WP;
 	} else if (!is_paging(vcpu)) {
 		/* From nonpaging to paging */
 		vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
@@ -1581,9 +1577,10 @@ static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
 			       CPU_BASED_CR3_STORE_EXITING));
 		vcpu->arch.cr0 = cr0;
 		vmx_set_cr4(vcpu, vcpu->arch.cr4);
-		if (!(vcpu->arch.cr0 & X86_CR0_WP))
-			*hw_cr0 &= ~X86_CR0_WP;
 	}
+
+	if (!(cr0 & X86_CR0_WP))
+		*hw_cr0 &= ~X86_CR0_WP;
 }
 
 static void ept_update_paging_mode_cr4(unsigned long *hw_cr4,
@@ -2841,6 +2838,8 @@ static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
 	unsigned long val;
 	int dr, reg;
 
+	if (!kvm_require_cpl(vcpu, 0))
+		return 1;
 	dr = vmcs_readl(GUEST_DR7);
 	if (dr & DR7_GD) {
 		/*
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index 3d4529011828..26e454ccd0a8 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -215,6 +215,19 @@ static void __queue_exception(struct kvm_vcpu *vcpu)
 }
 
 /*
+ * Checks if cpl <= required_cpl; if true, return true.  Otherwise queue
+ * a #GP and return false.
+ */
+bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
+{
+	if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
+		return true;
+	kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
+	return false;
+}
+EXPORT_SYMBOL_GPL(kvm_require_cpl);
+
+/*
  * Load the pae pdptrs.  Return true is they are all valid.
  */
 int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
@@ -936,6 +949,7 @@ int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
 	case MSR_P6_EVNTSEL0:
 	case MSR_P6_EVNTSEL1:
 	case MSR_K7_EVNTSEL0:
+	case MSR_K8_INT_PENDING_MSG:
 		data = 0;
 		break;
 	case MSR_MTRRcap:
@@ -1416,6 +1430,8 @@ static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
 
 	if (cpuid->nent < 1)
 		goto out;
+	if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
+		cpuid->nent = KVM_MAX_CPUID_ENTRIES;
 	r = -ENOMEM;
 	cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
 	if (!cpuid_entries)
@@ -1435,6 +1451,10 @@ static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
 	for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
 		do_cpuid_ent(&cpuid_entries[nent], func, 0,
 			     &nent, cpuid->nent);
+	r = -E2BIG;
+	if (nent >= cpuid->nent)
+		goto out_free;
+
 	r = -EFAULT;
 	if (copy_to_user(entries, cpuid_entries,
 			 nent * sizeof(struct kvm_cpuid_entry2)))
@@ -2898,6 +2918,11 @@ int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
 		a3 &= 0xFFFFFFFF;
 	}
 
+	if (kvm_x86_ops->get_cpl(vcpu) != 0) {
+		ret = -KVM_EPERM;
+		goto out;
+	}
+
 	switch (nr) {
 	case KVM_HC_VAPIC_POLL_IRQ:
 		ret = 0;
@@ -2909,6 +2934,7 @@ int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
 		ret = -KVM_ENOSYS;
 		break;
 	}
+out:
 	kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
 	++vcpu->stat.hypercalls;
 	return r;
@@ -3179,6 +3205,9 @@ static void update_cr8_intercept(struct kvm_vcpu *vcpu)
 	if (!kvm_x86_ops->update_cr8_intercept)
 		return;
 
+	if (!vcpu->arch.apic)
+		return;
+
 	if (!vcpu->arch.apic->vapic_addr)
 		max_irr = kvm_lapic_find_highest_irr(vcpu);
 	else
@@ -3733,7 +3762,7 @@ static int save_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
 	return kvm_write_guest(vcpu->kvm, gpa, seg_desc, 8);
 }
 
-static u32 get_tss_base_addr(struct kvm_vcpu *vcpu,
+static gpa_t get_tss_base_addr(struct kvm_vcpu *vcpu,
 			     struct desc_struct *seg_desc)
 {
 	u32 base_addr;
@@ -4099,13 +4128,7 @@ int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
 
 	vcpu->arch.cr2 = sregs->cr2;
 	mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
-
-	down_read(&vcpu->kvm->slots_lock);
-	if (gfn_to_memslot(vcpu->kvm, sregs->cr3 >> PAGE_SHIFT))
-		vcpu->arch.cr3 = sregs->cr3;
-	else
-		set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
-	up_read(&vcpu->kvm->slots_lock);
+	vcpu->arch.cr3 = sregs->cr3;
 
 	kvm_set_cr8(vcpu, sregs->cr8);
 
diff --git a/arch/x86/kvm/x86_emulate.c b/arch/x86/kvm/x86_emulate.c
index 616de4628d60..4b12352d0399 100644
--- a/arch/x86/kvm/x86_emulate.c
+++ b/arch/x86/kvm/x86_emulate.c
@@ -60,6 +60,7 @@
 #define SrcImmByte  (6<<4)	/* 8-bit sign-extended immediate operand. */
 #define SrcOne      (7<<4)	/* Implied '1' */
 #define SrcImmUByte (8<<4)      /* 8-bit unsigned immediate operand. */
+#define SrcImmU     (9<<4)      /* Immediate operand, unsigned */
 #define SrcMask     (0xf<<4)
 /* Generic ModRM decode. */
 #define ModRM       (1<<8)
@@ -195,7 +196,7 @@ static u32 opcode_table[256] = {
 	ByteOp | SrcImmUByte, SrcImmUByte,
 	/* 0xE8 - 0xEF */
 	SrcImm | Stack, SrcImm | ImplicitOps,
-	SrcImm | Src2Imm16, SrcImmByte | ImplicitOps,
+	SrcImmU | Src2Imm16, SrcImmByte | ImplicitOps,
 	SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps,
 	SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps,
 	/* 0xF0 - 0xF7 */
@@ -605,6 +606,9 @@ static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
 {
 	int rc = 0;
 
+	/* x86 instructions are limited to 15 bytes. */
+	if (eip + size - ctxt->decode.eip_orig > 15)
+		return X86EMUL_UNHANDLEABLE;
 	eip += ctxt->cs_base;
 	while (size--) {
 		rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
@@ -863,7 +867,7 @@ x86_decode_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
 	/* Shadow copy of register state. Committed on successful emulation. */
 
 	memset(c, 0, sizeof(struct decode_cache));
-	c->eip = kvm_rip_read(ctxt->vcpu);
+	c->eip = c->eip_orig = kvm_rip_read(ctxt->vcpu);
 	ctxt->cs_base = seg_base(ctxt, VCPU_SREG_CS);
 	memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
 
@@ -1027,6 +1031,7 @@ done_prefixes:
 		c->src.type = OP_MEM;
 		break;
 	case SrcImm:
+	case SrcImmU:
 		c->src.type = OP_IMM;
 		c->src.ptr = (unsigned long *)c->eip;
 		c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
@@ -1044,6 +1049,19 @@ done_prefixes:
 			c->src.val = insn_fetch(s32, 4, c->eip);
 			break;
 		}
+		if ((c->d & SrcMask) == SrcImmU) {
+			switch (c->src.bytes) {
+			case 1:
+				c->src.val &= 0xff;
+				break;
+			case 2:
+				c->src.val &= 0xffff;
+				break;
+			case 4:
+				c->src.val &= 0xffffffff;
+				break;
+			}
+		}
 		break;
 	case SrcImmByte:
 	case SrcImmUByte:
diff --git a/arch/x86/mm/Makefile b/arch/x86/mm/Makefile
index eefdeee8a871..0088329b564b 100644
--- a/arch/x86/mm/Makefile
+++ b/arch/x86/mm/Makefile
@@ -1,6 +1,11 @@
 obj-y	:=  init.o init_$(BITS).o fault.o ioremap.o extable.o pageattr.o mmap.o \
 	    pat.o pgtable.o gup.o
 
+# Make sure __phys_addr has no stackprotector
+nostackp := $(call cc-option, -fno-stack-protector)
+CFLAGS_ioremap.o		:= $(nostackp)
+CFLAGS_init.o			:= $(nostackp)
+
 obj-$(CONFIG_SMP)		+= tlb.o
 
 obj-$(CONFIG_X86_32)		+= pgtable_32.o iomap_32.o
diff --git a/arch/x86/mm/mmap.c b/arch/x86/mm/mmap.c
index 165829600566..c8191defc38a 100644
--- a/arch/x86/mm/mmap.c
+++ b/arch/x86/mm/mmap.c
@@ -29,13 +29,26 @@
 #include <linux/random.h>
 #include <linux/limits.h>
 #include <linux/sched.h>
+#include <asm/elf.h>
+
+static unsigned int stack_maxrandom_size(void)
+{
+	unsigned int max = 0;
+	if ((current->flags & PF_RANDOMIZE) &&
+		!(current->personality & ADDR_NO_RANDOMIZE)) {
+		max = ((-1U) & STACK_RND_MASK) << PAGE_SHIFT;
+	}
+
+	return max;
+}
+
 
 /*
  * Top of mmap area (just below the process stack).
  *
- * Leave an at least ~128 MB hole.
+ * Leave an at least ~128 MB hole with possible stack randomization.
  */
-#define MIN_GAP (128*1024*1024)
+#define MIN_GAP (128*1024*1024UL + stack_maxrandom_size())
 #define MAX_GAP (TASK_SIZE/6*5)
 
 /*
diff --git a/arch/x86/mm/pageattr.c b/arch/x86/mm/pageattr.c
index 7e600c1962db..fbb46d62ee5d 100644
--- a/arch/x86/mm/pageattr.c
+++ b/arch/x86/mm/pageattr.c
@@ -143,6 +143,7 @@ void clflush_cache_range(void *vaddr, unsigned int size)
 
 	mb();
 }
+EXPORT_SYMBOL_GPL(clflush_cache_range);
 
 static void __cpa_flush_all(void *arg)
 {
@@ -822,6 +823,7 @@ static int change_page_attr_set_clr(unsigned long *addr, int numpages,
 {
 	struct cpa_data cpa;
 	int ret, cache, checkalias;
+	unsigned long baddr = 0;
 
 	/*
 	 * Check, if we are requested to change a not supported
@@ -853,6 +855,11 @@ static int change_page_attr_set_clr(unsigned long *addr, int numpages,
 			 */
 			WARN_ON_ONCE(1);
 		}
+		/*
+		 * Save address for cache flush. *addr is modified in the call
+		 * to __change_page_attr_set_clr() below.
+		 */
+		baddr = *addr;
 	}
 
 	/* Must avoid aliasing mappings in the highmem code */
@@ -900,7 +907,7 @@ static int change_page_attr_set_clr(unsigned long *addr, int numpages,
 			cpa_flush_array(addr, numpages, cache,
 					cpa.flags, pages);
 		} else
-			cpa_flush_range(*addr, numpages, cache);
+			cpa_flush_range(baddr, numpages, cache);
 	} else
 		cpa_flush_all(cache);
 
diff --git a/arch/x86/pci/i386.c b/arch/x86/pci/i386.c
index 52e62e57fedd..5da8792b48a4 100644
--- a/arch/x86/pci/i386.c
+++ b/arch/x86/pci/i386.c
@@ -282,6 +282,15 @@ int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
 		return -EINVAL;
 
 	prot = pgprot_val(vma->vm_page_prot);
+
+	/*
+ 	 * Return error if pat is not enabled and write_combine is requested.
+ 	 * Caller can followup with UC MINUS request and add a WC mtrr if there
+ 	 * is a free mtrr slot.
+ 	 */
+	if (!pat_enabled && write_combine)
+		return -EINVAL;
+
 	if (pat_enabled && write_combine)
 		prot |= _PAGE_CACHE_WC;
 	else if (pat_enabled || boot_cpu_data.x86 > 3)
diff --git a/arch/x86/xen/Makefile b/arch/x86/xen/Makefile
index 7410640db173..3bb4fc21f4f2 100644
--- a/arch/x86/xen/Makefile
+++ b/arch/x86/xen/Makefile
@@ -8,6 +8,7 @@ endif
 # Make sure early boot has no stackprotector
 nostackp := $(call cc-option, -fno-stack-protector)
 CFLAGS_enlighten.o		:= $(nostackp)
+CFLAGS_mmu.o			:= $(nostackp)
 
 obj-y		:= enlighten.o setup.o multicalls.o mmu.o irq.o \
 			time.o xen-asm.o xen-asm_$(BITS).o \
@@ -16,3 +17,4 @@ obj-y		:= enlighten.o setup.o multicalls.o mmu.o irq.o \
 obj-$(CONFIG_SMP)		+= smp.o
 obj-$(CONFIG_PARAVIRT_SPINLOCKS)+= spinlock.o
 obj-$(CONFIG_XEN_DEBUG_FS)	+= debugfs.o
+
diff --git a/arch/x86/xen/enlighten.c b/arch/x86/xen/enlighten.c
index eb33aaa8415d..a11a115d82d3 100644
--- a/arch/x86/xen/enlighten.c
+++ b/arch/x86/xen/enlighten.c
@@ -51,6 +51,7 @@
 #include <asm/pgtable.h>
 #include <asm/tlbflush.h>
 #include <asm/reboot.h>
+#include <asm/stackprotector.h>
 
 #include "xen-ops.h"
 #include "mmu.h"
@@ -177,6 +178,7 @@ static __read_mostly unsigned int cpuid_leaf1_ecx_mask = ~0;
 static void xen_cpuid(unsigned int *ax, unsigned int *bx,
 		      unsigned int *cx, unsigned int *dx)
 {
+	unsigned maskebx = ~0;
 	unsigned maskecx = ~0;
 	unsigned maskedx = ~0;
 
@@ -184,9 +186,16 @@ static void xen_cpuid(unsigned int *ax, unsigned int *bx,
 	 * Mask out inconvenient features, to try and disable as many
 	 * unsupported kernel subsystems as possible.
 	 */
-	if (*ax == 1) {
+	switch (*ax) {
+	case 1:
 		maskecx = cpuid_leaf1_ecx_mask;
 		maskedx = cpuid_leaf1_edx_mask;
+		break;
+
+	case 0xb:
+		/* Suppress extended topology stuff */
+		maskebx = 0;
+		break;
 	}
 
 	asm(XEN_EMULATE_PREFIX "cpuid"
@@ -196,6 +205,7 @@ static void xen_cpuid(unsigned int *ax, unsigned int *bx,
 		  "=d" (*dx)
 		: "0" (*ax), "2" (*cx));
 
+	*bx &= maskebx;
 	*cx &= maskecx;
 	*dx &= maskedx;
 }
@@ -330,18 +340,28 @@ static void xen_load_gdt(const struct desc_ptr *dtr)
 	unsigned long frames[pages];
 	int f;
 
-	/* A GDT can be up to 64k in size, which corresponds to 8192
-	   8-byte entries, or 16 4k pages.. */
+	/*
+	 * A GDT can be up to 64k in size, which corresponds to 8192
+	 * 8-byte entries, or 16 4k pages..
+	 */
 
 	BUG_ON(size > 65536);
 	BUG_ON(va & ~PAGE_MASK);
 
 	for (f = 0; va < dtr->address + size; va += PAGE_SIZE, f++) {
 		int level;
-		pte_t *ptep = lookup_address(va, &level);
+		pte_t *ptep;
 		unsigned long pfn, mfn;
 		void *virt;
 
+		/*
+		 * The GDT is per-cpu and is in the percpu data area.
+		 * That can be virtually mapped, so we need to do a
+		 * page-walk to get the underlying MFN for the
+		 * hypercall.  The page can also be in the kernel's
+		 * linear range, so we need to RO that mapping too.
+		 */
+		ptep = lookup_address(va, &level);
 		BUG_ON(ptep == NULL);
 
 		pfn = pte_pfn(*ptep);
@@ -358,6 +378,44 @@ static void xen_load_gdt(const struct desc_ptr *dtr)
 		BUG();
 }
 
+/*
+ * load_gdt for early boot, when the gdt is only mapped once
+ */
+static __init void xen_load_gdt_boot(const struct desc_ptr *dtr)
+{
+	unsigned long va = dtr->address;
+	unsigned int size = dtr->size + 1;
+	unsigned pages = (size + PAGE_SIZE - 1) / PAGE_SIZE;
+	unsigned long frames[pages];
+	int f;
+
+	/*
+	 * A GDT can be up to 64k in size, which corresponds to 8192
+	 * 8-byte entries, or 16 4k pages..
+	 */
+
+	BUG_ON(size > 65536);
+	BUG_ON(va & ~PAGE_MASK);
+
+	for (f = 0; va < dtr->address + size; va += PAGE_SIZE, f++) {
+		pte_t pte;
+		unsigned long pfn, mfn;
+
+		pfn = virt_to_pfn(va);
+		mfn = pfn_to_mfn(pfn);
+
+		pte = pfn_pte(pfn, PAGE_KERNEL_RO);
+
+		if (HYPERVISOR_update_va_mapping((unsigned long)va, pte, 0))
+			BUG();
+
+		frames[f] = mfn;
+	}
+
+	if (HYPERVISOR_set_gdt(frames, size / sizeof(struct desc_struct)))
+		BUG();
+}
+
 static void load_TLS_descriptor(struct thread_struct *t,
 				unsigned int cpu, unsigned int i)
 {
@@ -581,6 +639,29 @@ static void xen_write_gdt_entry(struct desc_struct *dt, int entry,
 	preempt_enable();
 }
 
+/*
+ * Version of write_gdt_entry for use at early boot-time needed to
+ * update an entry as simply as possible.
+ */
+static __init void xen_write_gdt_entry_boot(struct desc_struct *dt, int entry,
+					    const void *desc, int type)
+{
+	switch (type) {
+	case DESC_LDT:
+	case DESC_TSS:
+		/* ignore */
+		break;
+
+	default: {
+		xmaddr_t maddr = virt_to_machine(&dt[entry]);
+
+		if (HYPERVISOR_update_descriptor(maddr.maddr, *(u64 *)desc))
+			dt[entry] = *(struct desc_struct *)desc;
+	}
+
+	}
+}
+
 static void xen_load_sp0(struct tss_struct *tss,
 			 struct thread_struct *thread)
 {
@@ -965,6 +1046,23 @@ static const struct machine_ops __initdata xen_machine_ops = {
 	.emergency_restart = xen_emergency_restart,
 };
 
+/*
+ * Set up the GDT and segment registers for -fstack-protector.  Until
+ * we do this, we have to be careful not to call any stack-protected
+ * function, which is most of the kernel.
+ */
+static void __init xen_setup_stackprotector(void)
+{
+	pv_cpu_ops.write_gdt_entry = xen_write_gdt_entry_boot;
+	pv_cpu_ops.load_gdt = xen_load_gdt_boot;
+
+	setup_stack_canary_segment(0);
+	switch_to_new_gdt(0);
+
+	pv_cpu_ops.write_gdt_entry = xen_write_gdt_entry;
+	pv_cpu_ops.load_gdt = xen_load_gdt;
+}
+
 /* First C function to be called on Xen boot */
 asmlinkage void __init xen_start_kernel(void)
 {
@@ -983,14 +1081,34 @@ asmlinkage void __init xen_start_kernel(void)
 	pv_apic_ops = xen_apic_ops;
 	pv_mmu_ops = xen_mmu_ops;
 
-#ifdef CONFIG_X86_64
 	/*
-	 * Setup percpu state.  We only need to do this for 64-bit
-	 * because 32-bit already has %fs set properly.
+	 * Set up some pagetable state before starting to set any ptes.
 	 */
-	load_percpu_segment(0);
+
+	/* Prevent unwanted bits from being set in PTEs. */
+	__supported_pte_mask &= ~_PAGE_GLOBAL;
+	if (!xen_initial_domain())
+		__supported_pte_mask &= ~(_PAGE_PWT | _PAGE_PCD);
+
+	__supported_pte_mask |= _PAGE_IOMAP;
+
+#ifdef CONFIG_X86_64
+	/* Work out if we support NX */
+	check_efer();
 #endif
 
+	xen_setup_features();
+
+	/* Get mfn list */
+	if (!xen_feature(XENFEAT_auto_translated_physmap))
+		xen_build_dynamic_phys_to_machine();
+
+	/*
+	 * Set up kernel GDT and segment registers, mainly so that
+	 * -fstack-protector code can be executed.
+	 */
+	xen_setup_stackprotector();
+
 	xen_init_irq_ops();
 	xen_init_cpuid_mask();
 
@@ -1001,8 +1119,6 @@ asmlinkage void __init xen_start_kernel(void)
 	set_xen_basic_apic_ops();
 #endif
 
-	xen_setup_features();
-
 	if (xen_feature(XENFEAT_mmu_pt_update_preserve_ad)) {
 		pv_mmu_ops.ptep_modify_prot_start = xen_ptep_modify_prot_start;
 		pv_mmu_ops.ptep_modify_prot_commit = xen_ptep_modify_prot_commit;
@@ -1019,22 +1135,8 @@ asmlinkage void __init xen_start_kernel(void)
 
 	xen_smp_init();
 
-	/* Get mfn list */
-	if (!xen_feature(XENFEAT_auto_translated_physmap))
-		xen_build_dynamic_phys_to_machine();
-
 	pgd = (pgd_t *)xen_start_info->pt_base;
 
-	/* Prevent unwanted bits from being set in PTEs. */
-	__supported_pte_mask &= ~_PAGE_GLOBAL;
-	if (!xen_initial_domain())
-		__supported_pte_mask &= ~(_PAGE_PWT | _PAGE_PCD);
-
-#ifdef CONFIG_X86_64
-	/* Work out if we support NX */
-	check_efer();
-#endif
-
 	/* Don't do the full vcpu_info placement stuff until we have a
 	   possible map and a non-dummy shared_info. */
 	per_cpu(xen_vcpu, 0) = &HYPERVISOR_shared_info->vcpu_info[0];
diff --git a/arch/x86/xen/smp.c b/arch/x86/xen/smp.c
index 429834ec1687..fe03eeed7b48 100644
--- a/arch/x86/xen/smp.c
+++ b/arch/x86/xen/smp.c
@@ -236,6 +236,7 @@ cpu_initialize_context(unsigned int cpu, struct task_struct *idle)
 	ctxt->user_regs.ss = __KERNEL_DS;
 #ifdef CONFIG_X86_32
 	ctxt->user_regs.fs = __KERNEL_PERCPU;
+	ctxt->user_regs.gs = __KERNEL_STACK_CANARY;
 #else
 	ctxt->gs_base_kernel = per_cpu_offset(cpu);
 #endif
diff --git a/arch/x86/xen/spinlock.c b/arch/x86/xen/spinlock.c
index 5601506f2dd9..36a5141108df 100644
--- a/arch/x86/xen/spinlock.c
+++ b/arch/x86/xen/spinlock.c
@@ -187,7 +187,6 @@ static noinline int xen_spin_lock_slow(struct raw_spinlock *lock, bool irq_enabl
 	struct xen_spinlock *prev;
 	int irq = __get_cpu_var(lock_kicker_irq);
 	int ret;
-	unsigned long flags;
 	u64 start;
 
 	/* If kicker interrupts not initialized yet, just spin */
@@ -199,16 +198,12 @@ static noinline int xen_spin_lock_slow(struct raw_spinlock *lock, bool irq_enabl
 	/* announce we're spinning */
 	prev = spinning_lock(xl);
 
-	flags = __raw_local_save_flags();
-	if (irq_enable) {
-		ADD_STATS(taken_slow_irqenable, 1);
-		raw_local_irq_enable();
-	}
-
 	ADD_STATS(taken_slow, 1);
 	ADD_STATS(taken_slow_nested, prev != NULL);
 
 	do {
+		unsigned long flags;
+
 		/* clear pending */
 		xen_clear_irq_pending(irq);
 
@@ -228,6 +223,12 @@ static noinline int xen_spin_lock_slow(struct raw_spinlock *lock, bool irq_enabl
 			goto out;
 		}
 
+		flags = __raw_local_save_flags();
+		if (irq_enable) {
+			ADD_STATS(taken_slow_irqenable, 1);
+			raw_local_irq_enable();
+		}
+
 		/*
 		 * Block until irq becomes pending.  If we're
 		 * interrupted at this point (after the trylock but
@@ -238,13 +239,15 @@ static noinline int xen_spin_lock_slow(struct raw_spinlock *lock, bool irq_enabl
 		 * pending.
 		 */
 		xen_poll_irq(irq);
+
+		raw_local_irq_restore(flags);
+
 		ADD_STATS(taken_slow_spurious, !xen_test_irq_pending(irq));
 	} while (!xen_test_irq_pending(irq)); /* check for spurious wakeups */
 
 	kstat_incr_irqs_this_cpu(irq, irq_to_desc(irq));
 
 out:
-	raw_local_irq_restore(flags);
 	unspinning_lock(xl, prev);
 	spin_time_accum_blocked(start);
 
@@ -323,8 +326,13 @@ static void xen_spin_unlock(struct raw_spinlock *lock)
 	smp_wmb();		/* make sure no writes get moved after unlock */
 	xl->lock = 0;		/* release lock */
 
-	/* make sure unlock happens before kick */
-	barrier();
+	/*
+	 * Make sure unlock happens before checking for waiting
+	 * spinners.  We need a strong barrier to enforce the
+	 * write-read ordering to different memory locations, as the
+	 * CPU makes no implied guarantees about their ordering.
+	 */
+	mb();
 
 	if (unlikely(xl->spinners))
 		xen_spin_unlock_slow(xl);
diff --git a/arch/xtensa/kernel/Makefile b/arch/xtensa/kernel/Makefile
index fe3186de6a33..6f56d95f2c1e 100644
--- a/arch/xtensa/kernel/Makefile
+++ b/arch/xtensa/kernel/Makefile
@@ -27,7 +27,8 @@ sed-y = -e 's/(\(\.[a-z]*it\|\.ref\|\)\.text)/(\1.literal \1.text)/g'	\
 	-e 's/(\(\.text\.[a-z]*\))/(\1.literal \1)/g'
 
 quiet_cmd__cpp_lds_S = LDS     $@
-      cmd__cpp_lds_S = $(CPP) $(cpp_flags) -D__ASSEMBLY__ $< | sed $(sed-y) >$@
+      cmd__cpp_lds_S = $(CPP) $(cpp_flags) -P -C -Uxtensa -D__ASSEMBLY__ $< \
+                       | sed $(sed-y) >$@
 
 $(obj)/vmlinux.lds: $(src)/vmlinux.lds.S FORCE
 	$(call if_changed_dep,_cpp_lds_S)