diff options
| author | Deepak Saxena <dsaxena@plexity.net> | 2006-05-31 16:14:05 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@g5.osdl.org> | 2006-05-31 16:27:44 -0700 |
| commit | 5cedae9ca752a43cfb1074907d12c9f01fbebd45 (patch) | |
| tree | 30bff4b8211984984c6614b7fc530ff916630d6b /arch | |
| parent | 29f767a254be8fd44fb5d2b5a48e9cda8399c4ea (diff) | |
[PATCH] ARM: Fix XScale PMD setting
The ARM Architecture Reference Manual lists bit 4 of the PMD as "implementation
defined" and it must be set to zero on Intel XScale CPUs or the cache does
not behave properly. Found by Mike Rapoport while debugging a flash issue
on the PXA255:
http://marc.10east.com/?l=linux-arm-kernel&m=114845287600782&w=1
Signed-off-by: Deepak Saxena <dsaxena@plexity.net>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mm/mm-armv.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/mm/mm-armv.c b/arch/arm/mm/mm-armv.c index f14b2d0f3690..95273de4f772 100644 --- a/arch/arm/mm/mm-armv.c +++ b/arch/arm/mm/mm-armv.c @@ -376,7 +376,7 @@ void __init build_mem_type_table(void) ecc_mask = 0; } - if (cpu_arch <= CPU_ARCH_ARMv5TEJ) { + if (cpu_arch <= CPU_ARCH_ARMv5TEJ && !cpu_is_xscale()) { for (i = 0; i < ARRAY_SIZE(mem_types); i++) { if (mem_types[i].prot_l1) mem_types[i].prot_l1 |= PMD_BIT4; @@ -631,7 +631,7 @@ void setup_mm_for_reboot(char mode) pgd = init_mm.pgd; base_pmdval = PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | PMD_TYPE_SECT; - if (cpu_architecture() <= CPU_ARCH_ARMv5TEJ) + if (cpu_architecture() <= CPU_ARCH_ARMv5TEJ && !cpu_is_xscale()) base_pmdval |= PMD_BIT4; for (i = 0; i < FIRST_USER_PGD_NR + USER_PTRS_PER_PGD; i++, pgd++) { |