diff options
| author | Nicolin Chen <b42378@freescale.com> | 2013-08-23 19:42:56 +0800 |
|---|---|---|
| committer | Nicolin Chen <b42378@freescale.com> | 2013-08-29 17:43:27 +0800 |
| commit | 57963075b0a495fd8180f48341e2f06f3a8149b9 (patch) | |
| tree | 5fc65739114d08254bdf64c27a99c7953e538bb0 /arch | |
| parent | b1d6221943c487e47a4cab9fe16cf507757b3e2b (diff) | |
ENGR00276567-3 ARM: imx6q: Set pll4 as ssi's parent
PLL4 is a flexible pll that can be set to a value as we need,
so we set it to an value that can easily derive 44.1K and 48K
and then put ssi baud clock as its child clock.
Signed-off-by: Nicolin Chen <b42378@freescale.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-imx/clk-imx6q.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index 543814a7d412..738cd7c48b4b 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c @@ -507,6 +507,14 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) if (ret) pr_warn("failed to set up CLKO: %d\n", ret); + /* Audio clocks */ + clk_set_parent(clk[ssi1_sel], clk[pll4_audio_div]); + clk_set_parent(clk[ssi2_sel], clk[pll4_audio_div]); + clk_set_parent(clk[ssi3_sel], clk[pll4_audio_div]); + + /* Set pll4_audio to a value that can derive 5K-88.2KHz and 8K-96KHz */ + clk_set_rate(clk[pll4_audio_div], 541900800); + /* Set initial power mode */ imx6_set_lpm(WAIT_CLOCKED); |