ENGR00242201 imx: Update specific clock code for MX6DL

-Update the parent of gpu2d_core for mx6dl.
-Update the parent of gpu3d_shader and gpu3d_core for mx6dl.
-Update the clock of gpu3d_shader and gpu3d_core for mx6dl.
The code change is cherry-picked from patch 00e75bcba16d.

Signed-off-by: Loren Huang <b02279@freescale.com>
(cherry picked from commit 2b335e6232b807d114a5a57e0b5956ab794786a4)

1 files changed, 20 insertions, 4 deletions

diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 8373e471d77f..25734ed936c8 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -679,11 +679,27 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
 	imx_clk_set_parent(clk[pcie_axi_sel], clk[axi]);
 
 	/* gpu clock initilazation */
+	/*
+	 * On mx6dl, 2d core clock sources(sel, podf) is from 3d
+	 * shader core clock, but 3d shader clock multiplexer of
+	 * mx6dl is different. For instance the equivalent of
+	 * pll2_pfd_594M on mx6q is pll2_pfd_528M on mx6dl.
+	 * Make a note here.
+	 */
 	imx_clk_set_parent(clk[gpu3d_shader_sel], clk[pll2_pfd1_594m]);
-	imx_clk_set_rate(clk[gpu3d_shader], 594000000);
-	imx_clk_set_parent(clk[gpu3d_core_sel], clk[mmdc_ch0_axi]);
-	imx_clk_set_rate(clk[gpu3d_core], 528000000);
-	imx_clk_set_parent(clk[gpu2d_core_sel], clk[pll3_usb_otg]);
+	if (cpu_is_imx6dl()) {
+		imx_clk_set_rate(clk[gpu2d_core], 528000000);
+		/* for mx6dl, change gpu3d_core parent to 594_PFD*/
+		imx_clk_set_parent(clk[gpu3d_core_sel], clk[pll2_pfd1_594m]);
+		imx_clk_set_rate(clk[gpu3d_core], 528000000);
+	} else if (cpu_is_imx6q()) {
+		imx_clk_set_rate(clk[gpu3d_shader], 594000000);
+		imx_clk_set_parent(clk[gpu3d_core_sel], clk[mmdc_ch0_axi]);
+		imx_clk_set_rate(clk[gpu3d_core], 528000000);
+		imx_clk_set_parent(clk[gpu2d_core_sel], clk[pll3_usb_otg]);
+	}
+
+
 
 	for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
 		imx_clk_prepare_enable(clk[clks_init_on[i]]);