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authorRanjani Vaidyanathan <ra5478@freescale.com>2013-05-21 14:40:13 -0500
committerRanjani Vaidyanathan <ra5478@freescale.com>2013-05-23 12:59:17 -0500
commit1e4a59e4c462f2222d311773067670e6fcaa1df7 (patch)
treee2930ec513845af88378d12425192bd9967f09df /arch
parentd6f32393eaf455ce3c32d4e9bafd34d9091eaf45 (diff)
ENGR00263639 MX6SL-Ensure Audio PLL (PLL4) is enabled correctly
The following commit: 6f394da8b374dc4a063209deedeb5d8a62ae4c74 introduced a bug that does not enable audio PLL when its frequency is something other than 24MHz. This patch ensures that Audio PLL will be enabled for all frequencies. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
Diffstat (limited to 'arch')
-rwxr-xr-xarch/arm/mach-mx6/clock_mx6sl.c6
1 files changed, 4 insertions, 2 deletions
diff --git a/arch/arm/mach-mx6/clock_mx6sl.c b/arch/arm/mach-mx6/clock_mx6sl.c
index fc42925d2a42..d8f33877bfe0 100755
--- a/arch/arm/mach-mx6/clock_mx6sl.c
+++ b/arch/arm/mach-mx6/clock_mx6sl.c
@@ -451,10 +451,12 @@ static int _clk_pll_enable(struct clk *clk)
}
/* Enable the PLL output now*/
reg = __raw_readl(pllbase);
+
+ /* If audio PLL is set to 24MHz, leave it in bypass mode. */
if (clk != &pll4_audio_main_clk || !audio_pll_bypass)
reg &= ~ANADIG_PLL_BYPASS;
- else
- reg |= ANADIG_PLL_ENABLE;
+
+ reg |= ANADIG_PLL_ENABLE;
__raw_writel(reg, pllbase);