ENGR00318063-11: ARM: imx6: add return check for clock calls

There are a bunch of clk_enable_prepare, clk_set_parent and clk_set_rate
calls in imx6 clock driver's initialization.  They are called without
retunr check.  If there is something going wrong with the calls, they
will just fail silently.

The patch creates a set of helper functions imx_clk_enable_prepare,
imx_clk_set_parent and imx_clk_set_rate, and use them instead from clock
initialization to check the return and print error message to tell
failures if any.

Signed-off-by: Shawn Guo <shawn.guo@freescale.com>

4 files changed, 133 insertions, 125 deletions

diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 4e7259669f4e..8f347d5f21f6 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -293,7 +293,6 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
 	struct device_node *np;
 	void __iomem *base;
 	int i, irq;
-	int ret;
 	u32 reg;
 
 	clk[dummy] = imx_clk_fixed("dummy", 0);
@@ -673,74 +672,69 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
 	 * We can not get the 100MHz from the pll2_pfd0_352m.
 	 * So choose pll2_pfd2_396m as enfc_sel's parent.
 	 */
-	clk_set_parent(clk[enfc_sel], clk[pll2_pfd2_396m]);
+	imx_clk_set_parent(clk[enfc_sel], clk[pll2_pfd2_396m]);
 
 	/* Set the parent clks of PCIe lvds1 and pcie_axi to be sata ref, axi */
-	if (clk_set_parent(clk[lvds1_sel], clk[sata_ref]))
-		pr_err("Failed to set PCIe bus parent clk.\n");
-	if (clk_set_parent(clk[pcie_axi_sel], clk[axi]))
-		pr_err("Failed to set PCIe parent clk.\n");
+	imx_clk_set_parent(clk[lvds1_sel], clk[sata_ref]);
+	imx_clk_set_parent(clk[pcie_axi_sel], clk[axi]);
 
 	/* gpu clock initilazation */
-	clk_set_parent(clk[gpu3d_shader_sel], clk[pll2_pfd1_594m]);
-	clk_set_rate(clk[gpu3d_shader], 594000000);
-	clk_set_parent(clk[gpu3d_core_sel], clk[mmdc_ch0_axi]);
-	clk_set_rate(clk[gpu3d_core], 528000000);
-	clk_set_parent(clk[gpu2d_core_sel], clk[pll3_usb_otg]);
+	imx_clk_set_parent(clk[gpu3d_shader_sel], clk[pll2_pfd1_594m]);
+	imx_clk_set_rate(clk[gpu3d_shader], 594000000);
+	imx_clk_set_parent(clk[gpu3d_core_sel], clk[mmdc_ch0_axi]);
+	imx_clk_set_rate(clk[gpu3d_core], 528000000);
+	imx_clk_set_parent(clk[gpu2d_core_sel], clk[pll3_usb_otg]);
 
 	for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
-		clk_prepare_enable(clk[clks_init_on[i]]);
+		imx_clk_prepare_enable(clk[clks_init_on[i]]);
 
 	if (IS_ENABLED(CONFIG_USB_MXS_PHY)) {
-		clk_prepare_enable(clk[usbphy1_gate]);
-		clk_prepare_enable(clk[usbphy2_gate]);
+		imx_clk_prepare_enable(clk[usbphy1_gate]);
+		imx_clk_prepare_enable(clk[usbphy2_gate]);
 	}
 
 	/* ipu clock initialization */
 	init_ldb_clks();
-	clk_set_parent(clk[ipu1_di0_pre_sel], clk[pll5_video_div]);
-	clk_set_parent(clk[ipu1_di1_pre_sel], clk[pll5_video_div]);
-	clk_set_parent(clk[ipu2_di0_pre_sel], clk[pll5_video_div]);
-	clk_set_parent(clk[ipu2_di1_pre_sel], clk[pll5_video_div]);
-	clk_set_parent(clk[ipu1_di0_sel], clk[ipu1_di0_pre]);
-	clk_set_parent(clk[ipu1_di1_sel], clk[ipu1_di1_pre]);
-	clk_set_parent(clk[ipu2_di0_sel], clk[ipu2_di0_pre]);
-	clk_set_parent(clk[ipu2_di1_sel], clk[ipu2_di1_pre]);
+	imx_clk_set_parent(clk[ipu1_di0_pre_sel], clk[pll5_video_div]);
+	imx_clk_set_parent(clk[ipu1_di1_pre_sel], clk[pll5_video_div]);
+	imx_clk_set_parent(clk[ipu2_di0_pre_sel], clk[pll5_video_div]);
+	imx_clk_set_parent(clk[ipu2_di1_pre_sel], clk[pll5_video_div]);
+	imx_clk_set_parent(clk[ipu1_di0_sel], clk[ipu1_di0_pre]);
+	imx_clk_set_parent(clk[ipu1_di1_sel], clk[ipu1_di1_pre]);
+	imx_clk_set_parent(clk[ipu2_di0_sel], clk[ipu2_di0_pre]);
+	imx_clk_set_parent(clk[ipu2_di1_sel], clk[ipu2_di1_pre]);
 	if (cpu_is_imx6dl()) {
-		clk_set_rate(clk[pll3_pfd1_540m], 540000000);
-		clk_set_parent(clk[ipu1_sel], clk[pll3_pfd1_540m]);
-		clk_set_parent(clk[axi_alt_sel], clk[pll3_pfd1_540m]);
-		clk_set_parent(clk[axi_sel], clk[axi_alt_sel]);
+		imx_clk_set_rate(clk[pll3_pfd1_540m], 540000000);
+		imx_clk_set_parent(clk[ipu1_sel], clk[pll3_pfd1_540m]);
+		imx_clk_set_parent(clk[axi_alt_sel], clk[pll3_pfd1_540m]);
+		imx_clk_set_parent(clk[axi_sel], clk[axi_alt_sel]);
 		/* set epdc/pxp axi clock to 200Mhz */
-		clk_set_parent(clk[ipu2_sel], clk[pll2_pfd2_396m]);
-		clk_set_rate(clk[ipu2], 200000000);
+		imx_clk_set_parent(clk[ipu2_sel], clk[pll2_pfd2_396m]);
+		imx_clk_set_rate(clk[ipu2], 200000000);
 	} else if (cpu_is_imx6q()) {
-		clk_set_parent(clk[ipu1_sel], clk[mmdc_ch0_axi]);
-		clk_set_parent(clk[ipu2_sel], clk[mmdc_ch0_axi]);
+		imx_clk_set_parent(clk[ipu1_sel], clk[mmdc_ch0_axi]);
+		imx_clk_set_parent(clk[ipu2_sel], clk[mmdc_ch0_axi]);
 	}
 
 	/*
 	 * Let's initially set up CLKO with OSC24M, since this configuration
 	 * is widely used by imx6q board designs to clock audio codec.
 	 */
-	ret = clk_set_parent(clk[cko2_sel], clk[osc]);
-	if (!ret)
-		ret = clk_set_parent(clk[cko], clk[cko2]);
-	if (ret)
-		pr_warn("failed to set up CLKO: %d\n", ret);
+	imx_clk_set_parent(clk[cko2_sel], clk[osc]);
+	imx_clk_set_parent(clk[cko], clk[cko2]);
 
 	/* Audio clocks */
-	clk_set_parent(clk[ssi1_sel], clk[pll4_audio_div]);
-	clk_set_parent(clk[ssi2_sel], clk[pll4_audio_div]);
-	clk_set_parent(clk[ssi3_sel], clk[pll4_audio_div]);
-	clk_set_parent(clk[esai_sel], clk[pll4_audio_div]);
-	clk_set_parent(clk[spdif_sel], clk[pll3_pfd3_454m]);
-	clk_set_rate(clk[spdif_podf], 227368421);
-	clk_set_parent(clk[spdif1_sel], clk[pll3_usb_otg]);
-	clk_set_rate(clk[spdif1_sel], 7500000);
+	imx_clk_set_parent(clk[ssi1_sel], clk[pll4_audio_div]);
+	imx_clk_set_parent(clk[ssi2_sel], clk[pll4_audio_div]);
+	imx_clk_set_parent(clk[ssi3_sel], clk[pll4_audio_div]);
+	imx_clk_set_parent(clk[esai_sel], clk[pll4_audio_div]);
+	imx_clk_set_parent(clk[spdif_sel], clk[pll3_pfd3_454m]);
+	imx_clk_set_rate(clk[spdif_podf], 227368421);
+	imx_clk_set_parent(clk[spdif1_sel], clk[pll3_usb_otg]);
+	imx_clk_set_rate(clk[spdif1_sel], 7500000);
 
 	/* Set pll4_audio to a value that can derive 5K-88.2KHz and 8K-96KHz */
-	clk_set_rate(clk[pll4_audio_div], 541900800);
+	imx_clk_set_rate(clk[pll4_audio_div], 541900800);
 
 #ifdef CONFIG_MX6_VPU_352M
 	/*
@@ -752,8 +746,8 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
 	 * all modules that sourceing clk from PLL2_PFD2 will
 	 * be impacted.
 	 */
-	clk_set_rate(clk[pll2_pfd2_396m], 352000000);
-	clk_set_parent(clk[vpu_axi_sel], clk[pll2_pfd2_396m]);
+	imx_clk_set_rate(clk[pll2_pfd2_396m], 352000000);
+	imx_clk_set_parent(clk[vpu_axi_sel], clk[pll2_pfd2_396m]);
 	pr_info("VPU 352M is enabled!\n");
 #endif
 
diff --git a/arch/arm/mach-imx/clk-imx6sl.c b/arch/arm/mach-imx/clk-imx6sl.c
index c99b51148035..e10371abf58a 100644
--- a/arch/arm/mach-imx/clk-imx6sl.c
+++ b/arch/arm/mach-imx/clk-imx6sl.c
@@ -119,9 +119,9 @@ void imx6sl_set_wait_clk(bool enter)
 			 * to run from the 24MHz OSC, as there is no way to
 			 * get 28.8MHz when ARM is sourced from PLL1.
 			 */
-			clk_set_parent(clks[IMX6SL_CLK_STEP],
+			imx_clk_set_parent(clks[IMX6SL_CLK_STEP],
 							clks[IMX6SL_CLK_OSC]);
-			clk_set_parent(clks[IMX6SL_CLK_PLL1_SW],
+			imx_clk_set_parent(clks[IMX6SL_CLK_PLL1_SW],
 							clks[IMX6SL_CLK_STEP]);
 		} else if (audio_bus_freq_mode) {
 			/*
@@ -132,26 +132,26 @@ void imx6sl_set_wait_clk(bool enter)
 			 */
 			pll1_org_rate = clk_get_rate(clks[IMX6SL_CLK_PLL1_SYS]);
 			/* Ensure PLL1 is at 24MHz. */
-			clk_set_rate(clks[IMX6SL_CLK_PLL1_SYS], OSC_RATE);
-			clk_set_parent(clks[IMX6SL_CLK_PLL1_SW], clks[IMX6SL_CLK_PLL1_SYS]);
+			imx_clk_set_rate(clks[IMX6SL_CLK_PLL1_SYS], OSC_RATE);
+			imx_clk_set_parent(clks[IMX6SL_CLK_PLL1_SW], clks[IMX6SL_CLK_PLL1_SYS]);
 		} else
 			new_parent_rate = clk_get_rate(clks[IMX6SL_CLK_PLL1_SW]);
 		wait_podf = (new_parent_rate + max_arm_wait_clk - 1) /
 						max_arm_wait_clk;
 
-		clk_set_rate(clks[IMX6SL_CLK_ARM], new_parent_rate / wait_podf);
+		imx_clk_set_rate(clks[IMX6SL_CLK_ARM], new_parent_rate / wait_podf);
 	} else {
 		if (low_bus_freq_mode)
 			/* Move ARM back to PLL1. */
-			clk_set_parent(clks[IMX6SL_CLK_PLL1_SW],
+			imx_clk_set_parent(clks[IMX6SL_CLK_PLL1_SW],
 				clks[IMX6SL_CLK_PLL1_SYS]);
 		else if (audio_bus_freq_mode) {
 			/* Move ARM back to PLL2_PFD2 via STEP_CLK. */
-			clk_set_parent(clks[IMX6SL_CLK_PLL1_SW], clks[IMX6SL_CLK_STEP]);
-			clk_set_rate(clks[IMX6SL_CLK_PLL1_SYS], pll1_org_rate);
+			imx_clk_set_parent(clks[IMX6SL_CLK_PLL1_SW], clks[IMX6SL_CLK_STEP]);
+			imx_clk_set_rate(clks[IMX6SL_CLK_PLL1_SYS], pll1_org_rate);
 		}
 		parent_rate = clk_get_rate(clks[IMX6SL_CLK_PLL1_SW]);
-		clk_set_rate(clks[IMX6SL_CLK_ARM], parent_rate / cur_arm_podf);
+		imx_clk_set_rate(clks[IMX6SL_CLK_ARM], parent_rate / cur_arm_podf);
 	}
 }
 
@@ -168,7 +168,6 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
 	struct device_node *np;
 	void __iomem *base;
 	int irq;
-	int ret;
 	int i;
 	u32 reg;
 
@@ -401,77 +400,67 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
 	clk_register_clkdev(clks[IMX6SL_CLK_GPT_SERIAL], "per", "imx-gpt.0");
 
 	/* Ensure the AHB clk is at 132MHz. */
-	ret = clk_set_rate(clks[IMX6SL_CLK_AHB], 132000000);
-	if (ret)
-		pr_warn("%s: failed to set AHB clock rate %d\n", __func__, ret);
+	imx_clk_set_rate(clks[IMX6SL_CLK_AHB], 132000000);
 
 	/*
 	 * To prevent the bus clock from being disabled accidently when
 	 * clk_disable() gets called on child clock, let's increment the use
 	 * count of IPG clock by initially calling clk_prepare_enable() on it.
 	 */
-	ret = clk_prepare_enable(clks[IMX6SL_CLK_IPG]);
-	if (ret)
-		pr_warn("%s: failed to enable IPG clock %d\n", __func__, ret);
+	imx_clk_prepare_enable(clks[IMX6SL_CLK_IPG]);
 
 	/*
 	 * Make sure the ARM clk is enabled to maintain the correct usecount
 	 * and enabling/disabling of parent PLLs.
 	 */
-	ret = clk_prepare_enable(clks[IMX6SL_CLK_ARM]);
-	if (ret)
-		pr_warn("%s: failed to enable ARM core clock %d\n",
-			__func__, ret);
+	imx_clk_prepare_enable(clks[IMX6SL_CLK_ARM]);
 
 	/*
 	 * Make sure the MMDC clk is enabled to maintain the correct usecount
 	 * and enabling/disabling of parent PLLs.
 	 */
-	ret = clk_prepare_enable(clks[IMX6SL_CLK_MMDC_ROOT]);
-	if (ret)
-		pr_warn("%s: failed to enable MMDC clock %d\n",
-			__func__, ret);
+	imx_clk_prepare_enable(clks[IMX6SL_CLK_MMDC_ROOT]);
 
 	if (IS_ENABLED(CONFIG_USB_MXS_PHY)) {
-		clk_prepare_enable(clks[IMX6SL_CLK_USBPHY1_GATE]);
-		clk_prepare_enable(clks[IMX6SL_CLK_USBPHY2_GATE]);
+		imx_clk_prepare_enable(clks[IMX6SL_CLK_USBPHY1_GATE]);
+		imx_clk_prepare_enable(clks[IMX6SL_CLK_USBPHY2_GATE]);
 	}
 
-	clk_set_parent(clks[IMX6SL_CLK_GPU2D_OVG_SEL],
+	imx_clk_set_parent(clks[IMX6SL_CLK_GPU2D_OVG_SEL],
 		clks[IMX6SL_CLK_PLL2_BUS]);
-	clk_set_parent(clks[IMX6SL_CLK_GPU2D_SEL], clks[IMX6SL_CLK_PLL2_BUS]);
+	imx_clk_set_parent(clks[IMX6SL_CLK_GPU2D_SEL], clks[IMX6SL_CLK_PLL2_BUS]);
 
 	/* Initialize Video PLLs to valid frequency (650MHz). */
-	clk_set_rate(clks[IMX6SL_CLK_PLL5_VIDEO], 650000000);
+	imx_clk_set_rate(clks[IMX6SL_CLK_PLL5_VIDEO], 650000000);
 	/* set PLL5 video as lcdif pix parent clock */
-	clk_set_parent(clks[IMX6SL_CLK_LCDIF_PIX_SEL],
+	imx_clk_set_parent(clks[IMX6SL_CLK_LCDIF_PIX_SEL],
 			clks[IMX6SL_CLK_PLL5_VIDEO_DIV]);
-	clk_set_parent(clks[IMX6SL_CLK_EPDC_PIX_SEL],
+	imx_clk_set_parent(clks[IMX6SL_CLK_EPDC_PIX_SEL],
 			clks[IMX6SL_CLK_PLL5_VIDEO_DIV]);
 
-	clk_set_parent(clks[IMX6SL_CLK_EPDC_AXI_SEL], clks[IMX6SL_CLK_PLL2_PFD2]);
-	clk_set_rate(clks[IMX6SL_CLK_EPDC_AXI], 200000000);
-	clk_set_parent(clks[IMX6SL_CLK_PXP_AXI_SEL], clks[IMX6SL_CLK_PLL2_PFD2]);
-	clk_set_rate(clks[IMX6SL_CLK_PXP_AXI], 200000000);
-	clk_set_parent(clks[IMX6SL_CLK_LCDIF_AXI_SEL], clks[IMX6SL_CLK_PLL2_PFD2]);
-	clk_set_rate(clks[IMX6SL_CLK_LCDIF_AXI], 200000000);
+	imx_clk_set_parent(clks[IMX6SL_CLK_EPDC_AXI_SEL], clks[IMX6SL_CLK_PLL2_PFD2]);
+	imx_clk_set_rate(clks[IMX6SL_CLK_EPDC_AXI], 200000000);
+	imx_clk_set_parent(clks[IMX6SL_CLK_PXP_AXI_SEL], clks[IMX6SL_CLK_PLL2_PFD2]);
+	imx_clk_set_rate(clks[IMX6SL_CLK_PXP_AXI], 200000000);
+	imx_clk_set_parent(clks[IMX6SL_CLK_LCDIF_AXI_SEL], clks[IMX6SL_CLK_PLL2_PFD2]);
+	imx_clk_set_rate(clks[IMX6SL_CLK_LCDIF_AXI], 200000000);
 
 	/* Audio clocks */
-	clk_set_parent(clks[IMX6SL_CLK_SPDIF0_SEL], clks[IMX6SL_CLK_PLL3_PFD3]);
-	clk_set_rate(clks[IMX6SL_CLK_SPDIF0_PODF], 227368421);
+	imx_clk_set_parent(clks[IMX6SL_CLK_SPDIF0_SEL], clks[IMX6SL_CLK_PLL3_PFD3]);
+	imx_clk_set_rate(clks[IMX6SL_CLK_SPDIF0_PODF], 227368421);
 
 	/* set extern_audio to be sourced from PLL4/audio PLL */
-	clk_set_parent(clks[IMX6SL_CLK_EXTERN_AUDIO_SEL], clks[IMX6SL_CLK_PLL4_AUDIO_DIV]);
+	imx_clk_set_parent(clks[IMX6SL_CLK_EXTERN_AUDIO_SEL], clks[IMX6SL_CLK_PLL4_AUDIO_DIV]);
 	/* set extern_audio to 24MHz */
-	clk_set_rate(clks[IMX6SL_CLK_PLL4_AUDIO], 24000000);
-	clk_set_rate(clks[IMX6SL_CLK_EXTERN_AUDIO], 24000000);
+	imx_clk_set_rate(clks[IMX6SL_CLK_PLL4_AUDIO], 24000000);
+	imx_clk_set_rate(clks[IMX6SL_CLK_EXTERN_AUDIO], 24000000);
 
 	/* set SSI2 parent to PLL4 */
-	clk_set_parent(clks[IMX6SL_CLK_SSI2_SEL], clks[IMX6SL_CLK_PLL4_AUDIO_DIV]);
-	clk_set_rate(clks[IMX6SL_CLK_SSI2], 24000000);
+	imx_clk_set_parent(clks[IMX6SL_CLK_SSI2_SEL], clks[IMX6SL_CLK_PLL4_AUDIO_DIV]);
+	imx_clk_set_rate(clks[IMX6SL_CLK_SSI2], 24000000);
 
 	/* set perclk to source from OSC 24MHz */
-	clk_set_parent(clks[IMX6SL_CLK_PERCLK_SEL], clks[IMX6SL_CLK_OSC]);
+	imx_clk_set_parent(clks[IMX6SL_CLK_PERCLK_SEL], clks[IMX6SL_CLK_OSC]);
 
 	/* Set initial power mode */
 	imx6_set_lpm(WAIT_CLOCKED);
@@ -483,7 +472,7 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
 
 	/* Set the UART parent if needed. */
 	if (uart_from_osc)
-		ret = clk_set_parent(clks[IMX6SL_CLK_UART_SEL], clks[IMX6SL_CLK_UART_OSC_4M]);
+		imx_clk_set_parent(clks[IMX6SL_CLK_UART_SEL], clks[IMX6SL_CLK_UART_OSC_4M]);
 
 	np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-gpt");
 	base = of_iomap(np, 0);
diff --git a/arch/arm/mach-imx/clk-imx6sx.c b/arch/arm/mach-imx/clk-imx6sx.c
index b3ddb75be7d8..44d504b617de 100644
--- a/arch/arm/mach-imx/clk-imx6sx.c
+++ b/arch/arm/mach-imx/clk-imx6sx.c
@@ -482,65 +482,63 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
 	clk_register_clkdev(clks[IMX6SX_CLK_ARM], NULL, "cpu0");
 
 	for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
-		clk_prepare_enable(clks[clks_init_on[i]]);
+		imx_clk_prepare_enable(clks[clks_init_on[i]]);
 
 	if (IS_ENABLED(CONFIG_USB_MXS_PHY)) {
-		clk_prepare_enable(clks[IMX6SX_CLK_USBPHY1_GATE]);
-		clk_prepare_enable(clks[IMX6SX_CLK_USBPHY2_GATE]);
+		imx_clk_prepare_enable(clks[IMX6SX_CLK_USBPHY1_GATE]);
+		imx_clk_prepare_enable(clks[IMX6SX_CLK_USBPHY2_GATE]);
 	}
 
 	/* Set the default 132MHz for EIM module */
-	clk_set_parent(clks[IMX6SX_CLK_EIM_SLOW_SEL], clks[IMX6SX_CLK_PLL2_PFD2]);
-	clk_set_rate(clks[IMX6SX_CLK_EIM_SLOW], 132000000);
+	imx_clk_set_parent(clks[IMX6SX_CLK_EIM_SLOW_SEL], clks[IMX6SX_CLK_PLL2_PFD2]);
+	imx_clk_set_rate(clks[IMX6SX_CLK_EIM_SLOW], 132000000);
 
 	/* set parent clock for LCDIF1 pixel clock */
-	clk_set_parent(clks[IMX6SX_CLK_LCDIF1_PRE_SEL], clks[IMX6SX_CLK_PLL5_VIDEO_DIV]);
-	clk_set_parent(clks[IMX6SX_CLK_LCDIF1_SEL], clks[IMX6SX_CLK_LCDIF1_PODF]);
+	imx_clk_set_parent(clks[IMX6SX_CLK_LCDIF1_PRE_SEL], clks[IMX6SX_CLK_PLL5_VIDEO_DIV]);
+	imx_clk_set_parent(clks[IMX6SX_CLK_LCDIF1_SEL], clks[IMX6SX_CLK_LCDIF1_PODF]);
 
 	/* Set the parent clks of PCIe lvds1 and pcie_axi to be pcie ref, axi */
-	if (clk_set_parent(clks[IMX6SX_CLK_LVDS1_SEL], clks[IMX6SX_CLK_PCIE_REF_125M]))
-		pr_err("Failed to set pcie bus parent clk.\n");
-	if (clk_set_parent(clks[IMX6SX_CLK_PCIE_AXI_SEL], clks[IMX6SX_CLK_AXI]))
-		pr_err("Failed to set pcie parent clk.\n");
+	imx_clk_set_parent(clks[IMX6SX_CLK_LVDS1_SEL], clks[IMX6SX_CLK_PCIE_REF_125M]);
+	imx_clk_set_parent(clks[IMX6SX_CLK_PCIE_AXI_SEL], clks[IMX6SX_CLK_AXI]);
 
 	/*
 	 * Init enet system AHB clock, set to 200Mhz
 	 * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB
 	 */
-	clk_set_parent(clks[IMX6SX_CLK_ENET_PRE_SEL], clks[IMX6SX_CLK_PLL2_PFD2]);
-	clk_set_parent(clks[IMX6SX_CLK_ENET_SEL], clks[IMX6SX_CLK_ENET_PODF]);
-	clk_set_rate(clks[IMX6SX_CLK_ENET_PODF], 200000000);
-	clk_set_rate(clks[IMX6SX_CLK_ENET_REF], 125000000);
-	clk_set_rate(clks[IMX6SX_CLK_ENET2_REF], 125000000);
+	imx_clk_set_parent(clks[IMX6SX_CLK_ENET_PRE_SEL], clks[IMX6SX_CLK_PLL2_PFD2]);
+	imx_clk_set_parent(clks[IMX6SX_CLK_ENET_SEL], clks[IMX6SX_CLK_ENET_PODF]);
+	imx_clk_set_rate(clks[IMX6SX_CLK_ENET_PODF], 200000000);
+	imx_clk_set_rate(clks[IMX6SX_CLK_ENET_REF], 125000000);
+	imx_clk_set_rate(clks[IMX6SX_CLK_ENET2_REF], 125000000);
 
 	/* Audio clocks */
-	clk_set_rate(clks[IMX6SX_CLK_PLL4_AUDIO_DIV], 393216000);
+	imx_clk_set_rate(clks[IMX6SX_CLK_PLL4_AUDIO_DIV], 393216000);
 
-	clk_set_parent(clks[IMX6SX_CLK_SPDIF_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]);
-	clk_set_rate(clks[IMX6SX_CLK_SPDIF_PODF], 98304000);
+	imx_clk_set_parent(clks[IMX6SX_CLK_SPDIF_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]);
+	imx_clk_set_rate(clks[IMX6SX_CLK_SPDIF_PODF], 98304000);
 
-	clk_set_parent(clks[IMX6SX_CLK_AUDIO_SEL], clks[IMX6SX_CLK_PLL3_USB_OTG]);
-	clk_set_rate(clks[IMX6SX_CLK_AUDIO_PODF], 24000000);
+	imx_clk_set_parent(clks[IMX6SX_CLK_AUDIO_SEL], clks[IMX6SX_CLK_PLL3_USB_OTG]);
+	imx_clk_set_rate(clks[IMX6SX_CLK_AUDIO_PODF], 24000000);
 
-	clk_set_parent(clks[IMX6SX_CLK_SSI1_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]);
-	clk_set_parent(clks[IMX6SX_CLK_SSI2_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]);
-	clk_set_parent(clks[IMX6SX_CLK_SSI3_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]);
-	clk_set_rate(clks[IMX6SX_CLK_SSI1_PODF], 24576000);
-	clk_set_rate(clks[IMX6SX_CLK_SSI2_PODF], 24576000);
-	clk_set_rate(clks[IMX6SX_CLK_SSI3_PODF], 24576000);
+	imx_clk_set_parent(clks[IMX6SX_CLK_SSI1_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]);
+	imx_clk_set_parent(clks[IMX6SX_CLK_SSI2_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]);
+	imx_clk_set_parent(clks[IMX6SX_CLK_SSI3_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]);
+	imx_clk_set_rate(clks[IMX6SX_CLK_SSI1_PODF], 24576000);
+	imx_clk_set_rate(clks[IMX6SX_CLK_SSI2_PODF], 24576000);
+	imx_clk_set_rate(clks[IMX6SX_CLK_SSI3_PODF], 24576000);
 
-	clk_set_parent(clks[IMX6SX_CLK_ESAI_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]);
-	clk_set_rate(clks[IMX6SX_CLK_ESAI_PODF], 24576000);
+	imx_clk_set_parent(clks[IMX6SX_CLK_ESAI_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]);
+	imx_clk_set_rate(clks[IMX6SX_CLK_ESAI_PODF], 24576000);
 
 	/* Set parent clock for vadc */
-	clk_set_parent(clks[IMX6SX_CLK_VID_SEL], clks[IMX6SX_CLK_PLL3_USB_OTG]);
+	imx_clk_set_parent(clks[IMX6SX_CLK_VID_SEL], clks[IMX6SX_CLK_PLL3_USB_OTG]);
 
 	/* default parent of can_sel clock is invalid, manually set it here */
-	clk_set_parent(clks[IMX6SX_CLK_CAN_SEL], clks[IMX6SX_CLK_PLL3_60M]);
+	imx_clk_set_parent(clks[IMX6SX_CLK_CAN_SEL], clks[IMX6SX_CLK_PLL3_60M]);
 
 	/* Update gpu clock from default 528M to 720M */
-	clk_set_parent(clks[IMX6SX_CLK_GPU_CORE_SEL], clks[IMX6SX_CLK_PLL3_PFD0]);
-	clk_set_parent(clks[IMX6SX_CLK_GPU_AXI_SEL], clks[IMX6SX_CLK_PLL3_PFD0]);
+	imx_clk_set_parent(clks[IMX6SX_CLK_GPU_CORE_SEL], clks[IMX6SX_CLK_PLL3_PFD0]);
+	imx_clk_set_parent(clks[IMX6SX_CLK_GPU_AXI_SEL], clks[IMX6SX_CLK_PLL3_PFD0]);
 
 
 	/* Set initial power mode */
diff --git a/arch/arm/mach-imx/clk.h b/arch/arm/mach-imx/clk.h
index 0f9076909517..bac0e2fc5d80 100644
--- a/arch/arm/mach-imx/clk.h
+++ b/arch/arm/mach-imx/clk.h
@@ -51,6 +51,33 @@ static inline struct clk *imx_clk_gate2_shared(const char *name,
 			shift, 0, &imx_ccm_lock, share_count);
 }
 
+static inline void imx_clk_prepare_enable(struct clk *clk)
+{
+	int ret = clk_prepare_enable(clk);
+
+	if (ret)
+		pr_err("failed to prepare and enable clk %s: %d\n",
+			__clk_get_name(clk), ret);
+}
+
+static inline void imx_clk_set_parent(struct clk *clk, struct clk *parent)
+{
+	int ret = clk_set_parent(clk, parent);
+
+	if (ret)
+		pr_err("failed to set parent of clk %s to %s: %d\n",
+			__clk_get_name(clk), __clk_get_name(parent), ret);
+}
+
+static inline void imx_clk_set_rate(struct clk *clk, unsigned long rate)
+{
+	int ret = clk_set_rate(clk, rate);
+
+	if (ret)
+		pr_err("failed to set rate of clk %s to %ld: %d\n",
+			__clk_get_name(clk), rate, ret);
+}
+
 struct clk *imx_clk_pfd(const char *name, const char *parent_name,
 		void __iomem *reg, u8 idx);