Merge remote-tracking branch 'remotes/fsl-linux-sdk/imx_3.10.31_1.1.0_beta' into imx_3.10.y_android

8 files changed, 218 insertions, 251 deletions

diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
index 511a1544a60d..5a4ac38bfa6d 100644
--- a/arch/arm/boot/dts/imx6dl.dtsi
+++ b/arch/arm/boot/dts/imx6dl.dtsi
@@ -144,6 +144,11 @@
 				compatible = "fsl,imx6dl-iomuxc";
 			};
 
+			dcic2: dcic@020e8000 {
+				clocks = <&clks 232>, <&clks 231>; /* DCIC2 depend on DCIC1 clock in imx6dl*/
+				clock-names = "dcic", "disp-axi";
+			};
+
 			pxp: pxp@020f0000 {
 				compatible = "fsl,imx6dl-pxp-dma";
 				reg = <0x020f0000 0x4000>;
diff --git a/arch/arm/boot/dts/imx6sx-sdb.dts b/arch/arm/boot/dts/imx6sx-sdb.dts
index 01d9ddbcb8d8..4cb3302eb321 100644
--- a/arch/arm/boot/dts/imx6sx-sdb.dts
+++ b/arch/arm/boot/dts/imx6sx-sdb.dts
@@ -444,6 +444,7 @@
 				MX6SX_PAD_QSPI1B_DATA1__GPIO4_IO_25 0x17059
 				MX6SX_PAD_QSPI1B_DATA2__GPIO4_IO_26 0x17059
 				MX6SX_PAD_QSPI1B_DATA3__GPIO4_IO_27 0x17059
+				MX6SX_PAD_CSI_DATA03__GPIO1_IO_17 0x17059
 				MX6SX_PAD_CSI_DATA04__GPIO1_IO_18 0x17059
 				MX6SX_PAD_CSI_DATA05__GPIO1_IO_19 0x17059
 				MX6SX_PAD_SD1_DATA3__GPIO6_IO_5 0xb000
diff --git a/arch/arm/mach-imx/busfreq-imx6.c b/arch/arm/mach-imx/busfreq-imx6.c
index 12e8f69ee935..8dce0e153121 100644
--- a/arch/arm/mach-imx/busfreq-imx6.c
+++ b/arch/arm/mach-imx/busfreq-imx6.c
@@ -46,6 +46,7 @@
 #include <linux/regulator/consumer.h>
 #include <linux/sched.h>
 #include <linux/suspend.h>
+#include "clk.h"
 #include "hardware.h"
 #include "common.h"
 
@@ -119,11 +120,11 @@ static struct delayed_work bus_freq_daemon;
 static void enter_lpm_imx6sx(void)
 {
 	/* set periph_clk2 to source from OSC for periph */
-	clk_set_parent(periph_clk2_sel, osc_clk);
-	clk_set_parent(periph_clk, periph_clk2);
+	imx_clk_set_parent(periph_clk2_sel, osc_clk);
+	imx_clk_set_parent(periph_clk, periph_clk2);
 	/* set ahb/ocram to 24MHz */
-	clk_set_rate(ahb_clk, LPAPM_CLK);
-	clk_set_rate(ocram_clk, LPAPM_CLK);
+	imx_clk_set_rate(ahb_clk, LPAPM_CLK);
+	imx_clk_set_rate(ocram_clk, LPAPM_CLK);
 
 	if (audio_bus_count) {
 		/* Need to ensure that PLL2_PFD_400M is kept ON. */
@@ -132,9 +133,9 @@ static void enter_lpm_imx6sx(void)
 			update_ddr_freq_imx6sx(DDR3_AUDIO_CLK);
 		else if (ddr_type == MMDC_MDMISC_DDR_TYPE_LPDDR2)
 			update_lpddr2_freq(LPDDR2_AUDIO_CLK);
-		clk_set_parent(periph2_clk2_sel, pll3);
-		clk_set_parent(periph2_pre_clk, pll2_400);
-		clk_set_parent(periph2_clk, periph2_pre_clk);
+		imx_clk_set_parent(periph2_clk2_sel, pll3);
+		imx_clk_set_parent(periph2_pre_clk, pll2_400);
+		imx_clk_set_parent(periph2_clk, periph2_pre_clk);
 		/*
 		 * As periph2_clk's parent is not changed from
 		 * high mode to audio mode, so clk framework
@@ -146,9 +147,9 @@ static void enter_lpm_imx6sx(void)
 		 */
 		if (high_bus_freq_mode) {
 			if (ddr_type == MMDC_MDMISC_DDR_TYPE_DDR3)
-				clk_set_rate(mmdc_clk, DDR3_AUDIO_CLK);
+				imx_clk_set_rate(mmdc_clk, DDR3_AUDIO_CLK);
 			else if (ddr_type == MMDC_MDMISC_DDR_TYPE_LPDDR2)
-				clk_set_rate(mmdc_clk, LPDDR2_AUDIO_CLK);
+				imx_clk_set_rate(mmdc_clk, LPDDR2_AUDIO_CLK);
 		}
 		audio_bus_freq_mode = 1;
 		low_bus_freq_mode = 0;
@@ -157,8 +158,8 @@ static void enter_lpm_imx6sx(void)
 			update_ddr_freq_imx6sx(LPAPM_CLK);
 		else if (ddr_type == MMDC_MDMISC_DDR_TYPE_LPDDR2)
 			update_lpddr2_freq(LPAPM_CLK);
-		clk_set_parent(periph2_clk2_sel, osc_clk);
-		clk_set_parent(periph2_clk, periph2_clk2);
+		imx_clk_set_parent(periph2_clk2_sel, osc_clk);
+		imx_clk_set_parent(periph2_clk, periph2_clk2);
 
 		if (audio_bus_freq_mode)
 			clk_disable_unprepare(pll2_400);
@@ -175,22 +176,22 @@ static void exit_lpm_imx6sx(void)
 	 * lower ahb/ocram's freq first to avoid too high
 	 * freq during parent switch from OSC to pll3.
 	 */
-	clk_set_rate(ahb_clk, LPAPM_CLK / 3);
-	clk_set_rate(ocram_clk, LPAPM_CLK / 2);
+	imx_clk_set_rate(ahb_clk, LPAPM_CLK / 3);
+	imx_clk_set_rate(ocram_clk, LPAPM_CLK / 2);
 	/* set periph_clk2 to pll3 */
-	clk_set_parent(periph_clk2_sel, pll3);
+	imx_clk_set_parent(periph_clk2_sel, pll3);
 	/* set periph clk to from pll2_400 */
-	clk_set_parent(periph_pre_clk, pll2_400);
-	clk_set_parent(periph_clk, periph_pre_clk);
+	imx_clk_set_parent(periph_pre_clk, pll2_400);
+	imx_clk_set_parent(periph_clk, periph_pre_clk);
 
 	if (ddr_type == MMDC_MDMISC_DDR_TYPE_DDR3)
 		update_ddr_freq_imx6sx(ddr_normal_rate);
 	else if (ddr_type == MMDC_MDMISC_DDR_TYPE_LPDDR2)
 		update_lpddr2_freq(ddr_normal_rate);
 	/* correct parent info after ddr freq change in asm code */
-	clk_set_parent(periph2_clk2_sel, pll3);
-	clk_set_parent(periph2_pre_clk, pll2_400);
-	clk_set_parent(periph2_clk, periph2_pre_clk);
+	imx_clk_set_parent(periph2_clk2_sel, pll3);
+	imx_clk_set_parent(periph2_pre_clk, pll2_400);
+	imx_clk_set_parent(periph2_clk, periph2_pre_clk);
 	/*
 	 * As periph2_clk's parent is not changed from
 	 * audio mode to high mode, so clk framework
@@ -201,7 +202,7 @@ static void exit_lpm_imx6sx(void)
 	 * change to hardware.
 	 */
 	if (audio_bus_freq_mode)
-		clk_set_rate(mmdc_clk, ddr_normal_rate);
+		imx_clk_set_rate(mmdc_clk, ddr_normal_rate);
 
 	clk_disable_unprepare(pll2_400);
 	if (audio_bus_freq_mode)
@@ -213,36 +214,36 @@ static void enter_lpm_imx6sl(void)
 	if (high_bus_freq_mode) {
 		pll2_org_rate = clk_get_rate(pll2);
 		/* Set periph_clk to be sourced from OSC_CLK */
-		clk_set_parent(periph_clk2_sel, osc_clk);
-		clk_set_parent(periph_clk, periph_clk2);
+		imx_clk_set_parent(periph_clk2_sel, osc_clk);
+		imx_clk_set_parent(periph_clk, periph_clk2);
 		/* Ensure AHB/AXI clks are at 24MHz. */
-		clk_set_rate(ahb_clk, LPAPM_CLK);
-		clk_set_rate(ocram_clk, LPAPM_CLK);
+		imx_clk_set_rate(ahb_clk, LPAPM_CLK);
+		imx_clk_set_rate(ocram_clk, LPAPM_CLK);
 	}
 	if (audio_bus_count) {
 		/* Set AHB to 8MHz to lower pwer.*/
-		clk_set_rate(ahb_clk, LPAPM_CLK / 3);
+		imx_clk_set_rate(ahb_clk, LPAPM_CLK / 3);
 
 		/* Set up DDR to 100MHz. */
 		update_lpddr2_freq(LPDDR2_AUDIO_CLK);
 
 		/* Fix the clock tree in kernel */
-		clk_set_rate(pll2, pll2_org_rate);
-		clk_set_parent(periph2_pre_clk, pll2_200);
-		clk_set_parent(periph2_clk, periph2_pre_clk);
+		imx_clk_set_rate(pll2, pll2_org_rate);
+		imx_clk_set_parent(periph2_pre_clk, pll2_200);
+		imx_clk_set_parent(periph2_clk, periph2_pre_clk);
 
 		if (low_bus_freq_mode || ultra_low_bus_freq_mode) {
 			/*
 			 * Swtich ARM to run off PLL2_PFD2_400MHz
 			 * since DDR is anyway at 100MHz.
 			 */
-			clk_set_parent(step_clk, pll2_400);
-			clk_set_parent(pll1_sw_clk, step_clk);
+			imx_clk_set_parent(step_clk, pll2_400);
+			imx_clk_set_parent(pll1_sw_clk, step_clk);
 			/*
 			 * Ensure that the clock will be
 			 * at original speed.
 			 */
-			clk_set_rate(cpu_clk, org_arm_rate);
+			imx_clk_set_rate(cpu_clk, org_arm_rate);
 		}
 		low_bus_freq_mode = 0;
 		ultra_low_bus_freq_mode = 0;
@@ -272,7 +273,7 @@ static void enter_lpm_imx6sl(void)
 				 * the CPU freq does not change, so attempt to
 				 * get a freq as close to 396MHz as possible.
 				 */
-				clk_set_rate(pll1_sys,
+				imx_clk_set_rate(pll1_sys,
 					clk_round_rate(pll1_sys, (org_arm_rate * 2)));
 				pll1_rate = clk_get_rate(pll1_sys);
 				arm_div = pll1_rate / org_arm_rate;
@@ -282,9 +283,9 @@ static void enter_lpm_imx6sl(void)
 				 * Ensure ARM CLK is lower before
 				 * changing the parent.
 				 */
-				clk_set_rate(cpu_clk, org_arm_rate / arm_div);
+				imx_clk_set_rate(cpu_clk, org_arm_rate / arm_div);
 				/* Now set the ARM clk parent to PLL1_SYS. */
-				clk_set_parent(pll1_sw_clk, pll1_sys);
+				imx_clk_set_parent(pll1_sw_clk, pll1_sys);
 
 				/*
 				 * Set STEP_CLK back to OSC to save power and
@@ -294,7 +295,7 @@ static void enter_lpm_imx6sl(void)
 				 * to change the step_clk parent to pll2_pfd2_400M
 				 * is requested sometime later, the change is ignored.
 				 */
-				clk_set_parent(step_clk, osc_clk);
+				imx_clk_set_parent(step_clk, osc_clk);
 				/* Now set DDR to 24MHz. */
 				update_lpddr2_freq(LPAPM_CLK);
 
@@ -303,9 +304,9 @@ static void enter_lpm_imx6sl(void)
 				 * Make sure PLL2 rate is updated as it gets
 				 * bypassed in the DDR freq change code.
 				 */
-				clk_set_rate(pll2, LPAPM_CLK);
-				clk_set_parent(periph2_clk2_sel, pll2);
-				clk_set_parent(periph2_clk, periph2_clk2_sel);
+				imx_clk_set_rate(pll2, LPAPM_CLK);
+				imx_clk_set_parent(periph2_clk2_sel, pll2);
+				imx_clk_set_parent(periph2_clk, periph2_clk2);
 
 			}
 			if (low_bus_count == 0) {
@@ -330,32 +331,31 @@ static void exit_lpm_imx6sl(void)
 	 * Make sure PLL2 rate is updated as it gets
 	 * un-bypassed in the DDR freq change code.
 	 */
-	clk_set_rate(pll2, pll2_org_rate);
-	clk_set_parent(periph2_pre_clk, pll2_400);
-	clk_set_parent(periph2_clk, periph2_pre_clk);
+	imx_clk_set_rate(pll2, pll2_org_rate);
+	imx_clk_set_parent(periph2_pre_clk, pll2_400);
+	imx_clk_set_parent(periph2_clk, periph2_pre_clk);
 
 	/* Ensure that periph_clk is sourced from PLL2_400. */
-	clk_set_parent(periph_pre_clk, pll2_400);
+	imx_clk_set_parent(periph_pre_clk, pll2_400);
 	/*
 	 * Before switching the perhiph_clk, ensure that the
 	 * AHB/AXI will not be too fast.
 	 */
-	clk_set_rate(ahb_clk, LPAPM_CLK / 3);
-	clk_set_rate(ocram_clk, LPAPM_CLK / 2);
-	clk_set_parent(periph_clk, periph_pre_clk);
+	imx_clk_set_rate(ahb_clk, LPAPM_CLK / 3);
+	imx_clk_set_rate(ocram_clk, LPAPM_CLK / 2);
+	imx_clk_set_parent(periph_clk, periph_pre_clk);
 
 	if (low_bus_freq_mode || ultra_low_bus_freq_mode) {
 		/* Move ARM from PLL1_SW_CLK to PLL2_400. */
-		clk_set_parent(step_clk, pll2_400);
-		clk_set_parent(pll1_sw_clk, step_clk);
-		clk_set_rate(cpu_clk, org_arm_rate);
+		imx_clk_set_parent(step_clk, pll2_400);
+		imx_clk_set_parent(pll1_sw_clk, step_clk);
+		imx_clk_set_rate(cpu_clk, org_arm_rate);
 		ultra_low_bus_freq_mode = 0;
 	}
 }
 
-int reduce_bus_freq(void)
+static void reduce_bus_freq(void)
 {
-	int ret = 0;
 	clk_prepare_enable(pll3);
 	if (cpu_is_imx6sl())
 		enter_lpm_imx6sl();
@@ -364,44 +364,24 @@ int reduce_bus_freq(void)
 	else {
 		if (cpu_is_imx6dl())
 			/* Set axi to periph_clk */
-			clk_set_parent(axi_sel_clk, periph_clk);
+			imx_clk_set_parent(axi_sel_clk, periph_clk);
 
 		if (audio_bus_count) {
 			/* Need to ensure that PLL2_PFD_400M is kept ON. */
 			clk_prepare_enable(pll2_400);
 			update_ddr_freq_imx6q(DDR3_AUDIO_CLK);
 			/* Make sure periph clk's parent also got updated */
-			ret = clk_set_parent(periph_clk2_sel, pll3);
-			if (ret)
-				dev_warn(busfreq_dev,
-					"%s: %d: clk set parent fail!\n",
-					__func__, __LINE__);
-			ret = clk_set_parent(periph_pre_clk, pll2_200);
-			if (ret)
-				dev_warn(busfreq_dev,
-					"%s: %d: clk set parent fail!\n",
-					__func__, __LINE__);
-			ret = clk_set_parent(periph_clk, periph_pre_clk);
-			if (ret)
-				dev_warn(busfreq_dev,
-					"%s: %d: clk set parent fail!\n",
-					__func__, __LINE__);
+			imx_clk_set_parent(periph_clk2_sel, pll3);
+			imx_clk_set_parent(periph_pre_clk, pll2_200);
+			imx_clk_set_parent(periph_clk, periph_pre_clk);
 			audio_bus_freq_mode = 1;
 			low_bus_freq_mode = 0;
 		} else {
 			update_ddr_freq_imx6q(LPAPM_CLK);
 			/* Make sure periph clk's parent also got updated */
-			ret = clk_set_parent(periph_clk2_sel, osc_clk);
-			if (ret)
-				dev_warn(busfreq_dev,
-					"%s: %d: clk set parent fail!\n",
-					__func__, __LINE__);
+			imx_clk_set_parent(periph_clk2_sel, osc_clk);
 			/* Set periph_clk parent to OSC via periph_clk2_sel */
-			ret = clk_set_parent(periph_clk, periph_clk2);
-			if (ret)
-				dev_warn(busfreq_dev,
-					"%s: %d: clk set parent fail!\n",
-					__func__, __LINE__);
+			imx_clk_set_parent(periph_clk, periph_clk2);
 			if (audio_bus_freq_mode)
 				clk_disable_unprepare(pll2_400);
 			low_bus_freq_mode = 1;
@@ -421,8 +401,6 @@ int reduce_bus_freq(void)
 		dev_dbg(busfreq_dev, "Bus freq set to low mode. Count:\
 			high %d, med %d, audio %d\n",
 			high_bus_count, med_bus_count, audio_bus_count);
-
-	return ret;
 }
 
 static void reduce_bus_freq_handler(struct work_struct *work)
@@ -469,9 +447,8 @@ int set_low_bus_freq(void)
  * Set the DDR to either 528MHz or 400MHz for iMX6qd
  * or 400MHz for iMX6dl.
  */
-int set_high_bus_freq(int high_bus_freq)
+static int set_high_bus_freq(int high_bus_freq)
 {
-	int ret = 0;
 	struct clk *periph_clk_parent;
 
 	if (bus_freq_scaling_initialized && bus_freq_scaling_is_active)
@@ -505,45 +482,21 @@ int set_high_bus_freq(int high_bus_freq)
 			clk_prepare_enable(pll2_400);
 			update_ddr_freq_imx6q(ddr_normal_rate);
 			/* Make sure periph clk's parent also got updated */
-			ret = clk_set_parent(periph_clk2_sel, pll3);
-			if (ret)
-				dev_warn(busfreq_dev,
-					"%s: %d: clk set parent fail!\n",
-					__func__, __LINE__);
-			ret = clk_set_parent(periph_pre_clk, periph_clk_parent);
-			if (ret)
-				dev_warn(busfreq_dev,
-					"%s: %d: clk set parent fail!\n",
-					__func__, __LINE__);
-			ret = clk_set_parent(periph_clk, periph_pre_clk);
-			if (ret)
-				dev_warn(busfreq_dev,
-					"%s: %d: clk set parent fail!\n",
-					__func__, __LINE__);
+			imx_clk_set_parent(periph_clk2_sel, pll3);
+			imx_clk_set_parent(periph_pre_clk, periph_clk_parent);
+			imx_clk_set_parent(periph_clk, periph_pre_clk);
 			if (cpu_is_imx6dl()) {
 				/* Set axi to pll3_pfd1_540m */
-				clk_set_parent(axi_alt_sel_clk, pll3_pfd1_540m);
-				clk_set_parent(axi_sel_clk, axi_alt_sel_clk);
+				imx_clk_set_parent(axi_alt_sel_clk, pll3_pfd1_540m);
+				imx_clk_set_parent(axi_sel_clk, axi_alt_sel_clk);
 			}
 			clk_disable_unprepare(pll2_400);
 		} else {
 			update_ddr_freq_imx6q(ddr_med_rate);
 			/* Make sure periph clk's parent also got updated */
-			ret = clk_set_parent(periph_clk2_sel, pll3);
-			if (ret)
-				dev_warn(busfreq_dev,
-					"%s: %d: clk set parent fail!\n",
-					__func__, __LINE__);
-			ret = clk_set_parent(periph_pre_clk, pll2_400);
-			if (ret)
-				dev_warn(busfreq_dev,
-					"%s: %d: clk set parent fail!\n",
-					__func__, __LINE__);
-			ret = clk_set_parent(periph_clk, periph_pre_clk);
-			if (ret)
-				dev_warn(busfreq_dev,
-					"%s: %d: clk set parent fail!\n",
-					__func__, __LINE__);
+			imx_clk_set_parent(periph_clk2_sel, pll3);
+			imx_clk_set_parent(periph_pre_clk, pll2_400);
+			imx_clk_set_parent(periph_clk, periph_pre_clk);
 		}
 		if (audio_bus_freq_mode)
 			clk_disable_unprepare(pll2_400);
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 4e7259669f4e..8373e471d77f 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -293,7 +293,6 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
 	struct device_node *np;
 	void __iomem *base;
 	int i, irq;
-	int ret;
 	u32 reg;
 
 	clk[dummy] = imx_clk_fixed("dummy", 0);
@@ -379,10 +378,10 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
 	clk[gpt_3m]    = imx_clk_fixed_factor("gpt_3m",    "osc",            1, 8);
 	clk[video_27m] = imx_clk_fixed_factor("video_27m", "pll3_pfd1_540m", 1, 20);
 
-	clk[pll4_post_div] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock);
-	clk[pll4_audio_div] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x170, 15, 1, 0, &imx_ccm_lock);
-	clk[pll5_post_div] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock);
-	clk[pll5_video_div] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock);
+	clk[pll4_post_div] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock);
+	clk[pll4_audio_div] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock);
+	clk[pll5_post_div] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock);
+	clk[pll5_video_div] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock);
 
 	np = ccm_node;
 	ccm_base = base = of_iomap(np, 0);
@@ -673,74 +672,69 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
 	 * We can not get the 100MHz from the pll2_pfd0_352m.
 	 * So choose pll2_pfd2_396m as enfc_sel's parent.
 	 */
-	clk_set_parent(clk[enfc_sel], clk[pll2_pfd2_396m]);
+	imx_clk_set_parent(clk[enfc_sel], clk[pll2_pfd2_396m]);
 
 	/* Set the parent clks of PCIe lvds1 and pcie_axi to be sata ref, axi */
-	if (clk_set_parent(clk[lvds1_sel], clk[sata_ref]))
-		pr_err("Failed to set PCIe bus parent clk.\n");
-	if (clk_set_parent(clk[pcie_axi_sel], clk[axi]))
-		pr_err("Failed to set PCIe parent clk.\n");
+	imx_clk_set_parent(clk[lvds1_sel], clk[sata_ref]);
+	imx_clk_set_parent(clk[pcie_axi_sel], clk[axi]);
 
 	/* gpu clock initilazation */
-	clk_set_parent(clk[gpu3d_shader_sel], clk[pll2_pfd1_594m]);
-	clk_set_rate(clk[gpu3d_shader], 594000000);
-	clk_set_parent(clk[gpu3d_core_sel], clk[mmdc_ch0_axi]);
-	clk_set_rate(clk[gpu3d_core], 528000000);
-	clk_set_parent(clk[gpu2d_core_sel], clk[pll3_usb_otg]);
+	imx_clk_set_parent(clk[gpu3d_shader_sel], clk[pll2_pfd1_594m]);
+	imx_clk_set_rate(clk[gpu3d_shader], 594000000);
+	imx_clk_set_parent(clk[gpu3d_core_sel], clk[mmdc_ch0_axi]);
+	imx_clk_set_rate(clk[gpu3d_core], 528000000);
+	imx_clk_set_parent(clk[gpu2d_core_sel], clk[pll3_usb_otg]);
 
 	for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
-		clk_prepare_enable(clk[clks_init_on[i]]);
+		imx_clk_prepare_enable(clk[clks_init_on[i]]);
 
 	if (IS_ENABLED(CONFIG_USB_MXS_PHY)) {
-		clk_prepare_enable(clk[usbphy1_gate]);
-		clk_prepare_enable(clk[usbphy2_gate]);
+		imx_clk_prepare_enable(clk[usbphy1_gate]);
+		imx_clk_prepare_enable(clk[usbphy2_gate]);
 	}
 
 	/* ipu clock initialization */
 	init_ldb_clks();
-	clk_set_parent(clk[ipu1_di0_pre_sel], clk[pll5_video_div]);
-	clk_set_parent(clk[ipu1_di1_pre_sel], clk[pll5_video_div]);
-	clk_set_parent(clk[ipu2_di0_pre_sel], clk[pll5_video_div]);
-	clk_set_parent(clk[ipu2_di1_pre_sel], clk[pll5_video_div]);
-	clk_set_parent(clk[ipu1_di0_sel], clk[ipu1_di0_pre]);
-	clk_set_parent(clk[ipu1_di1_sel], clk[ipu1_di1_pre]);
-	clk_set_parent(clk[ipu2_di0_sel], clk[ipu2_di0_pre]);
-	clk_set_parent(clk[ipu2_di1_sel], clk[ipu2_di1_pre]);
+	imx_clk_set_parent(clk[ipu1_di0_pre_sel], clk[pll5_video_div]);
+	imx_clk_set_parent(clk[ipu1_di1_pre_sel], clk[pll5_video_div]);
+	imx_clk_set_parent(clk[ipu2_di0_pre_sel], clk[pll5_video_div]);
+	imx_clk_set_parent(clk[ipu2_di1_pre_sel], clk[pll5_video_div]);
+	imx_clk_set_parent(clk[ipu1_di0_sel], clk[ipu1_di0_pre]);
+	imx_clk_set_parent(clk[ipu1_di1_sel], clk[ipu1_di1_pre]);
+	imx_clk_set_parent(clk[ipu2_di0_sel], clk[ipu2_di0_pre]);
+	imx_clk_set_parent(clk[ipu2_di1_sel], clk[ipu2_di1_pre]);
 	if (cpu_is_imx6dl()) {
-		clk_set_rate(clk[pll3_pfd1_540m], 540000000);
-		clk_set_parent(clk[ipu1_sel], clk[pll3_pfd1_540m]);
-		clk_set_parent(clk[axi_alt_sel], clk[pll3_pfd1_540m]);
-		clk_set_parent(clk[axi_sel], clk[axi_alt_sel]);
+		imx_clk_set_rate(clk[pll3_pfd1_540m], 540000000);
+		imx_clk_set_parent(clk[ipu1_sel], clk[pll3_pfd1_540m]);
+		imx_clk_set_parent(clk[axi_alt_sel], clk[pll3_pfd1_540m]);
+		imx_clk_set_parent(clk[axi_sel], clk[axi_alt_sel]);
 		/* set epdc/pxp axi clock to 200Mhz */
-		clk_set_parent(clk[ipu2_sel], clk[pll2_pfd2_396m]);
-		clk_set_rate(clk[ipu2], 200000000);
+		imx_clk_set_parent(clk[ipu2_sel], clk[pll2_pfd2_396m]);
+		imx_clk_set_rate(clk[ipu2], 200000000);
 	} else if (cpu_is_imx6q()) {
-		clk_set_parent(clk[ipu1_sel], clk[mmdc_ch0_axi]);
-		clk_set_parent(clk[ipu2_sel], clk[mmdc_ch0_axi]);
+		imx_clk_set_parent(clk[ipu1_sel], clk[mmdc_ch0_axi]);
+		imx_clk_set_parent(clk[ipu2_sel], clk[mmdc_ch0_axi]);
 	}
 
 	/*
 	 * Let's initially set up CLKO with OSC24M, since this configuration
 	 * is widely used by imx6q board designs to clock audio codec.
 	 */
-	ret = clk_set_parent(clk[cko2_sel], clk[osc]);
-	if (!ret)
-		ret = clk_set_parent(clk[cko], clk[cko2]);
-	if (ret)
-		pr_warn("failed to set up CLKO: %d\n", ret);
+	imx_clk_set_parent(clk[cko2_sel], clk[osc]);
+	imx_clk_set_parent(clk[cko], clk[cko2]);
 
 	/* Audio clocks */
-	clk_set_parent(clk[ssi1_sel], clk[pll4_audio_div]);
-	clk_set_parent(clk[ssi2_sel], clk[pll4_audio_div]);
-	clk_set_parent(clk[ssi3_sel], clk[pll4_audio_div]);
-	clk_set_parent(clk[esai_sel], clk[pll4_audio_div]);
-	clk_set_parent(clk[spdif_sel], clk[pll3_pfd3_454m]);
-	clk_set_rate(clk[spdif_podf], 227368421);
-	clk_set_parent(clk[spdif1_sel], clk[pll3_usb_otg]);
-	clk_set_rate(clk[spdif1_sel], 7500000);
+	imx_clk_set_parent(clk[ssi1_sel], clk[pll4_audio_div]);
+	imx_clk_set_parent(clk[ssi2_sel], clk[pll4_audio_div]);
+	imx_clk_set_parent(clk[ssi3_sel], clk[pll4_audio_div]);
+	imx_clk_set_parent(clk[esai_sel], clk[pll4_audio_div]);
+	imx_clk_set_parent(clk[spdif_sel], clk[pll3_pfd3_454m]);
+	imx_clk_set_rate(clk[spdif_podf], 227368421);
+	imx_clk_set_parent(clk[spdif1_sel], clk[pll3_usb_otg]);
+	imx_clk_set_rate(clk[spdif1_sel], 7500000);
 
 	/* Set pll4_audio to a value that can derive 5K-88.2KHz and 8K-96KHz */
-	clk_set_rate(clk[pll4_audio_div], 541900800);
+	imx_clk_set_rate(clk[pll4_audio_div], 541900800);
 
 #ifdef CONFIG_MX6_VPU_352M
 	/*
@@ -752,8 +746,8 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
 	 * all modules that sourceing clk from PLL2_PFD2 will
 	 * be impacted.
 	 */
-	clk_set_rate(clk[pll2_pfd2_396m], 352000000);
-	clk_set_parent(clk[vpu_axi_sel], clk[pll2_pfd2_396m]);
+	imx_clk_set_rate(clk[pll2_pfd2_396m], 352000000);
+	imx_clk_set_parent(clk[vpu_axi_sel], clk[pll2_pfd2_396m]);
 	pr_info("VPU 352M is enabled!\n");
 #endif
 
diff --git a/arch/arm/mach-imx/clk-imx6sl.c b/arch/arm/mach-imx/clk-imx6sl.c
index c99b51148035..13bc637e682f 100644
--- a/arch/arm/mach-imx/clk-imx6sl.c
+++ b/arch/arm/mach-imx/clk-imx6sl.c
@@ -119,9 +119,9 @@ void imx6sl_set_wait_clk(bool enter)
 			 * to run from the 24MHz OSC, as there is no way to
 			 * get 28.8MHz when ARM is sourced from PLL1.
 			 */
-			clk_set_parent(clks[IMX6SL_CLK_STEP],
+			imx_clk_set_parent(clks[IMX6SL_CLK_STEP],
 							clks[IMX6SL_CLK_OSC]);
-			clk_set_parent(clks[IMX6SL_CLK_PLL1_SW],
+			imx_clk_set_parent(clks[IMX6SL_CLK_PLL1_SW],
 							clks[IMX6SL_CLK_STEP]);
 		} else if (audio_bus_freq_mode) {
 			/*
@@ -132,26 +132,26 @@ void imx6sl_set_wait_clk(bool enter)
 			 */
 			pll1_org_rate = clk_get_rate(clks[IMX6SL_CLK_PLL1_SYS]);
 			/* Ensure PLL1 is at 24MHz. */
-			clk_set_rate(clks[IMX6SL_CLK_PLL1_SYS], OSC_RATE);
-			clk_set_parent(clks[IMX6SL_CLK_PLL1_SW], clks[IMX6SL_CLK_PLL1_SYS]);
+			imx_clk_set_rate(clks[IMX6SL_CLK_PLL1_SYS], OSC_RATE);
+			imx_clk_set_parent(clks[IMX6SL_CLK_PLL1_SW], clks[IMX6SL_CLK_PLL1_SYS]);
 		} else
 			new_parent_rate = clk_get_rate(clks[IMX6SL_CLK_PLL1_SW]);
 		wait_podf = (new_parent_rate + max_arm_wait_clk - 1) /
 						max_arm_wait_clk;
 
-		clk_set_rate(clks[IMX6SL_CLK_ARM], new_parent_rate / wait_podf);
+		imx_clk_set_rate(clks[IMX6SL_CLK_ARM], new_parent_rate / wait_podf);
 	} else {
 		if (low_bus_freq_mode)
 			/* Move ARM back to PLL1. */
-			clk_set_parent(clks[IMX6SL_CLK_PLL1_SW],
+			imx_clk_set_parent(clks[IMX6SL_CLK_PLL1_SW],
 				clks[IMX6SL_CLK_PLL1_SYS]);
 		else if (audio_bus_freq_mode) {
 			/* Move ARM back to PLL2_PFD2 via STEP_CLK. */
-			clk_set_parent(clks[IMX6SL_CLK_PLL1_SW], clks[IMX6SL_CLK_STEP]);
-			clk_set_rate(clks[IMX6SL_CLK_PLL1_SYS], pll1_org_rate);
+			imx_clk_set_parent(clks[IMX6SL_CLK_PLL1_SW], clks[IMX6SL_CLK_STEP]);
+			imx_clk_set_rate(clks[IMX6SL_CLK_PLL1_SYS], pll1_org_rate);
 		}
 		parent_rate = clk_get_rate(clks[IMX6SL_CLK_PLL1_SW]);
-		clk_set_rate(clks[IMX6SL_CLK_ARM], parent_rate / cur_arm_podf);
+		imx_clk_set_rate(clks[IMX6SL_CLK_ARM], parent_rate / cur_arm_podf);
 	}
 }
 
@@ -168,7 +168,6 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
 	struct device_node *np;
 	void __iomem *base;
 	int irq;
-	int ret;
 	int i;
 	u32 reg;
 
@@ -202,10 +201,10 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
 	clks[IMX6SL_CLK_USBPHY2_GATE] = imx_clk_gate("usbphy2_gate", "dummy",         base + 0x20, 6);
 
 	/*                                                           dev   name              parent_name      flags                reg        shift width div: flags, div_table lock */
-	clks[IMX6SL_CLK_PLL4_POST_DIV]  = clk_register_divider_table(NULL, "pll4_post_div",  "pll4_audio",    CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x70,  19, 2,   0, post_div_table, &imx_ccm_lock);
-	clks[IMX6SL_CLK_PLL4_AUDIO_DIV] =       clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x170, 15, 1,   0, &imx_ccm_lock);
-	clks[IMX6SL_CLK_PLL5_POST_DIV]  = clk_register_divider_table(NULL, "pll5_post_div",  "pll5_video",    CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0xa0,  19, 2,   0, post_div_table, &imx_ccm_lock);
-	clks[IMX6SL_CLK_PLL5_VIDEO_DIV] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x170, 30, 2,   0, video_div_table, &imx_ccm_lock);
+	clks[IMX6SL_CLK_PLL4_POST_DIV]  = clk_register_divider_table(NULL, "pll4_post_div",  "pll4_audio",    CLK_SET_RATE_PARENT, base + 0x70,  19, 2,   0, post_div_table, &imx_ccm_lock);
+	clks[IMX6SL_CLK_PLL4_AUDIO_DIV] =       clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1,   0, &imx_ccm_lock);
+	clks[IMX6SL_CLK_PLL5_POST_DIV]  = clk_register_divider_table(NULL, "pll5_post_div",  "pll5_video",    CLK_SET_RATE_PARENT, base + 0xa0,  19, 2,   0, post_div_table, &imx_ccm_lock);
+	clks[IMX6SL_CLK_PLL5_VIDEO_DIV] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2,   0, video_div_table, &imx_ccm_lock);
 	clks[IMX6SL_CLK_ENET_REF]       = clk_register_divider_table(NULL, "enet_ref",       "pll6_enet",     0,                   base + 0xe0,  0,  2,   0, clk_enet_ref_table, &imx_ccm_lock);
 
 	/*                                       name         parent_name     reg           idx */
@@ -401,77 +400,67 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
 	clk_register_clkdev(clks[IMX6SL_CLK_GPT_SERIAL], "per", "imx-gpt.0");
 
 	/* Ensure the AHB clk is at 132MHz. */
-	ret = clk_set_rate(clks[IMX6SL_CLK_AHB], 132000000);
-	if (ret)
-		pr_warn("%s: failed to set AHB clock rate %d\n", __func__, ret);
+	imx_clk_set_rate(clks[IMX6SL_CLK_AHB], 132000000);
 
 	/*
 	 * To prevent the bus clock from being disabled accidently when
 	 * clk_disable() gets called on child clock, let's increment the use
 	 * count of IPG clock by initially calling clk_prepare_enable() on it.
 	 */
-	ret = clk_prepare_enable(clks[IMX6SL_CLK_IPG]);
-	if (ret)
-		pr_warn("%s: failed to enable IPG clock %d\n", __func__, ret);
+	imx_clk_prepare_enable(clks[IMX6SL_CLK_IPG]);
 
 	/*
 	 * Make sure the ARM clk is enabled to maintain the correct usecount
 	 * and enabling/disabling of parent PLLs.
 	 */
-	ret = clk_prepare_enable(clks[IMX6SL_CLK_ARM]);
-	if (ret)
-		pr_warn("%s: failed to enable ARM core clock %d\n",
-			__func__, ret);
+	imx_clk_prepare_enable(clks[IMX6SL_CLK_ARM]);
 
 	/*
 	 * Make sure the MMDC clk is enabled to maintain the correct usecount
 	 * and enabling/disabling of parent PLLs.
 	 */
-	ret = clk_prepare_enable(clks[IMX6SL_CLK_MMDC_ROOT]);
-	if (ret)
-		pr_warn("%s: failed to enable MMDC clock %d\n",
-			__func__, ret);
+	imx_clk_prepare_enable(clks[IMX6SL_CLK_MMDC_ROOT]);
 
 	if (IS_ENABLED(CONFIG_USB_MXS_PHY)) {
-		clk_prepare_enable(clks[IMX6SL_CLK_USBPHY1_GATE]);
-		clk_prepare_enable(clks[IMX6SL_CLK_USBPHY2_GATE]);
+		imx_clk_prepare_enable(clks[IMX6SL_CLK_USBPHY1_GATE]);
+		imx_clk_prepare_enable(clks[IMX6SL_CLK_USBPHY2_GATE]);
 	}
 
-	clk_set_parent(clks[IMX6SL_CLK_GPU2D_OVG_SEL],
+	imx_clk_set_parent(clks[IMX6SL_CLK_GPU2D_OVG_SEL],
 		clks[IMX6SL_CLK_PLL2_BUS]);
-	clk_set_parent(clks[IMX6SL_CLK_GPU2D_SEL], clks[IMX6SL_CLK_PLL2_BUS]);
+	imx_clk_set_parent(clks[IMX6SL_CLK_GPU2D_SEL], clks[IMX6SL_CLK_PLL2_BUS]);
 
 	/* Initialize Video PLLs to valid frequency (650MHz). */
-	clk_set_rate(clks[IMX6SL_CLK_PLL5_VIDEO], 650000000);
+	imx_clk_set_rate(clks[IMX6SL_CLK_PLL5_VIDEO], 650000000);
 	/* set PLL5 video as lcdif pix parent clock */
-	clk_set_parent(clks[IMX6SL_CLK_LCDIF_PIX_SEL],
+	imx_clk_set_parent(clks[IMX6SL_CLK_LCDIF_PIX_SEL],
 			clks[IMX6SL_CLK_PLL5_VIDEO_DIV]);
-	clk_set_parent(clks[IMX6SL_CLK_EPDC_PIX_SEL],
+	imx_clk_set_parent(clks[IMX6SL_CLK_EPDC_PIX_SEL],
 			clks[IMX6SL_CLK_PLL5_VIDEO_DIV]);
 
-	clk_set_parent(clks[IMX6SL_CLK_EPDC_AXI_SEL], clks[IMX6SL_CLK_PLL2_PFD2]);
-	clk_set_rate(clks[IMX6SL_CLK_EPDC_AXI], 200000000);
-	clk_set_parent(clks[IMX6SL_CLK_PXP_AXI_SEL], clks[IMX6SL_CLK_PLL2_PFD2]);
-	clk_set_rate(clks[IMX6SL_CLK_PXP_AXI], 200000000);
-	clk_set_parent(clks[IMX6SL_CLK_LCDIF_AXI_SEL], clks[IMX6SL_CLK_PLL2_PFD2]);
-	clk_set_rate(clks[IMX6SL_CLK_LCDIF_AXI], 200000000);
+	imx_clk_set_parent(clks[IMX6SL_CLK_EPDC_AXI_SEL], clks[IMX6SL_CLK_PLL2_PFD2]);
+	imx_clk_set_rate(clks[IMX6SL_CLK_EPDC_AXI], 200000000);
+	imx_clk_set_parent(clks[IMX6SL_CLK_PXP_AXI_SEL], clks[IMX6SL_CLK_PLL2_PFD2]);
+	imx_clk_set_rate(clks[IMX6SL_CLK_PXP_AXI], 200000000);
+	imx_clk_set_parent(clks[IMX6SL_CLK_LCDIF_AXI_SEL], clks[IMX6SL_CLK_PLL2_PFD2]);
+	imx_clk_set_rate(clks[IMX6SL_CLK_LCDIF_AXI], 200000000);
 
 	/* Audio clocks */
-	clk_set_parent(clks[IMX6SL_CLK_SPDIF0_SEL], clks[IMX6SL_CLK_PLL3_PFD3]);
-	clk_set_rate(clks[IMX6SL_CLK_SPDIF0_PODF], 227368421);
+	imx_clk_set_parent(clks[IMX6SL_CLK_SPDIF0_SEL], clks[IMX6SL_CLK_PLL3_PFD3]);
+	imx_clk_set_rate(clks[IMX6SL_CLK_SPDIF0_PODF], 227368421);
 
 	/* set extern_audio to be sourced from PLL4/audio PLL */
-	clk_set_parent(clks[IMX6SL_CLK_EXTERN_AUDIO_SEL], clks[IMX6SL_CLK_PLL4_AUDIO_DIV]);
+	imx_clk_set_parent(clks[IMX6SL_CLK_EXTERN_AUDIO_SEL], clks[IMX6SL_CLK_PLL4_AUDIO_DIV]);
 	/* set extern_audio to 24MHz */
-	clk_set_rate(clks[IMX6SL_CLK_PLL4_AUDIO], 24000000);
-	clk_set_rate(clks[IMX6SL_CLK_EXTERN_AUDIO], 24000000);
+	imx_clk_set_rate(clks[IMX6SL_CLK_PLL4_AUDIO], 24000000);
+	imx_clk_set_rate(clks[IMX6SL_CLK_EXTERN_AUDIO], 24000000);
 
 	/* set SSI2 parent to PLL4 */
-	clk_set_parent(clks[IMX6SL_CLK_SSI2_SEL], clks[IMX6SL_CLK_PLL4_AUDIO_DIV]);
-	clk_set_rate(clks[IMX6SL_CLK_SSI2], 24000000);
+	imx_clk_set_parent(clks[IMX6SL_CLK_SSI2_SEL], clks[IMX6SL_CLK_PLL4_AUDIO_DIV]);
+	imx_clk_set_rate(clks[IMX6SL_CLK_SSI2], 24000000);
 
 	/* set perclk to source from OSC 24MHz */
-	clk_set_parent(clks[IMX6SL_CLK_PERCLK_SEL], clks[IMX6SL_CLK_OSC]);
+	imx_clk_set_parent(clks[IMX6SL_CLK_PERCLK_SEL], clks[IMX6SL_CLK_OSC]);
 
 	/* Set initial power mode */
 	imx6_set_lpm(WAIT_CLOCKED);
@@ -483,7 +472,7 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
 
 	/* Set the UART parent if needed. */
 	if (uart_from_osc)
-		ret = clk_set_parent(clks[IMX6SL_CLK_UART_SEL], clks[IMX6SL_CLK_UART_OSC_4M]);
+		imx_clk_set_parent(clks[IMX6SL_CLK_UART_SEL], clks[IMX6SL_CLK_UART_OSC_4M]);
 
 	np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-gpt");
 	base = of_iomap(np, 0);
diff --git a/arch/arm/mach-imx/clk-imx6sx.c b/arch/arm/mach-imx/clk-imx6sx.c
index b3ddb75be7d8..148001e4c35e 100644
--- a/arch/arm/mach-imx/clk-imx6sx.c
+++ b/arch/arm/mach-imx/clk-imx6sx.c
@@ -221,13 +221,13 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
 	clks[IMX6SX_CLK_GPT_3M]    = imx_clk_fixed_factor("gpt_3m",    "osc",            1,   8);
 
 	clks[IMX6SX_CLK_PLL4_POST_DIV]  = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio",
-				CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock);
+				CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock);
 	clks[IMX6SX_CLK_PLL4_AUDIO_DIV] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div",
-				CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x170, 15, 1, 0, &imx_ccm_lock);
+				CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock);
 	clks[IMX6SX_CLK_PLL5_POST_DIV]  = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video",
-				CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock);
+				CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock);
 	clks[IMX6SX_CLK_PLL5_VIDEO_DIV] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div",
-				CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock);
+				CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock);
 
 	/*                                                name                reg           shift   width   parent_names       num_parents */
 	clks[IMX6SX_CLK_LVDS1_SEL]          = imx_clk_mux("lvds1_sel",        base + 0x160, 0,      5,      lvds_sels,         ARRAY_SIZE(lvds_sels));
@@ -482,65 +482,63 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
 	clk_register_clkdev(clks[IMX6SX_CLK_ARM], NULL, "cpu0");
 
 	for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
-		clk_prepare_enable(clks[clks_init_on[i]]);
+		imx_clk_prepare_enable(clks[clks_init_on[i]]);
 
 	if (IS_ENABLED(CONFIG_USB_MXS_PHY)) {
-		clk_prepare_enable(clks[IMX6SX_CLK_USBPHY1_GATE]);
-		clk_prepare_enable(clks[IMX6SX_CLK_USBPHY2_GATE]);
+		imx_clk_prepare_enable(clks[IMX6SX_CLK_USBPHY1_GATE]);
+		imx_clk_prepare_enable(clks[IMX6SX_CLK_USBPHY2_GATE]);
 	}
 
 	/* Set the default 132MHz for EIM module */
-	clk_set_parent(clks[IMX6SX_CLK_EIM_SLOW_SEL], clks[IMX6SX_CLK_PLL2_PFD2]);
-	clk_set_rate(clks[IMX6SX_CLK_EIM_SLOW], 132000000);
+	imx_clk_set_parent(clks[IMX6SX_CLK_EIM_SLOW_SEL], clks[IMX6SX_CLK_PLL2_PFD2]);
+	imx_clk_set_rate(clks[IMX6SX_CLK_EIM_SLOW], 132000000);
 
 	/* set parent clock for LCDIF1 pixel clock */
-	clk_set_parent(clks[IMX6SX_CLK_LCDIF1_PRE_SEL], clks[IMX6SX_CLK_PLL5_VIDEO_DIV]);
-	clk_set_parent(clks[IMX6SX_CLK_LCDIF1_SEL], clks[IMX6SX_CLK_LCDIF1_PODF]);
+	imx_clk_set_parent(clks[IMX6SX_CLK_LCDIF1_PRE_SEL], clks[IMX6SX_CLK_PLL5_VIDEO_DIV]);
+	imx_clk_set_parent(clks[IMX6SX_CLK_LCDIF1_SEL], clks[IMX6SX_CLK_LCDIF1_PODF]);
 
 	/* Set the parent clks of PCIe lvds1 and pcie_axi to be pcie ref, axi */
-	if (clk_set_parent(clks[IMX6SX_CLK_LVDS1_SEL], clks[IMX6SX_CLK_PCIE_REF_125M]))
-		pr_err("Failed to set pcie bus parent clk.\n");
-	if (clk_set_parent(clks[IMX6SX_CLK_PCIE_AXI_SEL], clks[IMX6SX_CLK_AXI]))
-		pr_err("Failed to set pcie parent clk.\n");
+	imx_clk_set_parent(clks[IMX6SX_CLK_LVDS1_SEL], clks[IMX6SX_CLK_PCIE_REF_125M]);
+	imx_clk_set_parent(clks[IMX6SX_CLK_PCIE_AXI_SEL], clks[IMX6SX_CLK_AXI]);
 
 	/*
 	 * Init enet system AHB clock, set to 200Mhz
 	 * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB
 	 */
-	clk_set_parent(clks[IMX6SX_CLK_ENET_PRE_SEL], clks[IMX6SX_CLK_PLL2_PFD2]);
-	clk_set_parent(clks[IMX6SX_CLK_ENET_SEL], clks[IMX6SX_CLK_ENET_PODF]);
-	clk_set_rate(clks[IMX6SX_CLK_ENET_PODF], 200000000);
-	clk_set_rate(clks[IMX6SX_CLK_ENET_REF], 125000000);
-	clk_set_rate(clks[IMX6SX_CLK_ENET2_REF], 125000000);
+	imx_clk_set_parent(clks[IMX6SX_CLK_ENET_PRE_SEL], clks[IMX6SX_CLK_PLL2_PFD2]);
+	imx_clk_set_parent(clks[IMX6SX_CLK_ENET_SEL], clks[IMX6SX_CLK_ENET_PODF]);
+	imx_clk_set_rate(clks[IMX6SX_CLK_ENET_PODF], 200000000);
+	imx_clk_set_rate(clks[IMX6SX_CLK_ENET_REF], 125000000);
+	imx_clk_set_rate(clks[IMX6SX_CLK_ENET2_REF], 125000000);
 
 	/* Audio clocks */
-	clk_set_rate(clks[IMX6SX_CLK_PLL4_AUDIO_DIV], 393216000);
+	imx_clk_set_rate(clks[IMX6SX_CLK_PLL4_AUDIO_DIV], 393216000);
 
-	clk_set_parent(clks[IMX6SX_CLK_SPDIF_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]);
-	clk_set_rate(clks[IMX6SX_CLK_SPDIF_PODF], 98304000);
+	imx_clk_set_parent(clks[IMX6SX_CLK_SPDIF_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]);
+	imx_clk_set_rate(clks[IMX6SX_CLK_SPDIF_PODF], 98304000);
 
-	clk_set_parent(clks[IMX6SX_CLK_AUDIO_SEL], clks[IMX6SX_CLK_PLL3_USB_OTG]);
-	clk_set_rate(clks[IMX6SX_CLK_AUDIO_PODF], 24000000);
+	imx_clk_set_parent(clks[IMX6SX_CLK_AUDIO_SEL], clks[IMX6SX_CLK_PLL3_USB_OTG]);
+	imx_clk_set_rate(clks[IMX6SX_CLK_AUDIO_PODF], 24000000);
 
-	clk_set_parent(clks[IMX6SX_CLK_SSI1_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]);
-	clk_set_parent(clks[IMX6SX_CLK_SSI2_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]);
-	clk_set_parent(clks[IMX6SX_CLK_SSI3_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]);
-	clk_set_rate(clks[IMX6SX_CLK_SSI1_PODF], 24576000);
-	clk_set_rate(clks[IMX6SX_CLK_SSI2_PODF], 24576000);
-	clk_set_rate(clks[IMX6SX_CLK_SSI3_PODF], 24576000);
+	imx_clk_set_parent(clks[IMX6SX_CLK_SSI1_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]);
+	imx_clk_set_parent(clks[IMX6SX_CLK_SSI2_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]);
+	imx_clk_set_parent(clks[IMX6SX_CLK_SSI3_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]);
+	imx_clk_set_rate(clks[IMX6SX_CLK_SSI1_PODF], 24576000);
+	imx_clk_set_rate(clks[IMX6SX_CLK_SSI2_PODF], 24576000);
+	imx_clk_set_rate(clks[IMX6SX_CLK_SSI3_PODF], 24576000);
 
-	clk_set_parent(clks[IMX6SX_CLK_ESAI_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]);
-	clk_set_rate(clks[IMX6SX_CLK_ESAI_PODF], 24576000);
+	imx_clk_set_parent(clks[IMX6SX_CLK_ESAI_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]);
+	imx_clk_set_rate(clks[IMX6SX_CLK_ESAI_PODF], 24576000);
 
 	/* Set parent clock for vadc */
-	clk_set_parent(clks[IMX6SX_CLK_VID_SEL], clks[IMX6SX_CLK_PLL3_USB_OTG]);
+	imx_clk_set_parent(clks[IMX6SX_CLK_VID_SEL], clks[IMX6SX_CLK_PLL3_USB_OTG]);
 
 	/* default parent of can_sel clock is invalid, manually set it here */
-	clk_set_parent(clks[IMX6SX_CLK_CAN_SEL], clks[IMX6SX_CLK_PLL3_60M]);
+	imx_clk_set_parent(clks[IMX6SX_CLK_CAN_SEL], clks[IMX6SX_CLK_PLL3_60M]);
 
 	/* Update gpu clock from default 528M to 720M */
-	clk_set_parent(clks[IMX6SX_CLK_GPU_CORE_SEL], clks[IMX6SX_CLK_PLL3_PFD0]);
-	clk_set_parent(clks[IMX6SX_CLK_GPU_AXI_SEL], clks[IMX6SX_CLK_PLL3_PFD0]);
+	imx_clk_set_parent(clks[IMX6SX_CLK_GPU_CORE_SEL], clks[IMX6SX_CLK_PLL3_PFD0]);
+	imx_clk_set_parent(clks[IMX6SX_CLK_GPU_AXI_SEL], clks[IMX6SX_CLK_PLL3_PFD0]);
 
 
 	/* Set initial power mode */
diff --git a/arch/arm/mach-imx/clk-pllv3.c b/arch/arm/mach-imx/clk-pllv3.c
index bd257ae0bc2b..f121175b25a3 100644
--- a/arch/arm/mach-imx/clk-pllv3.c
+++ b/arch/arm/mach-imx/clk-pllv3.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2012-2013 Freescale Semiconductor, Inc.
+ * Copyright 2012-2014 Freescale Semiconductor, Inc.
  * Copyright 2012 Linaro Ltd.
  *
  * The code contained herein is licensed under the GNU General Public
@@ -439,7 +439,7 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
 
 	init.name = name;
 	init.ops = ops;
-	init.flags = CLK_SET_RATE_GATE;
+	init.flags = 0;
 	init.parent_names = &parent_name;
 	init.num_parents = 1;
 
diff --git a/arch/arm/mach-imx/clk.h b/arch/arm/mach-imx/clk.h
index 0f9076909517..bac0e2fc5d80 100644
--- a/arch/arm/mach-imx/clk.h
+++ b/arch/arm/mach-imx/clk.h
@@ -51,6 +51,33 @@ static inline struct clk *imx_clk_gate2_shared(const char *name,
 			shift, 0, &imx_ccm_lock, share_count);
 }
 
+static inline void imx_clk_prepare_enable(struct clk *clk)
+{
+	int ret = clk_prepare_enable(clk);
+
+	if (ret)
+		pr_err("failed to prepare and enable clk %s: %d\n",
+			__clk_get_name(clk), ret);
+}
+
+static inline void imx_clk_set_parent(struct clk *clk, struct clk *parent)
+{
+	int ret = clk_set_parent(clk, parent);
+
+	if (ret)
+		pr_err("failed to set parent of clk %s to %s: %d\n",
+			__clk_get_name(clk), __clk_get_name(parent), ret);
+}
+
+static inline void imx_clk_set_rate(struct clk *clk, unsigned long rate)
+{
+	int ret = clk_set_rate(clk, rate);
+
+	if (ret)
+		pr_err("failed to set rate of clk %s to %ld: %d\n",
+			__clk_get_name(clk), rate, ret);
+}
+
 struct clk *imx_clk_pfd(const char *name, const char *parent_name,
 		void __iomem *reg, u8 idx);