diff options
| author | rgoyal <rgoyal@nvidia.com> | 2011-01-06 12:38:20 +0530 |
|---|---|---|
| committer | Bharat Nihalani <bnihalani@nvidia.com> | 2011-01-17 02:43:01 -0800 |
| commit | 67f82f5a597622bd0b7384862c71b901580be265 (patch) | |
| tree | b71a3d0094145399751d09fcb3187c6e586993d0 /arch | |
| parent | 66aa261e1778437a1ef1ae8e57ba5598e1fb3a24 (diff) | |
ARM: tegra: whistler: sdmmc2 controller clock to 25MHz
As seeing issue with e1219 for high clock frequency
capping it to 25 MHz, we need to resolve this issue
BUG 780995
Change-Id: I8094421b9b6d176af085d55541ef506dcefc8403
Reviewed-on: http://git-master/r/15104
Tested-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-tegra/board-whistler.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/board-whistler.c b/arch/arm/mach-tegra/board-whistler.c index d5602a2289fc..a3daa6e31215 100644 --- a/arch/arm/mach-tegra/board-whistler.c +++ b/arch/arm/mach-tegra/board-whistler.c @@ -145,6 +145,7 @@ static __initdata struct tegra_clk_init_table whistler_clk_init_table[] = { { "i2s2", "pll_a_out0", 11289600, true}, { "audio", "pll_a_out0", 11289600, true}, { "audio_2x", "audio", 22579200, true}, + { "sdmmc2", "pll_p", 25000000, false}, { NULL, NULL, 0, 0}, }; |