diff options
| author | Fugang Duan <b38611@freescale.com> | 2015-04-21 19:29:16 +0800 |
|---|---|---|
| committer | Frank Li <Frank.Li@freescale.com> | 2015-04-24 23:04:18 +0800 |
| commit | bc3d93705ebcd2dc831931841bc5906696a85f0d (patch) | |
| tree | 359ff5aeb17806ebd045e5b50dd299c0e4ee0166 /arch | |
| parent | b0624aea7db2f9599c72f108da0622792843b5e5 (diff) | |
MLK-10727-2 imx: clk-imx7d: remove imx7d enet 1588 clock parent init
Remove imx7d enet 1588 clock parent init from imx7d clock file since
1588 clock parent and rate is set in dts file.
Signed-off-by: Fugang Duan <B38611@freescale.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-imx/clk-imx7d.c | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/arch/arm/mach-imx/clk-imx7d.c b/arch/arm/mach-imx/clk-imx7d.c index 5313bed12ce4..011949eb9c04 100644 --- a/arch/arm/mach-imx/clk-imx7d.c +++ b/arch/arm/mach-imx/clk-imx7d.c @@ -899,8 +899,6 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node) imx_clk_set_parent(clks[IMX7D_ENET_AXI_ROOT_SRC], clks[IMX7D_PLL_ENET_MAIN_250M_CLK]); imx_clk_set_rate(clks[IMX7D_ENET_AXI_ROOT_CLK], 267000000); imx_clk_set_parent(clks[IMX7D_ENET_PHY_REF_ROOT_SRC], clks[IMX7D_PLL_ENET_MAIN_25M_CLK]); - imx_clk_set_parent(clks[IMX7D_ENET1_TIME_ROOT_SRC], clks[IMX7D_PLL_ENET_MAIN_100M_CLK]); - imx_clk_set_parent(clks[IMX7D_ENET2_TIME_ROOT_SRC], clks[IMX7D_PLL_ENET_MAIN_100M_CLK]); /* set uart module clock's parent clock source that must be great then 80Mhz */ if (uart_from_osc) |