diff options
| author | Hongzhang Yang <Hongzhang.Yang@freescale.com> | 2012-11-01 19:26:44 +0800 |
|---|---|---|
| committer | Hongzhang Yang <Hongzhang.Yang@freescale.com> | 2012-11-01 19:40:18 +0800 |
| commit | ed72ea67c14a15a5b9f84fadf2cbcbddd910d934 (patch) | |
| tree | f83f99585b37c3b6898c95a49cb954fe69c78468 /arch | |
| parent | 0c4ca07c7845c1977553e605a7c859946207d8c8 (diff) | |
ENGR00232087-1 MX6: Enable PU LDO gating.
1. Revert ENGR00231910 Do not disable PU regulator,revert the PU
regulator patch;
2. VPU reset register address is different on MX6 and MX5. It can
fix ENGR00230203 [Android_MX6DL_SD] Gallery: System hang after resume
from suspend during video playback. 20%
Signed-off-by: Hongzhang Yang <Hongzhang.Yang@freescale.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-mx6/mx6_anatop_regulator.c | 2 | ||||
| -rwxr-xr-x | arch/arm/plat-mxc/include/mach/mxc_vpu.h | 5 |
2 files changed, 6 insertions, 1 deletions
diff --git a/arch/arm/mach-mx6/mx6_anatop_regulator.c b/arch/arm/mach-mx6/mx6_anatop_regulator.c index 1ed5183eaa6e..9599a5439e54 100644 --- a/arch/arm/mach-mx6/mx6_anatop_regulator.c +++ b/arch/arm/mach-mx6/mx6_anatop_regulator.c @@ -210,7 +210,7 @@ static int pu_disable(struct anatop_regulator *sreg) { unsigned int reg; int ret = 0; - return 0; + /* Disable the brown out detection since we are going to be * disabling the LDO. */ diff --git a/arch/arm/plat-mxc/include/mach/mxc_vpu.h b/arch/arm/plat-mxc/include/mach/mxc_vpu.h index 0c0fa2aad38b..7a6e24f2b0dd 100755 --- a/arch/arm/plat-mxc/include/mach/mxc_vpu.h +++ b/arch/arm/plat-mxc/include/mach/mxc_vpu.h @@ -67,6 +67,7 @@ struct vpu_mem_desc { #define BIT_INT_REASON 0x174 #define MJPEG_PIC_STATUS_REG 0x3004 +#define MBC_SET_SUBBLK_EN 0x4A0 #define BIT_WORK_CTRL_BUF_BASE 0x100 #define BIT_WORK_CTRL_BUF_REG(i) (BIT_WORK_CTRL_BUF_BASE + i * 4) @@ -77,7 +78,11 @@ struct vpu_mem_desc { #define BIT_FRAME_MEM_CTRL BIT_WORK_CTRL_BUF_REG(4) #define BIT_BIT_STREAM_PARAM BIT_WORK_CTRL_BUF_REG(5) +#ifndef CONFIG_ARCH_MX6 #define BIT_RESET_CTRL 0x11C +#else +#define BIT_RESET_CTRL 0x128 +#endif /* i could be 0, 1, 2, 3 */ #define BIT_RD_PTR_BASE 0x120 |