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authorVladimir Murzin <murzin.v@gmail.com>2013-09-28 10:22:00 +0200
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>2013-10-31 16:19:20 +1100
commita40a2b670706494610d794927b9aebe77e18af8d (patch)
tree02b94031e1dc501e3ade7bb93908705006d2ee57 /arch
parenta3e31b4588443f37d82195096c6b30dff1c152c2 (diff)
powerpc/bpf: Fix DIVWU instruction opcode
Currently DIVWU stands for *signed* divw opcode: 7d 2a 4b 96 divwu r9,r10,r9 7d 2a 4b d6 divw r9,r10,r9 Use the *unsigned* divw opcode for DIVWU. Suggested-by: Vassili Karpov <av1474@comtv.ru> Reviewed-by: Vassili Karpov <av1474@comtv.ru> Signed-off-by: Vladimir Murzin <murzin.v@gmail.com> Acked-by: Matt Evans <matt@ozlabs.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/powerpc/include/asm/ppc-opcode.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h
index 99f87906de17..3132bb9365f3 100644
--- a/arch/powerpc/include/asm/ppc-opcode.h
+++ b/arch/powerpc/include/asm/ppc-opcode.h
@@ -222,7 +222,7 @@
#define PPC_INST_MULLW 0x7c0001d6
#define PPC_INST_MULHWU 0x7c000016
#define PPC_INST_MULLI 0x1c000000
-#define PPC_INST_DIVWU 0x7c0003d6
+#define PPC_INST_DIVWU 0x7c000396
#define PPC_INST_RLWINM 0x54000000
#define PPC_INST_RLDICR 0x78000004
#define PPC_INST_SLW 0x7c000030