diff options
| author | Scott Williams <scwilliams@nvidia.com> | 2011-05-20 17:33:06 -0700 |
|---|---|---|
| committer | Niket Sirsi <nsirsi@nvidia.com> | 2011-05-27 16:03:09 -0700 |
| commit | 7f3ace1aa6f98c95081478a52b56e7f1008ed114 (patch) | |
| tree | 159d795e389e6505d18b5dcf5123e086024554e2 /arch | |
| parent | 87f319f8915ff4bc6b17ac7ddeb3b1bb0edc34d9 (diff) | |
ARM: tegra: clocks: Completely remove DVFS for FPGA platforms
Dynamic Voltage & Frequency Scaling (DVFS) is not possible on
FPGA platforms. Completely remove the DVFS code from the image
on FPGA platforms to reduce the image size.
Change-Id: I4f1a8587f01e775000f48fbca7c85d75acee9c74
Reviewed-on: http://git-master/r/32466
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-tegra/Makefile | 6 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/dvfs.h | 21 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/include/mach/clk.h | 5 |
3 files changed, 30 insertions, 2 deletions
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index cfb1fe1e5eb4..89c5dd379cf9 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -6,7 +6,11 @@ obj-y += io.o obj-y += irq.o legacy_irq.o obj-y += syncpt.o obj-y += clock.o +ifneq ($(CONFIG_TEGRA_FPGA_PLATFORM),y) obj-y += dvfs.o +obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_dvfs.o +obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra3_dvfs.o +endif obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += timer-t2.o obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += timer-t3.o obj-y += gpio.o @@ -40,13 +44,11 @@ obj-$(CONFIG_TEGRA_ARB_SEMAPHORE) += arb_sema.o obj-y += clock.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_clocks.o obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra3_clocks.o -obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_dvfs.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_fuse.o ifneq ($(CONFIG_TEGRA_FPGA_PLATFORM),y) obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_speedo.o obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra3_speedo.o endif -obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra3_dvfs.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += suspend-t2.o obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += suspend-t3.o obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += sysfs-cluster.o diff --git a/arch/arm/mach-tegra/dvfs.h b/arch/arm/mach-tegra/dvfs.h index 6de35a525411..50fe81416f9f 100644 --- a/arch/arm/mach-tegra/dvfs.h +++ b/arch/arm/mach-tegra/dvfs.h @@ -87,6 +87,7 @@ struct dvfs { struct list_head reg_node; }; +#ifndef CONFIG_TEGRA_FPGA_PLATFORM void tegra_soc_init_dvfs(void); int tegra_enable_dvfs_on_clk(struct clk *c, struct dvfs *d); int dvfs_debugfs_init(struct dentry *clk_debugfs_root); @@ -96,5 +97,25 @@ void tegra_dvfs_add_relationships(struct dvfs_relationship *rels, int n); void tegra_dvfs_rail_enable(struct dvfs_rail *rail); void tegra_dvfs_rail_disable(struct dvfs_rail *rail); bool tegra_dvfs_rail_updating(struct clk *clk); +#else +static inline void tegra_soc_init_dvfs(void) +{} +static inline int tegra_enable_dvfs_on_clk(struct clk *c, struct dvfs *d) +{ return 0; } +static inline int dvfs_debugfs_init(struct dentry *clk_debugfs_root) +{ return 0; } +static inline int tegra_dvfs_late_init(void) +{ return 0; } +static inline int tegra_dvfs_init_rails(struct dvfs_rail *dvfs_rails[], int n) +{ return 0; } +static inline void tegra_dvfs_add_relationships(struct dvfs_relationship *rels, int n) +{} +static inline void tegra_dvfs_rail_enable(struct dvfs_rail *rail) +{} +static inline void tegra_dvfs_rail_disable(struct dvfs_rail *rail) +{} +static inline bool tegra_dvfs_rail_updating(struct clk *clk) +{ return false; } +#endif #endif diff --git a/arch/arm/mach-tegra/include/mach/clk.h b/arch/arm/mach-tegra/include/mach/clk.h index d7ae8a0b1f05..0ca1a8924e21 100644 --- a/arch/arm/mach-tegra/include/mach/clk.h +++ b/arch/arm/mach-tegra/include/mach/clk.h @@ -37,7 +37,12 @@ enum tegra_clk_ex_param { void tegra_periph_reset_deassert(struct clk *c); void tegra_periph_reset_assert(struct clk *c); +#ifndef CONFIG_TEGRA_FPGA_PLATFORM int tegra_dvfs_set_rate(struct clk *c, unsigned long rate); +#else +static inline int tegra_dvfs_set_rate(struct clk *c, unsigned long rate) +{ return 0; } +#endif unsigned long clk_get_rate_all_locked(struct clk *c); #ifdef CONFIG_ARCH_TEGRA_2x_SOC void tegra_sdmmc_tap_delay(struct clk *c, int delay); |