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| author | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2015-06-03 18:17:19 +0200 |
|---|---|---|
| committer | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2015-06-03 18:17:19 +0200 |
| commit | 48507630703287a594d6a485af1913674cec836d (patch) | |
| tree | 5f2439b783f7514fbff43fffd06c17bdf886ba1d /arch | |
| parent | eeea9fbe6bb8db5d0caa485652e423371209cebf (diff) | |
colibri_t20: improve pmic rtc accuracy
It looks like our crystal load capacitance is way off as we just copied
NVIDIA's default setting being the lowest possible 1.5 pF due to their
boards having 20 pF external caps while our hardware does not have any
external caps assembled and we should use the highest 12.5 pF setting.
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-tegra/board-colibri_t20-power.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/board-colibri_t20-power.c b/arch/arm/mach-tegra/board-colibri_t20-power.c index ca1f5e4a2f95..786670e16f23 100644 --- a/arch/arm/mach-tegra/board-colibri_t20-power.c +++ b/arch/arm/mach-tegra/board-colibri_t20-power.c @@ -180,7 +180,7 @@ static struct tps6586x_rtc_platform_data rtc_data = { .month = 1, .day = 1, }, - .cl_sel = TPS6586X_RTC_CL_SEL_1_5PF /* use lowest (external 20pF cap) */ + .cl_sel = TPS6586X_RTC_CL_SEL_12_5PF /* use highest (no external cap) */ }; #define TPS_REG(_id, _data) \ |