diff options
| author | Dong Aisheng <b29396@freescale.com> | 2014-11-11 21:04:07 +0800 |
|---|---|---|
| committer | Dong Aisheng <b29396@freescale.com> | 2014-11-14 17:24:50 +0800 |
| commit | 21bb768f420ead4f9c0244f52b6cecb5e3eff997 (patch) | |
| tree | 44ebd6f9863c58b08ecddd0698d992e03a97bb31 /arch | |
| parent | fdfda34d35d79686da1b4eb6bbde73fc1360b34d (diff) | |
MLK-9833-1 ARM: imx6sx: only set can clock parent when M4 disabled
Since CAN device is allocated to run on M4 and handled by M4 if M4 is enabled,
so we do not set CAN parent clock when M4 is enabled.
Signed-off-by: Dong Aisheng <b29396@freescale.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-imx/clk-imx6sx.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/mach-imx/clk-imx6sx.c b/arch/arm/mach-imx/clk-imx6sx.c index b4d07595adbc..96ae86f7cf24 100644 --- a/arch/arm/mach-imx/clk-imx6sx.c +++ b/arch/arm/mach-imx/clk-imx6sx.c @@ -571,9 +571,6 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) /* Set parent clock for vadc */ imx_clk_set_parent(clks[IMX6SX_CLK_VID_SEL], clks[IMX6SX_CLK_PLL3_USB_OTG]); - /* default parent of can_sel clock is invalid, manually set it here */ - imx_clk_set_parent(clks[IMX6SX_CLK_CAN_SEL], clks[IMX6SX_CLK_PLL3_60M]); - /* Update gpu clock from default 528M to 720M */ imx_clk_set_parent(clks[IMX6SX_CLK_GPU_CORE_SEL], clks[IMX6SX_CLK_PLL3_PFD0]); imx_clk_set_parent(clks[IMX6SX_CLK_GPU_AXI_SEL], clks[IMX6SX_CLK_PLL3_PFD0]); @@ -582,6 +579,9 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) imx_clk_set_parent(clks[IMX6SX_CLK_QSPI1_SEL], clks[IMX6SX_CLK_PLL2_BUS]); imx_clk_set_parent(clks[IMX6SX_CLK_QSPI2_SEL], clks[IMX6SX_CLK_PLL2_BUS]); + if (!imx_src_is_m4_enabled()) + /* default parent of can_sel clock is invalid, manually set it here */ + imx_clk_set_parent(clks[IMX6SX_CLK_CAN_SEL], clks[IMX6SX_CLK_PLL3_60M]); /* * Enable clocks only after both parent and rate are all initialized * as needed |