diff options
| author | Robby Cai <r63905@freescale.com> | 2014-11-24 17:05:37 +0800 |
|---|---|---|
| committer | Robby Cai <r63905@freescale.com> | 2014-11-25 15:39:20 +0800 |
| commit | 65999b877a9d6ad53ad6f8ee9d3f80abb4383603 (patch) | |
| tree | 254aeb8a13cfa6f78d4a613388813dffe8d82302 /arch | |
| parent | 51efb4c5bfab6eae848fa857d534f5d82721d2e1 (diff) | |
MLK-9906 imx6sl: make epdc pixel clock derive from PLL2_PFD1
Previously the pixel clock for LCDIF and EPDC shares the same parent clock
PLL5_VIDEO. This will bring the following error boot message:
clk_pllv3_av_set_rate: cannot configure divider when PLL is powered on
The reason is the dual-display case breaks the rule added by the
patch "93a9e3d0b88203cb523dd92e85590683d6a85fdf ENGR00318063-6:
ARM: imx6: add CLK_SET_RATE_GATE flag for PLL clocks" which adds the
requirement "the clock must be gated across rate change"
After LCDIF pixel clock is configured and enabled, EPDC pixel clock
need to be configured also but the parent PLL is already enabled by
LCDIF driver thus the configuration will fail.
On i.MX6SL, we need support LCD display and EPDC display simultaneously,
then we cannot disable the PLL clock when LCD or EPDC is working already.
So we switch the parent for EPDC pixel clock to PLL2_PFD1.
Signed-off-by: Robby Cai <r63905@freescale.com>
(cherry picked from commit 8aa38347f486124f0bcec767b721a820fbae7010)
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-imx/clk-imx6sl.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-imx/clk-imx6sl.c b/arch/arm/mach-imx/clk-imx6sl.c index 88ec45adb069..f1e6f254e5bc 100644 --- a/arch/arm/mach-imx/clk-imx6sl.c +++ b/arch/arm/mach-imx/clk-imx6sl.c @@ -411,7 +411,7 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node) imx_clk_set_parent(clks[IMX6SL_CLK_LCDIF_PIX_SEL], clks[IMX6SL_CLK_PLL5_VIDEO_DIV]); imx_clk_set_parent(clks[IMX6SL_CLK_EPDC_PIX_SEL], - clks[IMX6SL_CLK_PLL5_VIDEO_DIV]); + clks[IMX6SL_CLK_PLL2_PFD1]); imx_clk_set_parent(clks[IMX6SL_CLK_EPDC_AXI_SEL], clks[IMX6SL_CLK_PLL2_PFD2]); imx_clk_set_rate(clks[IMX6SL_CLK_EPDC_AXI], 200000000); |