diff options
| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2017-03-06 17:40:41 +0100 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2018-03-22 09:17:37 +0100 |
| commit | ba2f98696ad210f01d86751f3b3898c062d44d8a (patch) | |
| tree | bc521aed045d137ba05cc5e1484ddc10239a5926 /arch | |
| parent | 88787c040211d0a809c71c444e05208d825ad614 (diff) | |
ARM: dts: r8a7792: Remove unit-address and reg from integrated cache
[ Upstream commit a0504f0880c11da301dc2b5a5135bd02376e367e ]
The Cortex-A15 cache controller is an integrated controller, and thus
the device node representing it should not have a unit-addresses or reg
property.
Fixes: 7c4163aae3d8e5b9 ("ARM: dts: r8a7792: initial SoC device tree")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Sasha Levin <alexander.levin@microsoft.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/boot/dts/r8a7792.dtsi | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index 713141d38b3e..0b50c6766867 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -58,9 +58,8 @@ next-level-cache = <&L2_CA15>; }; - L2_CA15: cache-controller@0 { + L2_CA15: cache-controller-0 { compatible = "cache"; - reg = <0>; cache-unified; cache-level = <2>; power-domains = <&sysc R8A7792_PD_CA15_SCU>; |