diff options
| author | Eric Miao <eric.y.miao@gmail.com> | 2010-07-15 21:54:20 +0800 |
|---|---|---|
| committer | Eric Miao <eric.y.miao@gmail.com> | 2010-08-05 14:34:45 +0800 |
| commit | 4d4a339dd51390066d09701876a499996f1a5fdc (patch) | |
| tree | b65deef07a2c7ce037e58effdc5fc039dfb339dc /arch | |
| parent | 8022887cda044524610ef2a5a45feb9d96b11b4f (diff) | |
[ARM] mmp: move mmp2 specific timer code to mmp2.c
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-mmp/mmp2.c | 21 | ||||
| -rw-r--r-- | arch/arm/mach-mmp/time.c | 21 |
2 files changed, 21 insertions, 21 deletions
diff --git a/arch/arm/mach-mmp/mmp2.c b/arch/arm/mach-mmp/mmp2.c index 7f5eb059bb01..b3fddacc7cb5 100644 --- a/arch/arm/mach-mmp/mmp2.c +++ b/arch/arm/mach-mmp/mmp2.c @@ -17,6 +17,7 @@ #include <asm/hardware/cache-tauros2.h> +#include <asm/mach/time.h> #include <mach/addr-map.h> #include <mach/regs-apbc.h> #include <mach/regs-apmu.h> @@ -158,6 +159,26 @@ static int __init mmp2_init(void) } postcore_initcall(mmp2_init); +static void __init mmp2_timer_init(void) +{ + unsigned long clk_rst; + + __raw_writel(APBC_APBCLK | APBC_RST, APBC_MMP2_TIMERS); + + /* + * enable bus/functional clock, enable 6.5MHz (divider 4), + * release reset + */ + clk_rst = APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1); + __raw_writel(clk_rst, APBC_MMP2_TIMERS); + + timer_init(IRQ_MMP2_TIMER1); +} + +struct sys_timer mmp2_timer = { + .init = mmp2_timer_init, +}; + /* on-chip devices */ MMP2_DEVICE(uart1, "pxa2xx-uart", 0, UART1, 0xd4030000, 0x30, 4, 5); MMP2_DEVICE(uart2, "pxa2xx-uart", 1, UART2, 0xd4017000, 0x30, 20, 21); diff --git a/arch/arm/mach-mmp/time.c b/arch/arm/mach-mmp/time.c index cf75694e9687..66528193f939 100644 --- a/arch/arm/mach-mmp/time.c +++ b/arch/arm/mach-mmp/time.c @@ -200,24 +200,3 @@ void __init timer_init(int irq) clocksource_register(&cksrc); clockevents_register_device(&ckevt); } - -static void __init mmp2_timer_init(void) -{ - unsigned long clk_rst; - - __raw_writel(APBC_APBCLK | APBC_RST, APBC_MMP2_TIMERS); - - /* - * enable bus/functional clock, enable 6.5MHz (divider 4), - * release reset - */ - clk_rst = APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1); - __raw_writel(clk_rst, APBC_MMP2_TIMERS); - - timer_init(IRQ_MMP2_TIMER1); -} - -struct sys_timer mmp2_timer = { - .init = mmp2_timer_init, -}; - |