summaryrefslogtreecommitdiff
path: root/arch
diff options
context:
space:
mode:
authorguoyin.chen <guoyin.chen@freescale.com>2013-08-12 13:12:19 +0800
committerguoyin.chen <guoyin.chen@freescale.com>2013-08-12 13:12:19 +0800
commiteaa67b8feb7d97821fd08749430392eba2900091 (patch)
treefa91e19b64a44da61e0d63b04c61bd92f77dbf38 /arch
parentf9017b715db9ac5a2ece1216117ee5185eda9f69 (diff)
parent98894af902b374bcbc1769f18662d587c3859304 (diff)
Merge remote-tracking branch 'fsl-linux-sdk/imx_3.0.35_4.1.0' into imx_3.0.35_android
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-mx6/board-mx6q_sabreauto.c9
-rwxr-xr-xarch/arm/mach-mx6/board-mx6sl_arm2.c2
-rw-r--r--arch/arm/mach-mx6/board-mx6sl_evk.c2
-rwxr-xr-xarch/arm/mach-mx6/clock_mx6sl.c37
-rw-r--r--arch/arm/mach-mx6/pm.c53
-rw-r--r--arch/arm/plat-mxc/include/mach/epdc.h1
6 files changed, 60 insertions, 44 deletions
diff --git a/arch/arm/mach-mx6/board-mx6q_sabreauto.c b/arch/arm/mach-mx6/board-mx6q_sabreauto.c
index e5378ba92cf6..86d6b1858e95 100644
--- a/arch/arm/mach-mx6/board-mx6q_sabreauto.c
+++ b/arch/arm/mach-mx6/board-mx6q_sabreauto.c
@@ -1145,6 +1145,15 @@ static int flexcan1_en;
static void mx6q_flexcan_switch(void)
{
if (flexcan0_en || flexcan1_en) {
+ /*
+ * The transceiver TJA1041A on sabreauto RevE baseboard will
+ * fail to transit to Normal state if EN/STBY is high by default
+ * after board power up. So we set the EN/STBY initial state to low
+ * first then to high to guarantee the state transition successfully.
+ */
+ gpio_set_value_cansleep(SABREAUTO_CAN_EN, 0);
+ gpio_set_value_cansleep(SABREAUTO_CAN_STBY, 0);
+
gpio_set_value_cansleep(SABREAUTO_CAN_EN, 1);
gpio_set_value_cansleep(SABREAUTO_CAN_STBY, 1);
/* Enable STEER pin if CAN1 interface is required.
diff --git a/arch/arm/mach-mx6/board-mx6sl_arm2.c b/arch/arm/mach-mx6/board-mx6sl_arm2.c
index 09d3c182ec45..a29f3bcb9b07 100755
--- a/arch/arm/mach-mx6/board-mx6sl_arm2.c
+++ b/arch/arm/mach-mx6/board-mx6sl_arm2.c
@@ -877,7 +877,6 @@ static struct imx_epdc_fb_platform_data epdc_data = {
.put_pins = epdc_put_pins,
.enable_pins = epdc_enable_pins,
.disable_pins = epdc_disable_pins,
- .pg_display_mix = true,
};
static int spdc_get_pins(void)
@@ -1105,7 +1104,6 @@ static struct mxc_fb_platform_data fb_data[] = {
.mode_str = "SEIKO-WVGA",
.mode = video_modes,
.num_modes = ARRAY_SIZE(video_modes),
- .pg_display_mix = true,
},
};
diff --git a/arch/arm/mach-mx6/board-mx6sl_evk.c b/arch/arm/mach-mx6/board-mx6sl_evk.c
index 7561ba90fa15..adc8b463b78b 100644
--- a/arch/arm/mach-mx6/board-mx6sl_evk.c
+++ b/arch/arm/mach-mx6/board-mx6sl_evk.c
@@ -1084,7 +1084,6 @@ static struct imx_epdc_fb_platform_data epdc_data = {
.put_pins = epdc_put_pins,
.enable_pins = epdc_enable_pins,
.disable_pins = epdc_disable_pins,
- .pg_display_mix = true,
};
static int spdc_get_pins(void)
@@ -1317,7 +1316,6 @@ static struct mxc_fb_platform_data wvga_fb_data[] = {
.mode_str = "SEIKO-WVGA",
.mode = wvga_video_modes,
.num_modes = ARRAY_SIZE(wvga_video_modes),
- .pg_display_mix = true,
},
};
diff --git a/arch/arm/mach-mx6/clock_mx6sl.c b/arch/arm/mach-mx6/clock_mx6sl.c
index e95c45484362..f375b4ac9dd4 100755
--- a/arch/arm/mach-mx6/clock_mx6sl.c
+++ b/arch/arm/mach-mx6/clock_mx6sl.c
@@ -89,11 +89,6 @@ DEFINE_SPINLOCK(mx6sl_clk_lock);
#define MXC_TPRER 0x04
#define V2_TPRER_PRE24M_OFFSET 12
#define V2_TPRER_PRE24M_MASK 0xF
-#define GPC_CNTR_OFFSET 0x0
-#define GPC_PGC_DISP_PGCR_OFFSET 0x240
-#define GPC_PGC_DISP_PUPSCR_OFFSET 0x244
-#define GPC_PGC_DISP_PDNSCR_OFFSET 0x248
-#define GPC_PGC_DISP_SR_OFFSET 0x24c
/* We need to check the exp status again after timer expiration,
* as there might be interrupt coming between the first time exp
@@ -1904,33 +1899,6 @@ static struct clk i2c_clk[] = {
},
};
-static int _display_mix_enable(struct clk *clk)
-{
- if (cpu_is_mx6sl() && (mx6sl_revision() >= IMX_CHIP_REVISION_1_2)) {
- __raw_writel(0x0, gpc_base + GPC_PGC_DISP_PGCR_OFFSET);
- __raw_writel(0x20, gpc_base + GPC_CNTR_OFFSET);
- __raw_writel(0x1, gpc_base + GPC_PGC_DISP_SR_OFFSET);
- }
- return 0;
-}
-
-static void _display_mix_disable(struct clk *clk)
-{
- if (cpu_is_mx6sl() && (mx6sl_revision() >= IMX_CHIP_REVISION_1_2)) {
- __raw_writel(0x101, gpc_base + GPC_PGC_DISP_PUPSCR_OFFSET);
- __raw_writel(0x101, gpc_base + GPC_PGC_DISP_PDNSCR_OFFSET);
-
- __raw_writel(0x1, gpc_base + GPC_PGC_DISP_PGCR_OFFSET);
- __raw_writel(0x10, gpc_base + GPC_CNTR_OFFSET);
- }
-}
-
-static struct clk display_mix = {
- __INIT_CLK_DEBUG(display_mix)
- .enable = _display_mix_enable,
- .disable = _display_mix_disable,
-};
-
static int _clk_ipu1_set_parent(struct clk *clk, struct clk *parent)
{
int mux;
@@ -2069,7 +2037,6 @@ static struct clk ipu2_clk = {
.set_rate = _clk_ipu2_set_rate,
.get_rate = _clk_ipu2_get_rate,
.flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
- .secondary = &display_mix,
};
static struct clk usdhc_dep_clk = {
@@ -2836,7 +2803,6 @@ static struct clk pxp_axi_clk = {
.round_rate = _clk_pxp_epdc_axi_round_rate,
.get_rate = _clk_pxp_axi_get_rate,
.flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
- .secondary = &display_mix,
};
static struct clk epdc_axi_clk = {
@@ -2852,7 +2818,6 @@ static struct clk epdc_axi_clk = {
.round_rate = _clk_pxp_epdc_axi_round_rate,
.get_rate = _clk_epdc_axi_get_rate,
.flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
- .secondary = &display_mix,
};
static unsigned long _clk_lcdif_pix_get_rate(struct clk *clk)
@@ -3002,7 +2967,6 @@ static struct clk lcdif_pix_clk = {
.round_rate = _clk_epdc_lcdif_pix_round_rate,
.get_rate = _clk_lcdif_pix_get_rate,
.flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
- .secondary = &display_mix,
};
static struct clk epdc_pix_clk = {
@@ -3018,7 +2982,6 @@ static struct clk epdc_pix_clk = {
.round_rate = _clk_epdc_lcdif_pix_round_rate,
.get_rate = _clk_epdc_pix_get_rate,
.flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
- .secondary = &display_mix,
};
static unsigned long _clk_spdif_round_rate(struct clk *clk,
unsigned long rate)
diff --git a/arch/arm/mach-mx6/pm.c b/arch/arm/mach-mx6/pm.c
index f2efa00efb47..d9c04e11bed0 100644
--- a/arch/arm/mach-mx6/pm.c
+++ b/arch/arm/mach-mx6/pm.c
@@ -50,7 +50,11 @@
#define GPC_ISR3_OFFSET 0x20
#define GPC_ISR4_OFFSET 0x24
#define GPC_CNTR_OFFSET 0x0
-#define GPC_PGC_DISP_PGCR_OFFSET 0x240
+#define GPC_PGC_DISP_PGCR_OFFSET 0x240
+#define GPC_PGC_DISP_PUPSCR_OFFSET 0x244
+#define GPC_PGC_DISP_PDNSCR_OFFSET 0x248
+#define GPC_PGC_DISP_SR_OFFSET 0x24c
+#define GPC_PGC_GPU_PGCR_OFFSET 0x260
#define GPC_PGC_CPU_PDN_OFFSET 0x2a0
#define GPC_PGC_CPU_PUPSCR_OFFSET 0x2a4
#define GPC_PGC_CPU_PDNSCR_OFFSET 0x2a8
@@ -170,6 +174,47 @@ static void usb_power_up_handler(void)
}
+static void disp_power_down(void)
+{
+ if (cpu_is_mx6sl() && (mx6sl_revision() >= IMX_CHIP_REVISION_1_2)) {
+
+ __raw_writel(0xFFFFFFFF, gpc_base + GPC_PGC_DISP_PUPSCR_OFFSET);
+ __raw_writel(0xFFFFFFFF, gpc_base + GPC_PGC_DISP_PDNSCR_OFFSET);
+
+ __raw_writel(0x1, gpc_base + GPC_PGC_DISP_PGCR_OFFSET);
+ __raw_writel(0x10, gpc_base + GPC_CNTR_OFFSET);
+
+ /* Disable EPDC/LCDIF pix clock, and EPDC/LCDIF/PXP axi clock */
+ __raw_writel(ccgr3 &
+ ~MXC_CCM_CCGRx_CG5_MASK &
+ ~MXC_CCM_CCGRx_CG4_MASK &
+ ~MXC_CCM_CCGRx_CG3_MASK &
+ ~MXC_CCM_CCGRx_CG2_MASK &
+ ~MXC_CCM_CCGRx_CG1_MASK, MXC_CCM_CCGR3);
+
+ }
+}
+
+static void disp_power_up(void)
+{
+ if (cpu_is_mx6sl() && (mx6sl_revision() >= IMX_CHIP_REVISION_1_2)) {
+ /*
+ * Need to enable EPDC/LCDIF pix clock, and
+ * EPDC/LCDIF/PXP axi clock before power up.
+ */
+ __raw_writel(ccgr3 |
+ MXC_CCM_CCGRx_CG5_MASK |
+ MXC_CCM_CCGRx_CG4_MASK |
+ MXC_CCM_CCGRx_CG3_MASK |
+ MXC_CCM_CCGRx_CG2_MASK |
+ MXC_CCM_CCGRx_CG1_MASK, MXC_CCM_CCGR3);
+
+ __raw_writel(0x0, gpc_base + GPC_PGC_DISP_PGCR_OFFSET);
+ __raw_writel(0x20, gpc_base + GPC_CNTR_OFFSET);
+ __raw_writel(0x1, gpc_base + GPC_PGC_DISP_SR_OFFSET);
+ }
+}
+
static void mx6_suspend_store(void)
{
/* save some settings before suspend */
@@ -274,12 +319,14 @@ static int mx6_suspend_enter(suspend_state_t state)
switch (state) {
case PM_SUSPEND_MEM:
+ disp_power_down();
usb_power_down_handler();
mxc_cpu_lp_set(ARM_POWER_OFF);
arm_pg = true;
break;
case PM_SUSPEND_STANDBY:
if (cpu_is_mx6sl()) {
+ disp_power_down();
usb_power_down_handler();
mxc_cpu_lp_set(STOP_XTAL_ON);
arm_pg = true;
@@ -347,8 +394,10 @@ static int mx6_suspend_enter(suspend_state_t state)
restore_gic_dist_state(0, &gds);
restore_gic_cpu_state(0, &gcs);
}
- if (state == PM_SUSPEND_MEM || (cpu_is_mx6sl()))
+ if (state == PM_SUSPEND_MEM || (cpu_is_mx6sl())) {
usb_power_up_handler();
+ disp_power_up();
+ }
mx6_suspend_restore();
diff --git a/arch/arm/plat-mxc/include/mach/epdc.h b/arch/arm/plat-mxc/include/mach/epdc.h
index 08fef76148f3..e6dae37d9a59 100644
--- a/arch/arm/plat-mxc/include/mach/epdc.h
+++ b/arch/arm/plat-mxc/include/mach/epdc.h
@@ -36,7 +36,6 @@ struct imx_epdc_fb_platform_data {
void (*put_pins) (void);
void (*enable_pins) (void);
void (*disable_pins) (void);
- bool pg_display_mix;
};
struct imx_spdc_panel_init_set {