ENGR00126361-1 MX50 DCP driver enable with clock gating

Added DCP device and clock gate support to MX50 MSL

Signed-off-by: Anish Trivedi <anish@freescale.com>

5 files changed, 60 insertions, 5 deletions

diff --git a/arch/arm/configs/imx5_defconfig b/arch/arm/configs/imx5_defconfig
index a3e59dd99538..d50a75476479 100644
--- a/arch/arm/configs/imx5_defconfig
+++ b/arch/arm/configs/imx5_defconfig
@@ -2096,8 +2096,8 @@ CONFIG_CRYPTO_ALGAPI2=y
 # CONFIG_CRYPTO_NULL is not set
 # CONFIG_CRYPTO_CRYPTD is not set
 # CONFIG_CRYPTO_AUTHENC is not set
-# CONFIG_CRYPTO_TEST is not set
-# CONFIG_CRYPTO_CRYPTODEV is not set
+CONFIG_CRYPTO_TEST=m
+CONFIG_CRYPTO_CRYPTODEV=y
 
 #
 # Authenticated Encryption with Associated Data
@@ -2109,10 +2109,10 @@ CONFIG_CRYPTO_ALGAPI2=y
 #
 # Block modes
 #
-# CONFIG_CRYPTO_CBC is not set
+CONFIG_CRYPTO_CBC=y
 # CONFIG_CRYPTO_CTR is not set
 # CONFIG_CRYPTO_CTS is not set
-# CONFIG_CRYPTO_ECB is not set
+CONFIG_CRYPTO_ECB=y
 # CONFIG_CRYPTO_LRW is not set
 # CONFIG_CRYPTO_PCBC is not set
 # CONFIG_CRYPTO_XTS is not set
@@ -2143,7 +2143,7 @@ CONFIG_CRYPTO_ALGAPI2=y
 #
 # Ciphers
 #
-# CONFIG_CRYPTO_AES is not set
+CONFIG_CRYPTO_AES=y
 # CONFIG_CRYPTO_ANUBIS is not set
 # CONFIG_CRYPTO_ARC4 is not set
 # CONFIG_CRYPTO_BLOWFISH is not set
diff --git a/arch/arm/mach-mx5/clock_mx50.c b/arch/arm/mach-mx5/clock_mx50.c
index 247693b296b3..2fa0f08846c5 100644
--- a/arch/arm/mach-mx5/clock_mx50.c
+++ b/arch/arm/mach-mx5/clock_mx50.c
@@ -2485,6 +2485,28 @@ static struct clk apbh_dma_clk = {
 	.enable_shift = MXC_CCM_CCGR7_CG10_OFFSET,
 };
 
+struct clk dcp_clk[] = {
+	{
+	.name = "dcp_clk",
+	.id = 0,
+	.parent = &ahb_clk,
+	.secondary = &dcp_clk[1],
+	.enable = _clk_enable,
+	.enable_reg = MXC_CCM_CCGR7,
+	.enable_shift = MXC_CCM_CCGR7_CG11_OFFSET,
+	.disable = _clk_disable,
+	},
+	{
+	 .name = "dcp_sec1_clk",
+	 .parent = &apbh_dma_clk,
+	 .secondary = &dcp_clk[2],
+	},
+	{
+	 .name = "dcp_sec2_clk",
+	 .parent = &ddr_clk,
+	},
+};
+
 static int _clk_display_axi_set_parent(struct clk *clk, struct clk *parent)
 {
 	u32 reg, mux;
@@ -3059,6 +3081,9 @@ static struct clk *mxc_clks[] = {
 	&pgc_clk,
 	&rtc_clk,
 	&rng_clk,
+	&dcp_clk[0],
+	&dcp_clk[1],
+	&dcp_clk[2],
 	&owire_clk,
 	&fec_clk[0],
 	&fec_clk[1],
diff --git a/arch/arm/mach-mx5/devices.c b/arch/arm/mach-mx5/devices.c
index 39d77e133747..879d78cfbcf3 100644
--- a/arch/arm/mach-mx5/devices.c
+++ b/arch/arm/mach-mx5/devices.c
@@ -473,6 +473,34 @@ struct platform_device mxcscc_device = {
 	.resource = scc_resources,
 };
 
+static struct resource dcp_resources[] = {
+
+	{
+		.flags = IORESOURCE_MEM,
+		.start = DCP_BASE_ADDR,
+		.end   = DCP_BASE_ADDR + 0x2000 - 1,
+	}, {
+		.flags = IORESOURCE_IRQ,
+		.start = MXC_INT_DCP_CHAN0,
+		.end = MXC_INT_DCP_CHAN0,
+	}, {
+		.flags = IORESOURCE_IRQ,
+		.start = MXC_INT_DCP_CHAN1_3,
+		.end = MXC_INT_DCP_CHAN1_3,
+	},
+};
+
+struct platform_device dcp_device = {
+	.name = "dcp",
+	.id = 0,
+	.num_resources = ARRAY_SIZE(dcp_resources),
+	.resource = dcp_resources,
+	.dev = {
+		.coherent_dma_mask = DMA_BIT_MASK(32),
+	},
+};
+
+
 static struct resource rngb_resources[] = {
 	{
 		.start = RNGB_BASE_ADDR,
diff --git a/arch/arm/mach-mx5/devices.h b/arch/arm/mach-mx5/devices.h
index f7517fb8083d..aa6fa06c3ee5 100644
--- a/arch/arm/mach-mx5/devices.h
+++ b/arch/arm/mach-mx5/devices.h
@@ -76,3 +76,4 @@ extern struct platform_device mxs_viim;
 extern struct platform_device mxs_dma_apbh_device;
 extern struct platform_device gpmi_nfc_device;
 extern struct platform_device mxc_rngb_device;
+extern struct platform_device dcp_device;
diff --git a/arch/arm/mach-mx5/mx50_arm2.c b/arch/arm/mach-mx5/mx50_arm2.c
index 8724833f25ba..56fdfd6c5a78 100644
--- a/arch/arm/mach-mx5/mx50_arm2.c
+++ b/arch/arm/mach-mx5/mx50_arm2.c
@@ -1080,6 +1080,7 @@ static void __init mxc_board_init(void)
 	mx5_usbh1_init();
 
 	mxc_register_device(&mxc_rngb_device, NULL);
+	mxc_register_device(&dcp_device, NULL);
 }
 
 static void __init mx50_arm2_timer_init(void)