Colibri iMX6 dtb: add all not muxed pin as gpio

All pins not assigned to other functionality are muxed to be
gpio. This allows for later sysfs access to these pins.

Some USB OTG control signals are among the list as the driver for
these is not yet ready.

2 files changed, 131 insertions, 8 deletions

diff --git a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts
index 7fcff241ff8d..fbcf0e591cf7 100644
--- a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts
+++ b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts
@@ -147,19 +147,21 @@
 	};
 };
 
-#if 0 /* TODO */
 &iomuxc {
 	/*
-	 * Mux the Apalis GPIOs, GPIO7 used for PCIe reset,
-	 * GPIO5, 6 used by optional fusion_F0710A kernel module
+	 * Mux all pins which are unused to be GPIOs
+	 * so they are ready for export to user space
 	 */
 	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_apalis_gpio1 &pinctrl_apalis_gpio2
-		     &pinctrl_apalis_gpio3 &pinctrl_apalis_gpio4
-		     &pinctrl_apalis_gpio5 &pinctrl_apalis_gpio6
-		     &pinctrl_apalis_gpio7 &pinctrl_apalis_gpio8>;
+	pinctrl-0 = <&pinctrl_weim_gpio_1 &pinctrl_weim_gpio_2
+	             &pinctrl_weim_gpio_3 &pinctrl_weim_gpio_4
+	             &pinctrl_weim_gpio_5
+	             &pinctrl_csi_gpio_1
+	             &pinctrl_gpio_1
+	             &pinctrl_usbh_oc_1 &pinctrl_usbc_id_1
+	             &pinctrl_usbc_det_1>;
 };
-#endif
+
 &lcd {
 	status = "okay";
 };
diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/imx6qdl-colibri.dtsi
index b517f47beb3a..4b269547d8bf 100644
--- a/arch/arm/boot/dts/imx6qdl-colibri.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi
@@ -363,6 +363,61 @@
 				MX6QDL_PAD_RGMII_TD0__GPIO6_IO20	PAD_CTRL_HYS_PU /* STMPE811 interrupt */
 			>;
 		};
+		pinctrl_usbh_oc_1: usbh_oc-1 {
+			fsl,pins = <
+				/* USBH_OC */
+				MX6QDL_PAD_EIM_D30__GPIO3_IO30		PAD_CTRL_HYS_PU
+			>;
+		};
+		pinctrl_usbc_id_1: usbc_id-1 {
+			fsl,pins = <
+				/* USBC_ID */
+				MX6QDL_PAD_NANDF_D2__GPIO2_IO02		PAD_CTRL_HYS_PU
+			>;
+		};
+		pinctrl_usbc_det_1: usbc_det-1 {
+			fsl,pins = <
+				/* USBC_DET */
+				MX6QDL_PAD_GPIO_17__GPIO7_IO12		PAD_CTRL_HYS_PU
+			>;
+		};
+	};
+	csi {
+		/* CSI pins used as GPIO */
+		pinctrl_csi_gpio_1: csi_gpio-1 {
+			fsl,pins = <
+				MX6QDL_PAD_EIM_A24__GPIO5_IO04   PAD_CTRL_HYS_PU
+				MX6QDL_PAD_SD2_CMD__GPIO1_IO11   PAD_CTRL_HYS_PU
+				MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 PAD_CTRL_HYS_PU
+				MX6QDL_PAD_EIM_D18__GPIO3_IO18   PAD_CTRL_HYS_PU
+				MX6QDL_PAD_EIM_A19__GPIO2_IO19   PAD_CTRL_HYS_PU
+				MX6QDL_PAD_EIM_D29__GPIO3_IO29   PAD_CTRL_HYS_PD
+				MX6QDL_PAD_EIM_A23__GPIO6_IO06   PAD_CTRL_HYS_PU
+				MX6QDL_PAD_EIM_A20__GPIO2_IO18   PAD_CTRL_HYS_PU
+				MX6QDL_PAD_EIM_A17__GPIO2_IO21   PAD_CTRL_HYS_PU
+				MX6QDL_PAD_EIM_A18__GPIO2_IO20   PAD_CTRL_HYS_PU
+				MX6QDL_PAD_EIM_EB3__GPIO2_IO31   PAD_CTRL_HYS_PU
+				MX6QDL_PAD_EIM_D17__GPIO3_IO17   PAD_CTRL_HYS_PU
+				MX6QDL_PAD_SD2_DAT0__GPIO1_IO15  PAD_CTRL_HYS_PU
+			>;
+		};
+	};
+	gpio {
+		pinctrl_gpio_1: gpio-1 {
+			fsl,pins = <
+				MX6QDL_PAD_GPIO_7__GPIO1_IO07       PAD_CTRL_HYS_PU
+				MX6QDL_PAD_GPIO_8__GPIO1_IO08       PAD_CTRL_HYS_PU
+				MX6QDL_PAD_EIM_D26__GPIO3_IO26      PAD_CTRL_HYS_PU
+				MX6QDL_PAD_EIM_D27__GPIO3_IO27      PAD_CTRL_HYS_PU
+				MX6QDL_PAD_NANDF_D6__GPIO2_IO06     PAD_CTRL_HYS_PU
+				MX6QDL_PAD_NANDF_D3__GPIO2_IO03     PAD_CTRL_HYS_PU
+				MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 PAD_CTRL_HYS_PU
+				MX6QDL_PAD_DI0_PIN4__GPIO4_IO20     PAD_CTRL_HYS_PU
+				MX6QDL_PAD_SD4_DAT3__GPIO2_IO11     PAD_CTRL_HYS_PU
+				MX6QDL_PAD_NANDF_D4__GPIO2_IO04     PAD_CTRL_HYS_PU
+				MX6QDL_PAD_SD4_DAT0__GPIO2_IO08     PAD_CTRL_HYS_PU
+			>;
+		};
 	};
 	weim {
 		pinctrl_weim_cs1_1: weim_cs1grp-1 {
@@ -415,6 +470,72 @@
 				MX6QDL_PAD_EIM_DA0__EIM_AD00   0xb0b1
 			>;
 		};
+		/* ADDRESS[16:18] [25] used as GPIO */
+		pinctrl_weim_gpio_1: weim_gpio-1 {
+			fsl,pins = <
+				MX6QDL_PAD_KEY_ROW4__GPIO4_IO15    PAD_CTRL_HYS_PU
+				MX6QDL_PAD_KEY_ROW2__GPIO4_IO11    PAD_CTRL_HYS_PU
+				MX6QDL_PAD_KEY_COL2__GPIO4_IO10    PAD_CTRL_HYS_PU
+				MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 PAD_CTRL_HYS_PU
+				MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 PAD_CTRL_HYS_PU
+				MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 PAD_CTRL_HYS_PU
+				MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 PAD_CTRL_HYS_PU
+				MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 PAD_CTRL_HYS_PU
+				MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 PAD_CTRL_HYS_PU
+				MX6QDL_PAD_NANDF_D1__GPIO2_IO01    PAD_CTRL_HYS_PU
+			>;
+		};
+		/* ADDRESS[19:24] used as GPIO */
+		pinctrl_weim_gpio_2: weim_gpio-2 {
+			fsl,pins = <
+				MX6QDL_PAD_KEY_ROW4__GPIO4_IO15    PAD_CTRL_HYS_PU
+				MX6QDL_PAD_KEY_ROW2__GPIO4_IO11    PAD_CTRL_HYS_PU
+				MX6QDL_PAD_KEY_COL2__GPIO4_IO10    PAD_CTRL_HYS_PU
+				MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 PAD_CTRL_HYS_PU
+				MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 PAD_CTRL_HYS_PU
+				MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 PAD_CTRL_HYS_PU
+				MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 PAD_CTRL_HYS_PU
+				MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 PAD_CTRL_HYS_PU
+				MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 PAD_CTRL_HYS_PU
+				MX6QDL_PAD_NANDF_D1__GPIO2_IO01    PAD_CTRL_HYS_PU
+			>;
+		};
+		/* DATA[16:31]  used as GPIO */
+		pinctrl_weim_gpio_3: weim_gpio-3 {
+			fsl,pins = <
+				MX6QDL_PAD_EIM_LBA__GPIO2_IO27     PAD_CTRL_HYS_PU
+				MX6QDL_PAD_EIM_BCLK__GPIO6_IO31    PAD_CTRL_HYS_PU
+				MX6QDL_PAD_NANDF_CS3__GPIO6_IO16   PAD_CTRL_HYS_PU
+				MX6QDL_PAD_NANDF_CS1__GPIO6_IO14   PAD_CTRL_HYS_PU
+				MX6QDL_PAD_NANDF_RB0__GPIO6_IO10   PAD_CTRL_HYS_PU
+				MX6QDL_PAD_NANDF_ALE__GPIO6_IO08   PAD_CTRL_HYS_PU
+				MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09  PAD_CTRL_HYS_PU
+				MX6QDL_PAD_NANDF_CS0__GPIO6_IO11   PAD_CTRL_HYS_PU
+				MX6QDL_PAD_NANDF_CLE__GPIO6_IO07   PAD_CTRL_HYS_PU
+				MX6QDL_PAD_GPIO_19__GPIO4_IO05     PAD_CTRL_HYS_PU
+				MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19   PAD_CTRL_HYS_PU
+				MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 PAD_CTRL_HYS_PU
+				MX6QDL_PAD_GPIO_4__GPIO1_IO04      PAD_CTRL_HYS_PU
+				MX6QDL_PAD_GPIO_5__GPIO1_IO05      PAD_CTRL_HYS_PU
+				MX6QDL_PAD_KEY_COL4__GPIO4_IO14    PAD_CTRL_HYS_PU
+				MX6QDL_PAD_GPIO_2__GPIO1_IO02      PAD_CTRL_HYS_PU
+			>;
+		};
+		/* DQM[0:3]  used as GPIO */
+		pinctrl_weim_gpio_4: weim_gpio-4 {
+			fsl,pins = <
+				MX6QDL_PAD_EIM_EB0__GPIO2_IO28  PAD_CTRL_HYS_PU
+				MX6QDL_PAD_EIM_EB1__GPIO2_IO29  PAD_CTRL_HYS_PU
+				MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 PAD_CTRL_HYS_PU
+				MX6QDL_PAD_NANDF_D0__GPIO2_IO00 PAD_CTRL_HYS_PU
+			>;
+		};
+		/* RDY  used as GPIO */
+		pinctrl_weim_gpio_5: weim_gpio-5 {
+			fsl,pins = <
+				MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 PAD_CTRL_HYS_PU
+			>;
+		};
 	};
 };