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authorLei Wen <leiwen@marvell.com>2011-06-21 05:37:47 -0700
committerEric Miao <eric.y.miao@gmail.com>2011-07-06 23:51:36 +0800
commit6662498e132dfa758925a160fd5ef80a083651c3 (patch)
tree7f534aced1211babfa537d5b1c2e5ebbc7e4566b /arch
parentd204b2c5b16df935fa9a546c528e168859fddcc0 (diff)
ARM: pxa168: correct nand pmu setting
The original pair of <0x01db, 208000000> is invalid. Correct it to the valid value. The 6th bit of the NFC APMU register indicates NFC works whether at 156Mhz or 78Mhz. So 0x19b indicates NFC works at 156Mhz, and 0x1db indicates it works at 78Mhz. Signed-off-by: Lei Wen <leiwen@marvell.com> Cc: stable@kernel.org Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-mmp/pxa168.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c
index 72b4e7631583..ab9f999106c7 100644
--- a/arch/arm/mach-mmp/pxa168.c
+++ b/arch/arm/mach-mmp/pxa168.c
@@ -79,7 +79,7 @@ static APBC_CLK(ssp4, PXA168_SSP4, 4, 0);
static APBC_CLK(ssp5, PXA168_SSP5, 4, 0);
static APBC_CLK(keypad, PXA168_KPC, 0, 32000);
-static APMU_CLK(nand, NAND, 0x01db, 208000000);
+static APMU_CLK(nand, NAND, 0x19b, 156000000);
static APMU_CLK(lcd, LCD, 0x7f, 312000000);
/* device and clock bindings */