diff options
| author | Sandor Yu <R01008@freescale.com> | 2014-12-20 11:05:46 +0800 |
|---|---|---|
| committer | Robby Cai <r63905@freescale.com> | 2014-12-23 13:39:36 +0800 |
| commit | f1ae217b23ac348190dd41bbd488184d2ff8012b (patch) | |
| tree | 95df8adf0c63c32014010bfc1c76dde0becfdd57 /arch | |
| parent | 971603ebc49f11e6d7026e7c9a3d209297e2290b (diff) | |
MLK-10046: gpc: read GPC_CNTR before write to avoid bits overwrite
On imx6sx, bit 17 and bit18 will power off/on VADC directly,
so read GPC_CNTR firstly before write to avoid touching other bits.
Signed-off-by: Sandor Yu <R01008@freescale.com>
(cherry picked from commit ce70fc330c33dd33a73e2f1c8d00f29ec4d68b1d)
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-imx/gpc.c | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/arch/arm/mach-imx/gpc.c b/arch/arm/mach-imx/gpc.c index fc74dabdc0f1..52fa87215f05 100644 --- a/arch/arm/mach-imx/gpc.c +++ b/arch/arm/mach-imx/gpc.c @@ -133,12 +133,14 @@ static void imx_disp_clk(bool enable) static void imx_gpc_dispmix_on(void) { + u32 val = readl_relaxed(gpc_base + GPC_CNTR); + if ((cpu_is_imx6sl() && imx_get_soc_revision() >= IMX_CHIP_REVISION_1_2) || cpu_is_imx6sx()) { imx_disp_clk(true); writel_relaxed(0x0, gpc_base + GPC_PGC_DISP_PGCR_OFFSET); - writel_relaxed(0x20, gpc_base + GPC_CNTR); + writel_relaxed(0x20 | val, gpc_base + GPC_CNTR); while (readl_relaxed(gpc_base + GPC_CNTR) & 0x20) ; writel_relaxed(0x1, gpc_base + GPC_PGC_DISP_SR_OFFSET); @@ -149,6 +151,8 @@ static void imx_gpc_dispmix_on(void) static void imx_gpc_dispmix_off(void) { + u32 val = readl_relaxed(gpc_base + GPC_CNTR); + if ((cpu_is_imx6sl() && imx_get_soc_revision() >= IMX_CHIP_REVISION_1_2) || cpu_is_imx6sx()) { imx_disp_clk(true); @@ -158,7 +162,7 @@ static void imx_gpc_dispmix_off(void) writel_relaxed(0xFFFFFFFF, gpc_base + GPC_PGC_DISP_PDNSCR_OFFSET); writel_relaxed(0x1, gpc_base + GPC_PGC_DISP_PGCR_OFFSET); - writel_relaxed(0x10, gpc_base + GPC_CNTR); + writel_relaxed(0x10 | val, gpc_base + GPC_CNTR); while (readl_relaxed(gpc_base + GPC_CNTR) & 0x10) ; |