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author | Naveen Kumar S <nkumars@nvidia.com> | 2016-07-20 16:47:05 +0530 |
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committer | Matthew Pedro <mapedro@nvidia.com> | 2016-07-26 09:43:08 -0700 |
commit | 9a1e9a92e975274f4b3507922b7ab4805defe975 (patch) | |
tree | 564f621fa131072e6b0824411baa2e7e3dfc7de0 /block/elevator.c | |
parent | a7da876159f2b71ad411c31d08030be2e99dd417 (diff) |
video: tegra: hdmi: choose clk rate above 100MHz
pll_d2 runs at a minimum of 100MHz on T124. Update logic
to choose parent clock rate more than 100MHz.
e.g.: A mode with 32MHz pclk chooses parent clock of
96MHz with a divider of 3.0, which fails as pll_d
can't be pulled below 100MHz.
bug 1785365
Change-Id: I12400549a3ed42295ddd46adcb6493232f2d896a
Signed-off-by: Naveen Kumar S <nkumars@nvidia.com>
Reviewed-on: http://git-master/r/1184235
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Aly Hirani <ahirani@nvidia.com>
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Diffstat (limited to 'block/elevator.c')
0 files changed, 0 insertions, 0 deletions