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| author | Jiada Wang <jiada_wang@mentor.com> | 2019-02-25 12:14:20 +0100 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2019-02-26 11:43:18 +0000 |
| commit | 8af6c521cc236534093f9e744cfa004314bfe5ae (patch) | |
| tree | 143c5bfc4fd1b8a7d495016cd934f2eeee3e150c /crypto/poly1305_generic.c | |
| parent | f938f3485c385b9b5c796b2e93427c015a7d18fa (diff) | |
ASoC: rsnd: gen: fix SSI9 4/5/6/7 busif related register address
Currently each SSI unit 's busif mode/adinr/dalign address is
registered by: (in busif4 case)
RSND_GEN_M_REG(SSI_BUSIF4_MODE, 0x500, 0x80)
RSND_GEN_M_REG(SSI_BUSIF4_ADINR,0x504, 0x80)
RSND_GEN_M_REG(SSI_BUSIF4_DALIGN, 0x508, 0x80)
But according to user manual 41.1.4 Register Configuration
ssi9 4/5/6/7 busif mode/adinr/dalign register address
( SSI9-[4/5/6/7]_BUSIF_[MODE/ADINR/DALIGN] )
are out of this rule.
This patch registers ssi9 4/5/6/7 mode/adinr/dalign register
as single register, and access these registers in case of
SSI9 BUSIF 4/5/6/7.
Fixes: commit 8c9d75033340 ("ASoC: rsnd: ssiu: Support BUSIF other than BUSIF0")
Signed-off-by: Jiada Wang <jiada_wang@mentor.com>
Signed-off-by: Timo Wischer <twischer@de.adit-jv.com>
Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'crypto/poly1305_generic.c')
0 files changed, 0 insertions, 0 deletions