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| author | Venkata(Muni) Anda <muni@nvidia.com> | 2010-01-29 10:53:33 -0800 |
|---|---|---|
| committer | Venkata(Muni) Anda <muni@nvidia.com> | 2010-02-03 06:14:13 -0800 |
| commit | 2e054343da89c64413e5c08840fa7ce550a5e885 (patch) | |
| tree | 9b92984c00b0c77d8878d814a885810b9ad7a5c6 /crypto | |
| parent | 3d13613ce235128f6e7e9a46e74d3865b3a940f9 (diff) | |
tegra: Use write-combined DMA buffer for Tx DMA instead of zero-copy DMA.
Given the constraints of Tx DMA to only use the dword aligned buffer start
and dword aligned size, it would prudent to allocate a uncached DMA buffer
and copy the data to that buffer before the trasmit.
Main reason if Flushing L2 is not a cheap operation and the UART driver
model is having to do all the operations while holding the spin-lock
will not work.
Change-Id: I0ca14d5809258e2a62111f0a8a5e8a8053de1a34
Diffstat (limited to 'crypto')
0 files changed, 0 insertions, 0 deletions