diff options
| author | Aniruddha Banerjee <aniruddhab@nvidia.com> | 2018-03-28 19:12:00 +0530 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2018-04-24 09:34:12 +0200 |
| commit | 910d84009977441fcb5661683528f88ed1dcca93 (patch) | |
| tree | d81975462a5784c3dcaeff37c12416247873bba1 /drivers/char | |
| parent | c9bb6fb2df18eda60e8dc125232338a76ffb7163 (diff) | |
irqchip/gic: Take lock when updating irq type
commit aa08192a254d362a4d5317647a81de6996961aef upstream.
Most MMIO GIC register accesses use a 1-hot bit scheme that
avoids requiring any form of locking. This isn't true for the
GICD_ICFGRn registers, which require a RMW sequence.
Unfortunately, we seem to be missing a lock for these particular
accesses, which could result in a race condition if changing the
trigger type on any two interrupts within the same set of 16
interrupts (and thus controlled by the same CFGR register).
Introduce a private lock in the GIC common comde for this
particular case, making it cover both GIC implementations
in one go.
Cc: stable@vger.kernel.org
Signed-off-by: Aniruddha Banerjee <aniruddhab@nvidia.com>
[maz: updated changelog]
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/char')
0 files changed, 0 insertions, 0 deletions