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| author | Stefan Agner <stefan.agner@toradex.com> | 2019-06-03 10:59:09 +0200 |
|---|---|---|
| committer | Stefan Agner <stefan.agner@toradex.com> | 2019-06-03 10:59:09 +0200 |
| commit | 2115c1bc6e396d5ffe9ecbe394d1c50a6e25c404 (patch) | |
| tree | 20fff445991414f23c0a29237940b75cd756de86 /drivers/clk/hisilicon/clk-hi3660.c | |
| parent | b794ea49ba3816c0d5cf05506964a8e69ce4efa3 (diff) | |
| parent | 3f7c1cab1a61108821cf47dda8a32ed25cc3588b (diff) | |
Merge tag 'v5.0.19' into toradex_5.0.ytoradex_5.0.y
This is the 5.0.19 stable release
Diffstat (limited to 'drivers/clk/hisilicon/clk-hi3660.c')
| -rw-r--r-- | drivers/clk/hisilicon/clk-hi3660.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/drivers/clk/hisilicon/clk-hi3660.c b/drivers/clk/hisilicon/clk-hi3660.c index f40419959656..794eeff0d5d2 100644 --- a/drivers/clk/hisilicon/clk-hi3660.c +++ b/drivers/clk/hisilicon/clk-hi3660.c @@ -163,8 +163,12 @@ static const struct hisi_gate_clock hi3660_crgctrl_gate_sep_clks[] = { "clk_isp_snclk_mux", CLK_SET_RATE_PARENT, 0x50, 17, 0, }, { HI3660_CLK_GATE_ISP_SNCLK2, "clk_gate_isp_snclk2", "clk_isp_snclk_mux", CLK_SET_RATE_PARENT, 0x50, 18, 0, }, + /* + * clk_gate_ufs_subsys is a system bus clock, mark it as critical + * clock and keep it on for system suspend and resume. + */ { HI3660_CLK_GATE_UFS_SUBSYS, "clk_gate_ufs_subsys", "clk_div_sysbus", - CLK_SET_RATE_PARENT, 0x50, 21, 0, }, + CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0x50, 21, 0, }, { HI3660_PCLK_GATE_DSI0, "pclk_gate_dsi0", "clk_div_cfgbus", CLK_SET_RATE_PARENT, 0x50, 28, 0, }, { HI3660_PCLK_GATE_DSI1, "pclk_gate_dsi1", "clk_div_cfgbus", |