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authorAnson Huang <Anson.Huang@nxp.com>2016-05-31 00:34:55 +0800
committerLeonard Crestez <leonard.crestez@nxp.com>2018-08-24 12:41:33 +0300
commit40bff27a27fb6c993953a1155b25603703c9833f (patch)
tree6d283855cb36cc840e1728c3730bcb6dc810a8bf /drivers/clk/imx/clk-gate2.c
parentb81a249c8bbeb2d62c14a2a0cbb406ea125666a5 (diff)
MLK-12861-1 ARM: imx: support runtime clock management on i.mx7d when M4 is enabled
For i.MX7D, current runtime clock management code will skip all PLL/PFD/GATE enable/disable when M4 is enabled, this is NOT good for power number in low power idle and audio playback, as M4 only uses one high speed PFD which is from system PLL, it is never disabled runtimely, so we can just enable the hardware operation of PLL/PFD/GATE for A7. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> (cherry picked from commit 02a2e8d73bcb8d2b8362b4328976dfcdc502a19c)
Diffstat (limited to 'drivers/clk/imx/clk-gate2.c')
-rw-r--r--drivers/clk/imx/clk-gate2.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/imx/clk-gate2.c b/drivers/clk/imx/clk-gate2.c
index effcd482b82c..b9bd5938d44a 100644
--- a/drivers/clk/imx/clk-gate2.c
+++ b/drivers/clk/imx/clk-gate2.c
@@ -59,7 +59,7 @@ static void clk_gate2_do_shared_clks(struct clk_hw *hw, bool enable)
{
struct clk_gate2 *gate = to_clk_gate2(hw);
- if (imx_src_is_m4_enabled()) {
+ if (imx_src_is_m4_enabled() && clk_on_imx6sx()) {
#ifdef CONFIG_SOC_IMX6SX
if (!amp_power_mutex || !shared_mem) {
if (enable)