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author | Otavio Salvador <otavio@ossystems.com.br> | 2019-03-28 10:47:24 -0300 |
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committer | GitHub <noreply@github.com> | 2019-03-28 10:47:24 -0300 |
commit | 0a8ab17689e628c84a666195bfc6ab85d11cf057 (patch) | |
tree | 01630dc4a6935df99bf7d11d34ff8d384fed86e2 /drivers/clk/imx/clk-imx6q.c | |
parent | 1e71d8c630cbc0d1f5d762fd019690b5cdb880ae (diff) | |
parent | 32aca03c2ce868d3412da0bb6ce6798c7bea357e (diff) |
Merge pull request #46 from toradex/4.9-2.3.x-imx
4.9 2.3.x imx
Diffstat (limited to 'drivers/clk/imx/clk-imx6q.c')
-rw-r--r-- | drivers/clk/imx/clk-imx6q.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c index 8cde9cc32798..3d918b281927 100644 --- a/drivers/clk/imx/clk-imx6q.c +++ b/drivers/clk/imx/clk-imx6q.c @@ -588,8 +588,12 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) * lvds1_gate and lvds2_gate are pseudo-gates. Both can be * independently configured as clock inputs or outputs. We treat * the "output_enable" bit as a gate, even though it's really just - * enabling clock output. + * enabling clock output. Initially the gate bits are cleared, as + * otherwise the exclusive configuration gets locked in the setup done + * by software running before the clock driver, with no way to change + * it. */ + writel(readl(base + 0x160) & ~0x3c00, base + 0x160); clk[IMX6QDL_CLK_LVDS1_GATE] = imx_clk_gate_exclusive("lvds1_gate", "lvds1_sel", base + 0x160, 10, BIT(12)); clk[IMX6QDL_CLK_LVDS2_GATE] = imx_clk_gate_exclusive("lvds2_gate", "lvds2_sel", base + 0x160, 11, BIT(13)); |