diff options
| author | Shengjiu Wang <shengjiu.wang@freescale.com> | 2015-01-27 16:44:34 +0800 |
|---|---|---|
| committer | Leonard Crestez <leonard.crestez@nxp.com> | 2018-08-23 16:57:55 +0300 |
| commit | 20aa4bd4fdfe907731106f668ccbce5a916ad714 (patch) | |
| tree | 51d02f1fb0ca0519440471baac277a122a7aab74 /drivers/clk/imx/clk-imx6sx.c | |
| parent | ba818e86632bde84c021f6cb10151736417134c0 (diff) | |
MLK-10161-3: ARM: imx6sx: Add SPDIF_GCLK clock in clock tree
As spdif driver will register SPDIF clock to regmap, regmap will do
clk_prepare in init function, so SPDIF clock is prepared in probe, then its
root clock (pll clock) is prepared also, which cause the arm can't enter
low power mode.
Add SPDIF_GCLK in clock tree which share same gate bits with SPDIF clock.
Its root clock is ipg clock, and register it to regmap, then the issue can be
fixed.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
(cherry picked from commit 3f8999cdb4fabed4f720c6ee23947e19c8fff83f)
Diffstat (limited to 'drivers/clk/imx/clk-imx6sx.c')
| -rw-r--r-- | drivers/clk/imx/clk-imx6sx.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/imx/clk-imx6sx.c b/drivers/clk/imx/clk-imx6sx.c index e045ca91a680..a0f2fe5c958e 100644 --- a/drivers/clk/imx/clk-imx6sx.c +++ b/drivers/clk/imx/clk-imx6sx.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2014 Freescale Semiconductor, Inc. + * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. * * The code contained herein is licensed under the GNU General Public * License. You may obtain a copy of the GNU General Public License |