diff options
| author | Peter Chen <peter.chen@nxp.com> | 2016-11-21 14:51:27 +0800 |
|---|---|---|
| committer | Leonard Crestez <leonard.crestez@nxp.com> | 2018-08-24 12:41:33 +0300 |
| commit | 5e9a61fc30100b515e338fff505f8e6a8d93d752 (patch) | |
| tree | 7556502e174aba31ccd1eef87b416e93d18b7b85 /drivers/clk/imx/clk-imx7ulp.c | |
| parent | 91e7adf3c940913b131df48b24a39828292a5fc3 (diff) | |
MLK-13485-4 clk: imx7ulp: add gpio port control clocks
Add gpio port control clocks, and add them to init table.
If the gpio clock is controlled by gpio driver, the watchdog
reset will occur due to unknown reason, we need to debug it
if we need driver to control its clocks.
Signed-off-by: Peter Chen <peter.chen@nxp.com>
Diffstat (limited to 'drivers/clk/imx/clk-imx7ulp.c')
| -rw-r--r-- | drivers/clk/imx/clk-imx7ulp.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/clk/imx/clk-imx7ulp.c b/drivers/clk/imx/clk-imx7ulp.c index 0804bef253e4..c55770f8d120 100644 --- a/drivers/clk/imx/clk-imx7ulp.c +++ b/drivers/clk/imx/clk-imx7ulp.c @@ -41,6 +41,10 @@ static int const clks_init_on[] __initconst = { IMX7ULP_CLK_NIC1_BUS_DIV, IMX7ULP_CLK_MMDC, IMX7ULP_CLK_RGPIO2P1, + IMX7ULP_CLK_PCTLC, + IMX7ULP_CLK_PCTLD, + IMX7ULP_CLK_PCTLE, + IMX7ULP_CLK_PCTLF, }; static void __init imx7ulp_clocks_init(struct device_node *scg_node) @@ -145,6 +149,10 @@ static void __init imx7ulp_clocks_init(struct device_node *scg_node) clks[IMX7ULP_CLK_LCDIF] = imx_clk_composite("lcdif", periph_plat_sels, ARRAY_SIZE(periph_plat_sels), true, true, true, base + 0xA8); clks[IMX7ULP_CLK_MMDC] = imx_clk_gate("mmdc", "nic1_div", base + 0xAC, 30); clks[IMX7ULP_CLK_GPU3D] = imx_clk_composite("gpu3d", periph_plat_sels, ARRAY_SIZE(periph_plat_sels), true, false, true, base + 0x140); + clks[IMX7ULP_CLK_PCTLC] = imx_clk_composite("pctlc", periph_slow_sels, ARRAY_SIZE(periph_slow_sels), true, false, true, base + 0xb8); + clks[IMX7ULP_CLK_PCTLD] = imx_clk_composite("pctld", periph_slow_sels, ARRAY_SIZE(periph_slow_sels), true, false, true, base + 0xbc); + clks[IMX7ULP_CLK_PCTLE] = imx_clk_composite("pctle", periph_slow_sels, ARRAY_SIZE(periph_slow_sels), true, false, true, base + 0xc0); + clks[IMX7ULP_CLK_PCTLF] = imx_clk_composite("pctlf", periph_slow_sels, ARRAY_SIZE(periph_slow_sels), true, false, true, base + 0xc4); clks[IMX7ULP_CLK_GPU2D] = imx_clk_composite("gpu2d", periph_plat_sels, ARRAY_SIZE(periph_plat_sels), true, false, true, base + 0x144); imx_check_clocks(clks, ARRAY_SIZE(clks)); |