diff options
| author | Fancy Fang <chen.fang@nxp.com> | 2018-06-06 10:41:07 +0800 |
|---|---|---|
| committer | Leonard Crestez <leonard.crestez@nxp.com> | 2018-08-24 12:41:33 +0300 |
| commit | 4f2ef223c1196510d563d11227d680ff8a9ec00f (patch) | |
| tree | 07177244cca300eab37eeb5fc97fe6d314931b06 /drivers/clk/imx | |
| parent | 6cd7d9c439ab0630bbe86def7252e3cd520836c3 (diff) | |
MLK-18535-2 clk: imx8mm: set video_pll1 rate to 594MHz
The 'video_pll1' PLL will be used as LCDIF pixel clock
source, and also used as MIPI DSI PHY reference clock
source. And 594MHz clock rate is better to derive the
27MHz PHY reference clock and the LCDIF pixel clocks
requied for most popular display modes.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Diffstat (limited to 'drivers/clk/imx')
| -rw-r--r-- | drivers/clk/imx/clk-imx8mm.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c index aa0931cba6d4..8ab6bc562073 100644 --- a/drivers/clk/imx/clk-imx8mm.c +++ b/drivers/clk/imx/clk-imx8mm.c @@ -919,6 +919,7 @@ static void __init imx8mm_clocks_init(struct device_node *ccm_node) /* increase NOC clock to design target */ clk_set_rate(clks[IMX8MM_SYS_PLL3], 750000000); + clk_set_rate(clks[IMX8MM_VIDEO_PLL1], 594000000); clk_set_parent(clks[IMX8MM_CLK_NOC_SRC], clks[IMX8MM_SYS_PLL3_OUT]); clk_set_parent(clks[IMX8MM_CLK_PCIE1_CTRL_SRC], clks[IMX8MM_SYS_PLL2_250M]); clk_set_parent(clks[IMX8MM_CLK_PCIE1_PHY_SRC], clks[IMX8MM_SYS_PLL2_100M]); |