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authorAndy Duan <fugang.duan@nxp.com>2018-08-09 14:29:09 +0800
committerLeonard Crestez <leonard.crestez@nxp.com>2018-08-24 12:41:33 +0300
commit651dd2acf5596aab596ab7c5f678ca28011f8c26 (patch)
tree85905159c20e25fb7bc1043655e4be2205c564a6 /drivers/clk/imx
parent48af9e5402eda6ca6f685176676c5e35a33fbf0e (diff)
MLK-19169 clk: imx8mm/mq: keep earlycon uart port clocks on during bootconsole enable period
Keep earlycon uart port clocks on during bootconsole enable period to avoid messy chars print out. Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Diffstat (limited to 'drivers/clk/imx')
-rw-r--r--drivers/clk/imx/Makefile8
-rw-r--r--drivers/clk/imx/clk-imx8.c1
-rw-r--r--drivers/clk/imx/clk-imx8mm.c16
-rw-r--r--drivers/clk/imx/clk-imx8mq.c10
4 files changed, 27 insertions, 8 deletions
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index 9e6431ed6f2e..d09bcea81ed7 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -33,7 +33,7 @@ obj-$(CONFIG_SOC_VF610) += clk-vf610.o
#
# IMX Clock specific Makefile
#
-obj-$(CONFIG_ARCH_FSL_IMX8QM) += clk-imx8qm.o clk-imx8.o clk-divider-scu.o clk-gate-scu.o clk-mux-scu.o
-obj-$(CONFIG_ARCH_FSL_IMX8QXP) += clk-imx8qxp.o clk-imx8.o clk-divider-scu.o clk-gate-scu.o clk-mux-scu.o
-obj-$(CONFIG_ARCH_FSL_IMX8MQ) += clk-imx8mq.o clk-frac-pll.o clk-sccg-pll.o clk-gate2.o
-obj-$(CONFIG_ARCH_FSL_IMX8MM) += clk-imx8mm.o clk-intpll.o clk-gate2.o clk-cpu.o
+obj-$(CONFIG_ARCH_FSL_IMX8QM) += clk.o clk-imx8qm.o clk-imx8.o clk-divider-scu.o clk-gate-scu.o clk-mux-scu.o
+obj-$(CONFIG_ARCH_FSL_IMX8QXP) += clk.o clk-imx8qxp.o clk-imx8.o clk-divider-scu.o clk-gate-scu.o clk-mux-scu.o
+obj-$(CONFIG_ARCH_FSL_IMX8MQ) += clk.o clk-imx8mq.o clk-frac-pll.o clk-sccg-pll.o clk-gate2.o
+obj-$(CONFIG_ARCH_FSL_IMX8MM) += clk.o clk-imx8mm.o clk-intpll.o clk-gate2.o clk-cpu.o
diff --git a/drivers/clk/imx/clk-imx8.c b/drivers/clk/imx/clk-imx8.c
index 73c94573bf64..fb5896a09b79 100644
--- a/drivers/clk/imx/clk-imx8.c
+++ b/drivers/clk/imx/clk-imx8.c
@@ -18,7 +18,6 @@
#include "clk-imx8.h"
-DEFINE_SPINLOCK(imx_ccm_lock);
sc_ipc_t ccm_ipc_handle;
int imx8_clk_mu_init(void)
diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
index 13a8abdb7cb0..e4e0c806b48b 100644
--- a/drivers/clk/imx/clk-imx8mm.c
+++ b/drivers/clk/imx/clk-imx8mm.c
@@ -379,6 +379,9 @@ static const char *imx8mm_vpu_h1_sels[] = {"osc_24m", "vpu_pll_out", "sys_pll1_8
static const char *imx8mm_dram_core_sels[] = {"dram_pll_out", "dram_alt_root", };
+static struct clk *clks[IMX8MM_CLK_END];
+static struct clk_onecell_data clk_data;
+
static int const clks_init_on[] __initconst = {
IMX8MM_CLK_AHB_CG, IMX8MM_CLK_DRAM_CORE,
IMX8MM_CLK_NOC_CG, IMX8MM_CLK_NOC_APB_CG,
@@ -389,12 +392,17 @@ static int const clks_init_on[] __initconst = {
IMX8MM_CLK_DISP_APB_CG,
};
+static struct clk ** const uart_clks[] __initconst = {
+ &clks[IMX8MM_CLK_UART1_ROOT],
+ &clks[IMX8MM_CLK_UART2_ROOT],
+ &clks[IMX8MM_CLK_UART3_ROOT],
+ &clks[IMX8MM_CLK_UART4_ROOT],
+ NULL
+};
+
static const char *imx8mm_clko1_sels[] = {"osc_24m", "sys_pll1_800m", "osc_27m", "sys_pll1_200m", "audio_pll2_clk",
"vpu_pll", "sys_pll1_80m", };
-static struct clk *clks[IMX8MM_CLK_END];
-static struct clk_onecell_data clk_data;
-
static int __init imx_clk_init_on(struct device_node *np,
struct clk * const clks[])
{
@@ -967,6 +975,8 @@ static void __init imx8mm_clocks_init(struct device_node *ccm_node)
clk_set_parent(clks[IMX8MM_CLK_DISP_APB_SRC], clks[IMX8MM_SYS_PLL1_800M]);
clk_set_rate(clks[IMX8MM_CLK_DISP_APB_PRE_DIV], 200000000);
+ imx_register_uart_clocks(uart_clks);
+
pr_info("i.MX8MM clock driver init done\n");
}
diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c
index 5eca458bad34..9151efccf0be 100644
--- a/drivers/clk/imx/clk-imx8mq.c
+++ b/drivers/clk/imx/clk-imx8mq.c
@@ -286,6 +286,14 @@ static int const clks_init_on[] __initconst = {
IMX8MQ_CLK_DRAM_APB_DIV,
};
+static struct clk ** const uart_clks[] __initconst = {
+ &clks[IMX8MQ_CLK_UART1_ROOT],
+ &clks[IMX8MQ_CLK_UART2_ROOT],
+ &clks[IMX8MQ_CLK_UART3_ROOT],
+ &clks[IMX8MQ_CLK_UART4_ROOT],
+ NULL
+};
+
static struct clk_onecell_data clk_data;
static int __init imx_clk_init_on(struct device_node *np,
@@ -893,6 +901,8 @@ static void __init imx8mq_clocks_init(struct device_node *ccm_node)
clk_set_parent(clks[IMX8MQ_CLK_CSI2_PHY_REF_SRC], clks[IMX8MQ_SYS2_PLL_1000M]);
clk_set_parent(clks[IMX8MQ_CLK_CSI2_ESC_SRC], clks[IMX8MQ_SYS1_PLL_800M]);
+ imx_register_uart_clocks(uart_clks);
+
pr_info("i.MX8MQ clock driver init done\n");
}