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authorSean Wang <sean.wang@mediatek.com>2017-10-05 11:50:24 +0800
committerStephen Boyd <sboyd@codeaurora.org>2017-11-02 01:10:12 -0700
commit2fc0a509e4ee858a450f28a4efb430835004dd70 (patch)
tree2030b145fe76a8684ba701fc449ddae56844113c /drivers/clk/mediatek/Makefile
parentbda921fad518b4d5d2249d41432025ce5b368173 (diff)
clk: mediatek: add clock support for MT7622 SoC
Add all supported clocks exported from every susbystem found on MT7622 SoC such as topckgen, apmixedsys, infracfg, pericfg , pciessys, ssusbsys, ethsys and audsys. Signed-off-by: Chen Zhong <chen.zhong@mediatek.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/mediatek/Makefile')
-rw-r--r--drivers/clk/mediatek/Makefile4
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index a4e5c47c73a4..de8c3d0bb4ca 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -20,5 +20,9 @@ obj-$(CONFIG_COMMON_CLK_MT2712_MFGCFG) += clk-mt2712-mfg.o
obj-$(CONFIG_COMMON_CLK_MT2712_MMSYS) += clk-mt2712-mm.o
obj-$(CONFIG_COMMON_CLK_MT2712_VDECSYS) += clk-mt2712-vdec.o
obj-$(CONFIG_COMMON_CLK_MT2712_VENCSYS) += clk-mt2712-venc.o
+obj-$(CONFIG_COMMON_CLK_MT7622) += clk-mt7622.o
+obj-$(CONFIG_COMMON_CLK_MT7622_ETHSYS) += clk-mt7622-eth.o
+obj-$(CONFIG_COMMON_CLK_MT7622_HIFSYS) += clk-mt7622-hif.o
+obj-$(CONFIG_COMMON_CLK_MT7622_AUDSYS) += clk-mt7622-aud.o
obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o
obj-$(CONFIG_COMMON_CLK_MT8173) += clk-mt8173.o