diff options
| author | Heiko Stübner <heiko@sntech.de> | 2014-10-30 14:26:13 +0100 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2014-11-07 23:41:14 +0100 |
| commit | d1f931be7cfb5458d90a4642fda8b4da6b266a84 (patch) | |
| tree | 10950f481d91f174ce40f1e3fadaeba39265ab05 /drivers/clk/rockchip | |
| parent | 78eaf6095cc763c1a228ebac5682852f04e85205 (diff) | |
clk: rockchip: fix rk3188 hsadc_frac definition
The arguments to COMPOSITE_FRAC for hsadc_frac were mangled, leaving out the
the general clock flags argument. This results in strange effects, as only
sometimes a zero-division is reported as the wrong register is read.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'drivers/clk/rockchip')
| -rw-r--r-- | drivers/clk/rockchip/clk-rk3188.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/clk/rockchip/clk-rk3188.c b/drivers/clk/rockchip/clk-rk3188.c index 4dfd5e249347..f88eb7dacd97 100644 --- a/drivers/clk/rockchip/clk-rk3188.c +++ b/drivers/clk/rockchip/clk-rk3188.c @@ -320,9 +320,9 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = { COMPOSITE(0, "hsadc_src", mux_pll_src_gpll_cpll_p, 0, RK2928_CLKSEL_CON(22), 0, 1, MFLAGS, 8, 8, DFLAGS, RK2928_CLKGATE_CON(2), 6, GFLAGS), - COMPOSITE_FRAC(0, "hsadc_frac", "hsadc_src", + COMPOSITE_FRAC(0, "hsadc_frac", "hsadc_src", 0, RK2928_CLKSEL_CON(23), 0, - RK2928_CLKGATE_CON(2), 7, 0, GFLAGS), + RK2928_CLKGATE_CON(2), 7, GFLAGS), MUX(SCLK_HSADC, "sclk_hsadc", mux_sclk_hsadc_p, 0, RK2928_CLKSEL_CON(22), 4, 2, MFLAGS), |