diff options
| author | Matthew Leach <matthew@mattleach.net> | 2016-06-08 19:30:58 +0100 |
|---|---|---|
| committer | Sylwester Nawrocki <s.nawrocki@samsung.com> | 2016-06-10 11:58:42 +0200 |
| commit | 21a5560b5dfc79ec03335280e68e6c2d3f1528b1 (patch) | |
| tree | bb14fa096ee8cfd867873d24cfe6fb56f67af490 /drivers/clk/samsung | |
| parent | 4de103397bed108212ac8e382d9285eb6b2700bd (diff) | |
clk: samsung: exynos4: fixup reg access on be
Use the byte-order aware big endian accessors, allowing for kernels
running under big-endian.
Signed-off-by: Matthew Leach <matthew@mattleach.net>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Diffstat (limited to 'drivers/clk/samsung')
| -rw-r--r-- | drivers/clk/samsung/clk-exynos4.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index 13eaf4cb0dbc..faab9b31baf5 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c @@ -1375,12 +1375,12 @@ static void __init exynos4x12_core_down_clock(void) if (num_possible_cpus() == 4) tmp |= PWR_CTRL1_USE_CORE3_WFE | PWR_CTRL1_USE_CORE2_WFE | PWR_CTRL1_USE_CORE3_WFI | PWR_CTRL1_USE_CORE2_WFI; - __raw_writel(tmp, reg_base + PWR_CTRL1); + writel_relaxed(tmp, reg_base + PWR_CTRL1); /* * Disable the clock up feature in case it was enabled by bootloader. */ - __raw_writel(0x0, reg_base + E4X12_PWR_CTRL2); + writel_relaxed(0x0, reg_base + E4X12_PWR_CTRL2); } #define E4210_CPU_DIV0(apll, pclk_dbg, atb, periph, corem1, corem0) \ |