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authorLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>2014-01-07 17:47:53 +0100
committerMike Turquette <mturquette@linaro.org>2014-02-18 21:41:03 -0800
commit8510e7263ad9399e771e0f67517a0d5409390445 (patch)
tree81968568188367467a70de0f3bbe9b9a49b9a3a0 /drivers/clk/shmobile
parent995a9190ac9ca85cc15d11d9566017e91c58a118 (diff)
clk: shmobile: rcar-gen2: Fix qspi divisor
The qspi clock divisor is incorrectly set to twice the value it should have, possibly because it has been computed based on PLL1 as the clock parent instead of PLL1 / 2 (the datasheets specifies the qspi nominal frequencies, not the divisor values). Fix it. Reported-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Tested-by: Geert Uytterhoeven <geert@linux-m68k.org> Acked-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Mike Turquette <mturquette@linaro.org>
Diffstat (limited to 'drivers/clk/shmobile')
-rw-r--r--drivers/clk/shmobile/clk-rcar-gen2.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/shmobile/clk-rcar-gen2.c b/drivers/clk/shmobile/clk-rcar-gen2.c
index 8c7bcbd727df..dd272a0d1446 100644
--- a/drivers/clk/shmobile/clk-rcar-gen2.c
+++ b/drivers/clk/shmobile/clk-rcar-gen2.c
@@ -215,7 +215,7 @@ rcar_gen2_cpg_register_clock(struct device_node *np, struct rcar_gen2_cpg *cpg,
} else if (!strcmp(name, "qspi")) {
parent_name = "pll1_div2";
div = (cpg_mode & (BIT(3) | BIT(2) | BIT(1))) == BIT(2)
- ? 16 : 20;
+ ? 8 : 10;
} else if (!strcmp(name, "sdh")) {
parent_name = "pll1_div2";
table = cpg_sdh_div_table;