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authorChen-Yu Tsai <wens@csie.org>2015-12-05 21:16:43 +0800
committerMaxime Ripard <maxime.ripard@free-electrons.com>2015-12-08 11:05:27 +0100
commit3cdd9f5c4953465abb87ec757159cc0576ae6b0a (patch)
tree9304b707c35d6f0e650ecf7e97cfbaa7098382a9 /drivers/clk/sunxi/Makefile
parentab6e23a4e388f5f2696b8e92c350f845142da118 (diff)
clk: sunxi: Add VE (Video Engine) module clock driver for sun[457]i
The video engine has its own special module clock, consisting of a clock gate, configurable dividers, and a reset control. On later (sun[68]i) families, the reset control is moved out of this piece of hardware and grouped with reset controls of other peripherals. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Tested-by: Jens Kuske <jenskuske@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'drivers/clk/sunxi/Makefile')
-rw-r--r--drivers/clk/sunxi/Makefile1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
index abf4916f1f97..1a909f9024eb 100644
--- a/drivers/clk/sunxi/Makefile
+++ b/drivers/clk/sunxi/Makefile
@@ -7,6 +7,7 @@ obj-y += clk-a10-codec.o
obj-y += clk-a10-hosc.o
obj-y += clk-a10-mod1.o
obj-y += clk-a10-pll2.o
+obj-y += clk-a10-ve.o
obj-y += clk-a20-gmac.o
obj-y += clk-mod0.o
obj-y += clk-simple-gates.o